WO2010047328A1

WO2010047328A1 - Semiconductor memory device

Info

Publication number: WO2010047328A1
Application number: PCT/JP2009/068064
Authority: WO
Inventors: 竜介根橋; 昇崎村; 直彦杉林; 弘明本庄
Original assignee: 日本電気株式会社
Priority date: 2008-10-23
Filing date: 2009-10-20
Publication date: 2010-04-29
Also published as: JP5565704B2; JPWO2010047328A1

Abstract

A semiconductor memory device has a memory array provided with a plurality of memory cells. The plurality of memory cells comprise first memory cells and third memory cells arranged along either the even rows or the odd rows, and second memory cells arranged along the other. Each of the plurality of memory cells includes a magnetoresistive element connected by one terminal to cell internal wiring, and has convex parts including the cell internal wiring in the center portion on at least one of the sides along the row direction. The convex parts of the second memory cells are arranged opposite concave parts formed between the convex parts of the first memory cells and the convex parts of the third memory cells.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which a magnetoresistive element (MTJ: Magnetic Tunnel Junction) is introduced into a memory cell as a memory element, that is, a magnetic random access memory (MRAM).

An MTJ element used for an MRAM memory cell includes a fixed magnetic layer, a free magnetic layer, and a tunnel insulating film. In the fixed magnetic layer, the magnetization direction is fixed in an arbitrary direction. In the free magnetic layer, the direction of magnetization is variable by an external magnetic field. The tunnel insulating film is sandwiched between these two magnetic layers. In MRAM, 1-bit stored information is assigned to the relative magnetization state between the fixed magnetic layer and the free magnetic layer. For example, it is defined as “0” when the magnetization of the pinned magnetic layer and the magnetization of the free magnetic layer are in the same direction, that is, in a parallel state. When the magnetization of the pinned magnetic layer and the magnetization of the free magnetic layer are different from each other by 180 degrees, that is, in the antiparallel state, it is defined as “1”. Further, reading of the MRAM is performed by utilizing the fact that the resistance value of the MTJ element varies depending on the magnetization state. FIG. 1 is a schematic diagram illustrating the writing principle of a typical MRAM. A write current Ix is supplied to a write word line extending parallel to the easy axis of magnetization of the magnetic layer, and a write current Iy is supplied to a write bit line extending perpendicular to the easy axis of magnetization. As a result, the magnetization of the free magnetic layer (cell A) is reversed by the combined magnetic field generated by these write currents. As described above, the memory cell is selected and the write operation is performed using the magnetization reversal characteristics of the MTJ element. FIG. 2 is a graph showing the relationship between the write current and the write margin. The vertical axis represents the write current Ix, and the horizontal axis represents the write current Iy. The write current has a lower limit and an upper limit (indicated by “operation margin” in the figure). The write margin is narrow. Therefore, in order to selectively write to the selected memory cell (cell A), it is necessary to accurately control the current value and current waveform. Therefore, the current source circuit becomes complicated, and it is difficult to perform a high-speed write operation of 100 MHz or higher.

A memory cell (2-Transistor-1-MTJ element type memory cell: 2T1MTJ cell) in which a write current is electrically selected by a transistor or a diode is introduced in Japanese Patent Application Laid-Open No. 2004-348934 (US2004100835 (A1)). . FIG. 3 is a schematic diagram showing the configuration of the 2T1MTJ cell in Japanese Patent Application Laid-Open No. 2004-348934. As shown in FIG. 3, the 2T1MTJ cell is placed directly above the write line 115, the transistor 111 that connects the bit line BL and the write line 115, the transistor 112 that connects the bit line / BL and the write line 115, and the like. The MTJ element 113 is formed. In the write operation, the word line WL of the selected memory cell is activated and the

transistors

111 and 112 are turned on. As a result, the write current Iw flowing through the bit lines BL and / BL flows through the write line 115. At this time, the magnetization of the MTJ element 113 is reversed by the write magnetic field Hw generated by the write current Iw. However, these wirings are formed in a wiring layer sufficiently far from the MTJ element 113 so that the magnetic field generated by the write current flowing only in the bit lines BL and / BL instead of the write line 115 does not reverse the magnetization of the MTJ element 113. Is done. For example, when the MTJ element 113 is formed between a three-layer wiring and a four-layer wiring, the one-layer wiring may be used as a bit line. Thus, since the write magnetic field Hw is not supplied to the non-selected memory cells, there is no half-selected state. Therefore, in the writing method using the 2T1MTJ cell, the selectivity of the memory cell at the time of writing is dramatically improved, and it is not necessary to accurately control the write current value and the current waveform. Therefore, the write circuit can be simplified by a logic circuit such as an SRAM decoder, and a high-speed write operation at the GHz level can be performed.

A configuration of an MRAM aimed at realizing a high-speed read operation is disclosed in Japanese Patent Application Laid-Open No. 2002-197852 (US 6,349,054 (B1)). According to this, a memory array is configured by even-numbered memory cells connected to the bit line BL and odd-numbered memory cells connected to the bit line / BL. Similarly, dummy cells (equivalent to the above-described reference cells) used as a read determination criterion are also provided in the even rows and the odd rows, respectively. The dummy cell holds an intermediate resistance value between the resistance value Rlow of data “0” and the resistance value Rhigh of data “1”. When even-numbered memory cells are selected, odd-numbered dummy cells are used, and when odd-numbered memory cells are selected, even-numbered dummy cells are used. According to this technique, the load capacitances of the bit line BL and the bit line / BL become equal, and the reading time can be increased. However, since the write method uses the same method as the conventional MRAM shown in FIG. 1, the operation speed, that is, the random access time is limited by a write time of 10 ns or more. Also, the cell area becomes larger than when memory cells are arranged in a matrix.

As described above, it is not easy to increase the operation speed (random access time) of the MRAM as high as that of the SRAM. For example, when a memory array based on the idea described in Japanese Patent Laid-Open No. 2002-197852 is configured using 2T1MTJ cells described in Japanese Patent Application Laid-Open No. 2004-348934, the cell area is approximately doubled, Not right. A semiconductor memory device (eg, MRAM) using a magnetoresistive effect element capable of high speed operation similar to SRAM is desired. There is a need for a semiconductor memory device (eg, MRAM) using a 2T1MTJ cell that can realize a high-speed write operation that can realize a high-speed read operation without cell area overhead.

As a related technique, a semiconductor device is disclosed in Japanese Patent Laid-Open No. 2000-12790. In this semiconductor device, the memory cell array of the memory unit of the semiconductor device is divided into a plurality of regions, an even number of I / O line groups are allocated and arranged in the divided memory cell array region, and the memory unit has a predetermined bit configuration. You can do it. In the bit configuration of the memory unit, the number of bits 9 may be a basic unit. Of the even number of I / O line groups, two I / O lines assigned to adjacent memory cell array regions are combined into one I / O line, and the number of bits in the bit configuration of the memory cell portion is a predetermined bit. The number of bits in the configuration may be halved.

Japanese Patent Laid-Open No. 2003-281880 (US Pat. No. 6,822,897 (B2)) discloses a thin film magnetic memory device. The thin film magnetic memory device includes a plurality of memory cells, a plurality of data lines, and a plurality of first and second gate wirings. The plurality of memory cells are arranged in a matrix along the first and second directions, and a first group is formed for each memory cell group adjacent to each other along the first direction. A second group is formed for each memory cell group adjacent to each other along the direction. The plurality of data lines are provided for each of the first groups along the first direction. The plurality of first and second gate lines are provided along the second direction, and each is provided for each of the second groups. Each of the memory cells electrically connects the magnetoresistive element between a corresponding data line and a fixed voltage at the time of data reading, and a magnetoresistive element whose electrical resistance changes according to magnetically written storage data. And an access transistor for coupling. Each of the access transistors is turned on and off in accordance with a voltage of a predetermined one of the first and second gate wirings that is predetermined for each of the first groups.

Japanese Unexamined Patent Application Publication No. 2003-346474 (US 6,618,317 (B1)) discloses a thin film magnetic memory device. The thin film magnetic memory device includes a memory array, a plurality of bit lines, a plurality of column selection lines, an address decoder, and first and second write control circuits. In the memory array, a plurality of memory cells each storing magnetically written data are arranged in a matrix. The plurality of bit lines are provided corresponding to the plurality of memory cell columns, respectively. The plurality of column selection lines are provided corresponding to the plurality of memory cell columns, respectively. The address decoder sets voltages of the plurality of column selection lines according to a column selection result during data writing. The first and second write control circuits are arranged corresponding to one end side and the other end side of the plurality of bit lines, respectively, and data in a direction corresponding to write data is applied to the selected bit line at the time of data writing Supply write current. A first write control circuit configured to electrically connect one of the first and second voltages corresponding to the write data and a first shared node during the data writing; A plurality of drivers, each provided between one end side of the plurality of bit lines and the first shared node, each of which is turned on according to a corresponding voltage level of the plurality of column selection lines. First switch circuit. The second write control circuit is configured to electrically connect the other of the first and second voltages corresponding to the write data and a second shared node during the data write. Each of the plurality of bit lines is provided between the other end side of the plurality of bit lines and the second shared node, each corresponding to the corresponding one of the voltage levels of the plurality of column selection lines. A plurality of second switch circuits that are turned on.

Further, Japanese Patent Application Laid-Open No. 2006-108565 (US735884 (B2)) discloses a magnetoresistive effect element and a magnetic recording apparatus. The magnetoresistive element includes a first fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction changes, a first nonmagnetic layer provided between the first fixed layer and the recording layer, It comprises. In this magnetoresistance effect element, the film thickness of the recording layer is 5 nm to 20 nm. The recording layer has an extending portion extending in the first direction and a protruding portion protruding in a second direction perpendicular to the first direction from the side surface of the extending portion. When the maximum length in the first direction of the recording layer is defined as the first length and the maximum length in the second direction of the recording layer is defined as the second length, the first length / the first length The length of 2 is 1.5 to 2.2.

In addition, a magnetic random access memory is disclosed in Japanese Patent Laid-Open No. 2006-114762 (US2006083053 (A1)). This magnetic random access memory has a planar shape having a plurality of corners, and includes a magnetoresistive effect element having a radius of curvature of 20 nm or less at one or more corners.

Further, a magnetoresistive storage device is disclosed in Japanese Patent Application Laid-Open No. 2008-147437. The magnetoresistive memory device includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines, a plurality of common lines, a plurality of bit line drivers, and a plurality of common line drivers. The plurality of memory cells are arranged in a matrix, each having a variable magnetoresistive element in which the magnetization direction is set by an injection current and data is stored by its resistance value. A plurality of word lines are arranged in pairs corresponding to each memory cell row. The paired word lines are alternately connected to the memory cells in the corresponding row. The plurality of bit lines are arranged corresponding to each memory cell column, and the memory cells in the corresponding column are connected to each bit line. The plurality of common lines are arranged parallel to the bit lines between each pair of adjacent bit lines of the plurality of bit lines, and each is connected to a memory cell connected to the corresponding bit line pair. The plurality of bit line drivers are arranged corresponding to the respective bit lines, and at the time of data writing, a current flows through the corresponding bit line in accordance with the column selection signal and the write data. The plurality of common line drivers are arranged corresponding to the respective common lines, and at the time of data writing, a current flows through the corresponding common line according to the write data and the column selection signal. One of the bit line driver and the common line driver in the selected column supplies current while the other draws current during data writing.

The inventor newly discovered the following facts this time. The 2T1MTJ cell can realize a high-speed write operation similar to that of SRAM as compared with the write method used in the conventional MRAM. However, since the same read method as that of the conventional MRAM is used, the operation speed is limited by the read speed.

FIG. 4 is a circuit block diagram showing a basic configuration of the MRAM 101 using 2T1MTJ cells. The memory array 102 includes a cell column in which 2T1MTJ cells (hereinafter also simply referred to as memory cells) C are arranged in a matrix and a reference cell column in which reference cells R for two columns are arranged.

In the write operation, the row decoder 103 selects the selected word line WL from the plurality of word lines WL. The column decoder 104 selects at least one set of selected bit lines BL and / BL from the plurality of bit lines BL by the switch 106. That is, at least one selected cell C to which data is to be written is selected from the plurality of memory cells C by the selected word line WL and the selected bit lines BL and / BL. The selected cell C is electrically connected to the column decoder 104 by the switch 106. A write current Iw from a write current circuit (not shown) is supplied to the path of the column decoder 104 -selected bit line BL-selected cell C, write line 115 -selected bit line / BL-column decoder 104.

On the other hand, at the time of reading, the row decoder 103 selects the selected word line WL from the plurality of word lines WL. The column decoder 104 selects a selected bit line BL from the plurality of bit lines BL by the switch 107. That is, the selected cell C from which memory data is to be read from the plurality of memory cells C is selected by the selected word line WL and the selected bit line BL. The selected cell C is electrically connected to one input terminal of the sense amplifier 105 by the switch 107. A sense current IR flowing through the MTJ element 113 of the selected cell C is generated and supplied to one input terminal of the sense amplifier 105.

At the same time, the column decoder 104 always selects the two reference bit lines BLR0 and BLR1 by the switch 107. That is, by the selected word line WL and the two reference bit lines BLR0 and BLR1, a plurality of reference cells R0 storing data “0” and a plurality of reference cells R1 storing data “1” Therefore, the selected reference cells R0 and R1 are simultaneously selected. With the switch 107, the selected reference cells R0 and R1 are electrically connected to the other input terminal of the sense amplifier 105. The reference current Iref (0) flowing through the MTJ element of the reference cell R0 and the Iref (1) flowing through the MTJ element of the reference cell R1 are averaged to generate a reference voltage Vref used as a read criterion. , And supplied to the other input terminal of the sense amplifier 105.

That is, one of the two input terminals of the sense amplifier 105 is connected to the selected cell C, and the other is connected to the selected reference cells R0 and R1. For this reason, the load capacitances of the two input terminals of the sense amplifier 105 do not match. Therefore, the speed at which the sense signal (sense current IR0 flowing through the selected cell C) is stable differs from the speed at which the reference signal (reference current Iref flowing through the reference cell) is stabilized. Therefore, the sense amplifier 105 cannot perform a determination operation until the sense signal and the reference signal are sufficiently set, and the reading speed is limited. In addition, the influence of fluctuations in the power supply voltage and the coupling between the wirings is not uniform, which is disadvantageous from the viewpoint of noise resistance. Therefore, it is not easy to improve the reading speed of the MRAM using the 2T1MTJ cell. As a result, the operation speed, that is, the random access time is limited by the read time of 10 ns or more.

JP 2004-348934 A JP 2002-197852 A Japanese Patent Laid-Open No. 2000-12790 JP 2003-281880 A JP 2003-346474 A JP 2006-108565 A JP 2006-114762 A JP 2008-147437 A

An object of the present invention is to provide a semiconductor memory device using a magnetoresistive effect element that has a high degree of integration of memory cells and can perform high-speed operations (read operation and write operation).

The semiconductor memory device of the present invention includes a memory array including a plurality of memory cells. The plurality of memory cells include a first memory cell and a third memory cell arranged along one of the even-numbered row and the odd-numbered row, and a second memory cell arranged along the other. Each of the plurality of memory cells includes a magnetoresistive element having one end connected to the intra-cell wiring, and has a convex portion including the intra-cell wiring at the center of at least one of the sides along the row direction. The convex part of the second memory cell is arranged facing a concave part formed between the convex part of the first memory cell and the convex part of the third memory cell.

According to the present invention, in a semiconductor memory device using a magnetoresistive effect element, the degree of integration of memory cells is high, and high-speed operation similar to SRAM can be performed.

The above and other objects, advantages, and features of the present invention will be understood in more detail by the following description of embodiments with reference to the accompanying drawings.
FIG. 1 is a schematic diagram illustrating the writing principle of a typical MRAM. FIG. 2 is a graph showing the relationship between the write current and the write margin. FIG. 3 is a schematic diagram showing a configuration of a 2T1MTJ cell in Japanese Patent Application Laid-Open No. 2004-348934. FIG. 4 is a circuit block diagram showing a basic configuration of an MRAM using 2T1MTJ cells. FIG. 5 is a circuit block diagram showing a configuration of the semiconductor memory device according to the embodiment of the present invention. FIG. 6 is a circuit block diagram showing a configuration of the semiconductor memory device according to the embodiment of the present invention. FIG. 7 shows a truth table for controlling the voltage applied to the write bit line during the write operation of the semiconductor memory device according to the embodiment of the present invention. FIG. 8 shows a truth table for programming the reference cell of the semiconductor memory device according to the embodiment of the present invention. FIG. 9 is a cross-sectional view showing a part of the memory array in the semiconductor memory device according to the embodiment of the present invention. FIG. 10 is a plan view showing a part of the layout of the memory array in the semiconductor memory device according to the embodiment of the present invention. FIG. 11 is a plan view showing a part of the layout of the memory array in the semiconductor memory device according to the embodiment of the present invention. FIG. 12 is a circuit diagram showing a part of the memory array in the semiconductor memory device according to the embodiment of the present invention. FIG. 13 is a plan view showing a part of the layout of the memory array in the semiconductor memory device according to the modification of the embodiment of the present invention. FIG. 14 is a plan view showing a part of the layout of the memory array in the semiconductor memory device to be compared. FIG. 15 is a plan view showing a part of the layout of the memory array in the semiconductor memory device to be compared. FIG. 16 is a circuit diagram showing a part of a memory array in a semiconductor memory device to be compared. FIG. 17 is a cross-sectional view showing a part of a first modification of the memory array in the semiconductor device according to the embodiment of the present invention. FIG. 18 is a plan view showing a part of the layout of the first modification of the memory array in the semiconductor device according to the embodiment of the present invention. FIG. 19 is a cross-sectional view showing a part of a second modification of the memory array in the semiconductor device according to the embodiment of the present invention. FIG. 20 is a plan view showing a part of the layout of the second modification of the memory array in the semiconductor device according to the embodiment of the present invention.

Hereinafter, embodiments of a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

5 and 6 are circuit block diagrams showing the configuration of the semiconductor memory device according to the embodiment of the present invention. However, FIG. 5 also shows the path of the sense current in the read operation. FIG. 6 also shows the path of the write current in the write operation.

The semiconductor memory device 1 is a 2T1MTJ cell type MRAM. The semiconductor memory device 1 includes a memory array 2, a row decoder 3, a column decoder 4, a sense amplifier 5, a first switch unit 6, a second switch unit 8, and a selector 9.

The memory array 2 includes a plurality of word lines WLi (i = 0 to n: n is a natural number), a plurality of read bit lines RBLj, / RBLj (j = 1 to m: m is a natural number), a plurality of write bit lines WBLj, / WBLj, a plurality of memory cells Cij (i = 0 to n, j = 0 to m), two reference word lines WLR0 and WLR1, and a plurality of reference cells R0j and R1j (j = 0 to m). However, if there is no need to distinguish between them, i and j may be omitted.

The plurality of word lines WLi extend in the X direction and are connected to the row decoder 3. The plurality of read bit lines RBLj and / RBLj extend in the Y direction and are connected to the sense amplifier 5 via the first switch unit 6 and the selection unit 9. The plurality of write bit lines WBLj, / WBLj extend in the Y direction and are connected to the column decoder 4 via the second switch unit 8. Write bit line WBLj, read bit line RBLj, write bit line / WBLj, and read bit line / RBLj are arranged in this order in the X direction. For example, write bit line WBL0, read bit line RBL0, write bit line / WBL0, read bit line / RBL0, write bit line WBL1, read bit line RBL1, write bit line / WBL1, read bit line / RBL1,. is there.

The plurality of memory cells Cij are arranged in a matrix. When i is an even number, the plurality of memory cells Cij are provided corresponding to the respective intersections between the plurality of word lines WLi and the plurality of write bit lines WBLj (or read bit lines RBLj). When i is an odd number, i is provided corresponding to each of the intersections of the plurality of word lines WLi and the plurality of write bit lines / WBLj (or read bit lines / RBLj).

The plurality of memory cells Cij include memory cells in even rows (i = even) and memory cells in odd rows (i = odd). In the even-numbered memory cells Cij, for example, the memory cells C00, C01, C02,... Are arranged in the X direction on the 0th row (rows along the word line WL0 in the figure), and the 2nd row (words in the figure). C20, C21, C22,... Are arranged in the X direction in the row along the line WL2. The same applies to the fourth row, the sixth row, and so on. In this case, i is an even number. On the other hand, in the odd-numbered memory cells Cij, for example, memory cells C10, C11, C12,... Are arranged in the X direction in the first row (row along the word line WL1 in the figure), and the third row (in the figure). , C30, C31, C32,... Are arranged in the X direction. The same applies to the fifth row, the seventh row,. In this case, i is an odd number.

As a result, the memory cells Cij in the even rows are arranged along the even columns. For example, in the 0th column (column along the read bit line RBL0 in the drawing), the memory cells C00, C20, C40,... Are arranged in the Y direction, and the second column (along the read bit line RBL1 in the drawing). , C01, C21, C41,... Are arranged in the Y direction. The same applies to the fourth column, the sixth column,. On the other hand, the memory cells Cij in the odd rows are arranged along the odd columns as a result. For example, memory cells C10, C30, C50,... Are arranged in the first direction (column along the read bit line / RBL0 in the drawing) in the Y direction, and the third column (along the read bit line / RBL1 in the drawing). , C11, C31, C51,... Are arranged in the Y direction. The same applies to the fifth column, the seventh column,.

Each memory cell Cij includes a first transistor 11, a second transistor 12, and an MTJ element 13.
In the memory cells Cij in the even rows, first, one terminal of the MTJ element 13 is connected to the read bit line RBLj. The first transistor 11 has a gate connected to the word line WLi, one of the source / drain connected to the write bit line WBLj, and the other (via the write line 15; described later) to the other terminal of the MTJ element 13. . The second transistor 12 has a gate connected to the word line WLi, one of the source / drain connected to the write bit line / WBLj, and the other (via the write line 15; described later) to the other terminal of the MTJ element 13. Yes.

In the odd-numbered memory cells Cij, first, one terminal of the MTJ element 13 is connected to the read bit line / RBLj. The first transistor 11 has a gate connected to the word line WLi, one source / drain connected to the write bit line / WBLj, and the other (via the write line 15; described later) to the other terminal of the MTJ element 13. Yes. The second transistor 12 has a gate connected to the word line WLi, one of the source / drain connected to the write bit line WBL (j + 1), and the other (via the write line 15; described later) to the other terminal of the MTJ element 13. Has been.

The write bit lines WBLj, / WBLj are shared between even-numbered (column) memory cells and odd-numbered (column) memory cells. For example, the write bit line / WBL0 is shared between the memory cell C00 in the even row (column) and the memory cell C10 in the odd row (column), between C20 and C30, between C40 and C50, and so on. ing. The write bit line WBL1 is shared between the odd-numbered row (column) memory cell C10 and the even-numbered row (column) memory cell C01, between C30 and C21, between C50 and C41, and so on. The write bit line / WBL1 is shared between the memory cell C01 in the even-numbered row (column) and the memory cell C11 in the odd-numbered row (column), between C21 and C31, between C41 and C51, and so on. .

The reference word lines WLR0 and WLR1 extend in the X direction and are connected to the row decoder 3. The plurality of reference cells R0j are provided corresponding to each intersection of the reference word line WLR0 and the plurality of write bit lines WBLj (or read bit line RBLj). The plurality of reference cells R1j are provided corresponding to each intersection of the reference word line WLR1 (odd row) and the plurality of write bit lines / WBLj (or read bit lines / RBLj). That is, the plurality of reference cells R0j (R00, R01, R02,...) Are arranged along the even-numbered reference word line WLR0 and arranged in the even-numbered columns. On the other hand, a plurality of reference cells R1j (R10, R11, R12,...) Are arranged along the odd-numbered reference word lines WLR1 and arranged in the odd columns. The plurality of reference cells R0j and R1j form two rows of reference cell rows.

Similarly to the memory cell C, each reference cell R0j, R1j also includes a first transistor 11, a second transistor 12, and an MTJ element 13. In the reference cell R0j in the even-numbered row, first, the MTJ element 13 has one terminal connected to the read bit line RBLj. The first transistor 11 has a gate connected to the reference word line WLR0, one of the source / drain connected to the write bit line WBLj, and the other (via the write line 15; described later) to the other terminal of the MTJ element 13. Yes. The second transistor 12 has a gate connected to the reference word line WLR0, one of the source / drain connected to the write bit line / WBLj, and the other (via the write line 15; described later) to the other terminal of the MTJ element 13. ing.

In the odd-numbered reference cell R1j, first, one terminal of the MTJ element 13 is connected to the read bit line / RBLj. The first transistor 11 has a gate connected to the reference word line WLR1, one source / drain connected to the write bit line / WBLj, and the other (via the write line 15) to the other terminal of the MTJ element 13. . The second transistor 12 has a gate connected to the reference word line WLR1, one source / drain connected to the write bit line WBL (j + 1), and the other connected to the other terminal of the MTJ element 13 (via the write line 15). ing.

The write bit lines WBLj and / WBLj are shared between the even-numbered (column) reference cell R0j and the odd-numbered (column) reference cell R1j. For example, the write bit line / WBL0 is shared between the even-numbered row (column) reference cell R00 and the odd-numbered row (column) reference cell R10. The write bit line WBL1 is shared between the even-numbered (column) reference cells R10 and the odd-numbered (column) reference cells R01.

In the present invention, even columns (columns of a plurality of memory cells C and reference cells R arranged along the read bit line RBLj) are adjacent odd columns (memory cells C and reference cells R arranged along the read bit line / RBLj). And a pair). Then, when the memory cell C belonging to one of the even and odd columns in the set is selected during the read operation, the reference cell R belonging to the other column of the set is selected for reference. The even-numbered read bit lines RBLj are connected to one input terminal of the sense amplifier 5, and the odd-numbered read bit lines / RBLj of the same set are connected to the other input terminal of the same sense amplifier 5. That is, in the set, a memory cell C and a reference cell R from which stored data is read are prepared. For example, when the memory cell C00 in the 0th column (even column) is selected as a storage data read target, the reference cell R10 in the first column (odd column) that forms a pair with the 0th column is prepared as a reference cell. The

The row decoder 3 selects a selected word line from a plurality of word lines WLi and selects a selected reference word line from two reference word lines WLR0 and WLR1 during a read operation. Further, during the write operation, the selected word line is selected from the plurality of word lines WLi.

The column decoder 4 selects a set of selected read bit lines RBLj and / RBLj from the set of a plurality of read bit lines RBL and / RBLj by the first switch unit 6 during a read operation. In the write operation, the second switch unit 8 selects a set of selected write bit lines WBLj and / WBLj from a set of a plurality of write bit lines WBLj and / WBLj.

The sense amplifier 5 receives sense signals from the selected read bit lines RBLj and / RBLj at two input terminals and outputs a sense result during a read operation. The sense amplifier 5 includes a sense amplifier 5-1 in which j corresponds to an even number and a sense amplifier 5-2 in which j corresponds to an odd number. Note that the number of sense amplifiers 5 may be equal to the number of sets formed of even columns and odd columns. In that case, the same number of sets can be read out simultaneously.

The selector 9 includes transistors M10, M11, M12, and M13. The selector 9 switches the input terminal of the sense amplifier 5 depending on whether the row address (XA) is even or odd. For example, when an even row of memory cells is selected, the signal X0N obtained by decoding the least significant bit X0 of the row address is activated, the X0T is deactivated, the transistors M10 and M11 are on, and the transistors M12 and M13 are off It becomes the state of. At this time, SAINj is connected to the signal side input terminal SSi of the sense amplifier 5, and / SAINj is connected to the reference side input terminal SSR of the sense amplifier 5.

Here, the reference side input terminals SSR of two adjacent sense amplifiers 5 are short-circuited to each other. Thereby, the reference signal used as the reference | standard of read-out determination can be produced | generated by averaging the reference current which flows into two reference cells. For example, when data “0” is programmed in the reference cells R00 and R10 and data “1” is programmed in R01 and R11 in advance, the averaged reference current Iref is “0” sense currents Is (0) and “1”. ”Is an intermediate value of the sense current Is (1).

Note that any one of the first switch unit 6, the second switch unit 8, and the selector 9 may be included in the column decoder 4.

Next, a read operation of the semiconductor memory device according to the embodiment of the present invention will be described with reference to FIG.

In the present embodiment, the even columns of the memory cells C form the same column address (YA = same set) as the adjacent odd columns (even columns or odd columns are distinguished by row addresses (XA)). ). When even-numbered memory cells C are selected based on the addresses (XA, YA) input in the read mode (reading operation), reference to odd-numbered columns located in the same column address (belonging to the same set) Cell R is selected simultaneously. For example, when the memory cell C00 in the 0th column that is an even column is selected, the reference cell R10 in the first column that is an odd column is simultaneously selected. On the other hand, when odd-numbered memory cells are selected, even-numbered reference cells located in the same column address (belonging to the same set) are simultaneously selected. For example, when the memory cell C10 in the first column that is an odd column is selected, the reference cell R00 in the 0th column that is an even column is simultaneously selected.

First, a case will be described in which at least two sense amplifiers 5 are provided and the memory cells C00 and C01 in the even-numbered columns are read simultaneously corresponding to the two sense amplifiers 5 (the sense current path is shown in FIG. 5). Have been). When reading memory cells in even columns, the reference cells in odd columns in the same set as the even columns to which the memory cells to be read belong are selected. Note that the number of memory cells that can be read simultaneously is the same as or less than the number of sense amplifiers 5.

First, the memory cell C00 in the 0th column and the corresponding reference cell R10 in the first column are selected simultaneously.
The row decoder 3 selects and activates the word line WL0 as a selected word line based on the row address XA, and turns on the first and

second transistors

11 and 12 of the memory cell C00. Similarly, the row decoder 3 selects and activates the reference word line WLR1 as the selected reference word line based on the row address XA, and turns on the first and

second transistors

11 and 12 of the reference cell R10. Next, the column decoder 4 activates the signal RY0 based on the column address YA to turn on the transistors M0 and M1 of the first switch unit 6. As a result, the read bit line RBL0 and the read bit line / RBL0 are selected as the selected read bit lines. As a result, the memory cell C00 is selected by the word line WL0 and the read bit line RBL0. Similarly, the reference cell R10 is selected by the reference word line WLR1 and the read bit line / RBL0. The read bit line RBL0 is connected to the input wiring SAIN0 to the sense amplifier 5 through the transistor M0. Read bit line / RBL0 is connected to input wiring / SAIN0 to sense amplifier 5 through transistor M1.

Similarly, the memory cell C01 in the second column and the corresponding reference cell R11 in the third column are simultaneously selected.
Based on the row address XA, the row decoder 3 selects and activates the word line WL0 as the selected word line, and selects and activates the reference word line WLR1 as the selected reference word line. Accordingly, the first and

second transistors

11 and 12 of the memory cell C01 and the first and

second transistors

11 and 12 of the reference cell R11 are turned on. Next, the column decoder 4 activates the signal RY1 based on the column address YA to turn on the transistors M2 and M3 of the first switch unit 6. As a result, the read bit line RBL1 and the read bit line / RBL1 are selected as the selected read bit lines. As a result, the memory cell C01 is selected by the word line WL0 and the read bit line RBL1. Similarly, the reference cell R11 is selected by the reference word line WLR1 and the read bit line / RBL1. The read bit line RBL1 is connected to the input wiring SAIN1 to the sense amplifier 5 through the transistor M2. Read bit line / RBL1 is connected to input wiring / SAIN1 to sense amplifier 5 through transistor M3.

Here, when the memory cell C00 in the 0th row (even row) is selected, the selector 9-1 activates the signal X0N obtained by decoding the least significant bit X0 of the row address and deactivates X0T. As a result, the transistors M10 and M11 are turned on, and the transistors M12 and M13 are turned off. Thereby, the input wiring SAIN0 is connected to the signal side input terminal SSi of the sense amplifier 5, and the input wiring / SAIN0 is connected to the reference side input terminal SSR of the sense amplifier 5.

On the other hand, when the memory cell C01 in the 0th row (even row) is selected, the selector 9-2 activates the signal X0N obtained by decoding the least significant bit X0 of the row address and deactivates X0T. As a result, the transistors M10 and M11 are turned on, and the transistors M12 and M13 are turned off. As a result, the input wiring SAIN1 is connected to the signal side input terminal SSi of the sense amplifier 5, and the input wiring / SAIN1 is connected to the reference side input terminal SSR of the sense amplifier 5.

The reference current Iref averaged by pre-programming data “0” in the reference cell R10 and data “1” in the reference cell R11 is the sense current Is (0) of “0” and the sense current of “1”. It is an intermediate value of Is (1). The sense amplifiers 5-1 and 5-2 supply the clamp voltage Vc to the signal side input terminal SSi and the reference side input terminal SSR. That is, Vc is also applied to the input wirings SAIN0 and / SAIN0 and the selected read bit lines RBL0 and / RBL0. Similarly, Vc is also applied to the input wirings SAIN1 and / SAIN1 and the selected read bit lines RBL1 and / RBL1. In the read mode (read operation), all the write bit lines WBL and / WBL are grounded. Accordingly, the sense current Is0 flows through the input memory line SAIN0 and the read bit line RBL0 in the selected memory cell C00. Similarly, a sense current Is1 flows in the selected memory cell C01 via the input wiring SAIN1 and the read bit line RBL1. On the other hand, the reference current / Is0 flows through the input cell / SAIN0 and the read bit line / RBL0 in the selected reference cell R10. Similarly, a reference current / Is1 flows through the reference cell R11 via the input wiring / SAIN1 and the relax bit line / RBL1. The sense amplifier 5-1 compares the magnitude of the sense current Is0 and the averaged reference current Iref (= (/ Is0 + / Is1) / 2) and outputs a read result. Similarly, the sense amplifier 5-2 compares the magnitude of the sense current Is1 and the averaged reference current Iref (= (/ Is0 + / Is1) / 2), and outputs a read result.

Next, a case will be described in which at least two sense amplifiers 5 are provided and the odd-numbered memory cells C10 and C11 are read simultaneously corresponding to the two sense amplifiers 5 (the sense current path is shown in FIG. 5). Not shown).

The memory cell C10 in the first column and the corresponding reference cell R00 in the 0th column are simultaneously selected.
First, the row decoder 3 selects and activates the word line WL1 as a selected word line based on the row address XA, and turns on the first and

second transistors

11 and 12 of the memory cell C10. Similarly, the row decoder 3 selects and activates the reference word line WLR0 as the selected reference word line based on the row address XA, and turns on the first and

second transistors

11 and 12 of the reference cell R00. Next, the column decoder 4 activates the signal RY0 based on the column address YA to turn on the transistors M0 and M1 of the first switch unit 6. As a result, the read bit line RBL0 and the read bit line / RBL0 are selected as the selected read bit lines. As a result, the memory cell C10 is selected by the word line WL1 and the read bit / line RBL0. Similarly, the reference cell R00 is selected by the reference word line WLR0 and the read bit line RBL0. The read bit line RBL0 is connected to the input wiring SAIN0 to the sense amplifier 5 through the transistor M0. Read bit line / RBL0 is connected to input wiring / SAIN0 to sense amplifier 5 through transistor M1.

Similarly, the memory cell C11 in the second column and the corresponding reference cell R01 in the third column are selected simultaneously.
Based on the row address XA, the row decoder 3 selects and activates the word line WL1 as the selected word line, and selects and activates the reference word line WLR0 as the selected reference word line. Accordingly, the first and

second transistors

11 and 12 of the memory cell C11 and the first and

second transistors

11 and 12 of the reference cell R01 are turned on. Next, the column decoder 4 activates the signal RY1 based on the column address YA to turn on the transistors M2 and M3 of the first switch unit 6. As a result, the read bit line RBL1 and the read bit line / RBL1 are selected as the selected read bit lines. As a result, the memory cell C11 is selected by the word line WL1 and the read bit / line RBL1. Similarly, the reference cell R01 is selected by the reference word line WLR0 and the read bit line RBL1. The read bit line RBL1 is connected to the input wiring SAIN1 to the sense amplifier 5 through the transistor M2. Read bit line / RBL1 is connected to input wiring / SAIN1 to sense amplifier 5 through transistor M3.

Here, when the memory cell C10 in the first row (odd row) is selected, the selector 9-1 deactivates the signal X0N obtained by decoding the least significant bit X0 of the row address, and activates X0T. As a result, the transistors M10 and M11 are turned off, and the transistors M12 and M13 are turned on. As a result, the input wiring / SAIN0 is connected to the signal side input terminal SSi of the sense amplifier 5, and the input wiring SAIN0 is connected to the reference side input terminal SSR of the sense amplifier 5.

On the other hand, when the memory cell C11 in the first row (odd row) is selected, the selector 9-2 deactivates the signal X0N obtained by decoding the least significant bit X0 of the row address and activates X0T. As a result, the transistors M10 and M11 are turned off, and the transistors M12 and M13 are turned on. As a result, the input wiring / SAIN1 is connected to the signal side input terminal SSi of the sense amplifier 5, and the input wiring SAIN1 is connected to the reference side input terminal SSR of the sense amplifier 5.

The sense amplifiers 5-1 and 5-2 supply the clamp voltage Vc to the signal side input terminal SSi and the reference side input terminal SSR. That is, Vc is also applied to the input wirings SAIN0 and / SAIN0 and the selected read bit lines RBL0 and / RBL0. Similarly, Vc is also applied to the input wirings SAIN1 and / SAIN1 and the selected read bit lines RBL1 and / RBL1. In the read mode (read operation), all the write bit lines WBL and / WBL are grounded. Therefore, the sense current Is0 flows through the input line / SAIN0 and the read bit line / RBL0 in the selected memory cell C10. Similarly, the sense current Is1 flows through the input line / SAIN1 and the read bit line / RBL1 in the selected memory cell C11. On the other hand, a reference current / Is0 flows through the input cell SAIN0 and the read bit line RBL0 in the selected reference cell R00. Similarly, a reference current / Is1 flows through the reference cell R01 via the input wiring SAIN1 and the relax bit line RBL1. The sense amplifier 5-1 compares the magnitude of the sense current Is0 and the averaged reference current Iref (= (/ Is0 + / Is1) / 2) and outputs a read result. Similarly, the sense amplifier 5-2 compares the magnitude of the sense current Is1 and the averaged reference current Iref (= (/ Is0 + / Is1) / 2), and outputs a read result.

As described above, the read operation in the embodiment of the semiconductor memory device of the present invention is executed.

As described above, two adjacent sense amplifiers 5 short-circuit the reference side input terminal SSR, while the reference side input terminal SSR of the sense amplifier 5 receives the reference current from the reference cell R that stores data “0”. And the reference side input terminal SSR of the other sense amplifier 5 needs to be supplied with a reference current from the reference cell R storing data “1”. Therefore, even when data is read from one memory cell, in addition to the reference cell for that memory cell (example: “0” is stored), there are also reference cells that store different data (example: “1”). Control to select at the same time. For example, even when data is read from one memory cell, two data are temporarily read as described above.

Next, a write operation in the embodiment of the semiconductor memory device of the present invention will be described with reference to FIG. In this figure, “0” is written when the write current Iw flows in the −X direction (right to left with respect to the paper surface) in the memory cell C, and “1” when the write current Iw flows in the + X direction (left to right with respect to the paper surface). Define as write.

Writing to the memory cell C (2T1MTJ cell) is performed by applying complementary voltages to the write bit line WBLj and the write bit line / WBLj according to the write data. FIG. 7 shows a truth table for controlling the voltage applied to the write bit line in the write mode (write operation) in the semiconductor memory device according to the embodiment of the present invention. “YA” is a column address, “XA” is a row address (“even” = even, “odd” = odd), “Din” is input data (“1”, “0”), “WBLj”, and “/ WBLj” "Indicates the state of the ride bit line (" H "= High level," L "= Low level).

For example, when writing to the memory cell C00 in the 0th row which is the even row (XA = “even”) of the 0th set (YA = 0), the row decoder 3 activates the word line WL0. When the input data is “1”, the column decoder 4 sets the write bit line WBL0 to the “H” level and the write bit line / WBL0 to the “L” level. As a result, the write current Iw (1) is supplied in the + X direction. When the input data is “0”, write bit line WBL0 is set to “L” level and write bit line / WBL0 is set to “H” level. As a result, the write current Iw (0) is supplied in the −X direction (not shown).

On the other hand, when writing to the memory cell C10 in the first row which is the odd row (XA = “odd”) of the 0th group (YA = 0), the row decoder 3 activates the word line WL1. When the input data is “1”, the column decoder 4 sets the write bit line / WBL0 to “H” level and the write bit line WBL1 to “L” level. As a result, the write current Iw (1) is supplied in the + X direction. When the input data is “0”, the write bit line / WBL0 is set to “L” level and the write bit line WBL1 is set to “H” level. As a result, the write current Iw (0) is supplied in the −X direction (not shown).

For example, when writing to the memory cell C01 in the second row which is the even row (XA = “even”) of the first set (YA = 1), the row decoder 3 activates the word line WL0. When the input data is “1”, the column decoder 4 sets the write bit line WBL1 to the “H” level and the write bit line / WBL1 to the “L” level. Thereby, the write current Iw (1) is supplied in the + X direction (not shown). When the input data is “0”, the write bit line WBL1 is set to “L” level and the write bit line / WBL1 is set to “H” level. As a result, the write current Iw (0) is supplied in the −X direction.

On the other hand, when writing to the memory cell C11 in the third row, which is the odd row (XA = “odd”) in the first set (YA = 1), the row decoder 3 activates the word line WL1. When the input data is “1”, the column decoder 4 sets the write bit line / WBL1 to the “H” level and the write bit line WBL2 to the “L” level. Thereby, the write current Iw (1) is supplied in the + X direction (not shown). When the input data is “0”, the write bit line / WBL1 is set to “L” level and the write bit line WBL2 is set to “H” level. As a result, the write current Iw (0) is supplied in the −X direction.

The write circuit for controlling the voltage to the write bit line WBLj based on the truth table shown in FIG. 7 uses the switch Sk (k = 0 to q: q natural number) of the second switch unit 8 as shown in FIG. Can be realized. For example, when an even-numbered memory cell is selected, X0N is activated, X0T is deactivated, and switches S0, S2,... Are turned on. At this time, for example, when writing to the memory cell C00, the column decoder 4 transmits the control signal DY0 to the terminal W0 and the control signal / DY0 to the terminal / W0. Thereby, complementary voltages corresponding to the input data can be applied to the write bit lines WBL0 and / WBL0 (based on the truth table of FIG. 7).

On the other hand, when an odd row of memory cells is selected, X0N is deactivated, X0T is activated, and switches S1, S3,... Are turned on. At this time, for example, when writing to the memory cell C10, the column decoder 4 transmits the control signal DY0 to the terminal / W0 and the control signal / DY0 to the terminal W1. Thereby, complementary voltages according to the input data can be applied to the write bit lines / WBL0 and WBL1 (based on the truth table of FIG. 7).

That is, in the present invention, a write current can be supplied by applying complementary voltages to the two write bit lines. For example, the write bit line WBL is driven by a logic gate buffer (or an inverter or the like) that receives the terminals W0, / W0,... Of FIG. This buffer has the role of a write driver. As described above, the overhead (additional portion) of the circuit related to writing is only the switch Sk and the terminal W of the second switch unit 8, and this switch is usually realized by a CMOS switch or the like, and its area overhead is small.

Next, a method for programming the reference cell will be described. FIG. 8 shows a truth table for programming the reference cell in the semiconductor memory device according to the embodiment of the present invention. “Operation mode” indicates the type of operation mode (read (read), write (write), reference cell program (reference cell write)), and “low address LSB (Least Significant Bit)” is even / odd of the least significant bit X0. The “word line” is the state of the word line WLi (“H” = High level, “L” = Low level), and the “reference word line” is the state of the reference word lines WLR0 and WLR1 (“H” = High level, “ L ”= Low level).

In the above-described normal read mode (read operation), when an address (X0 = 0) for selecting (“H” level) memory cells in even rows (word lines WL0, 2,...) Is input, odd rows The reference word line WLR1 is activated ("H" level). On the other hand, when an address (X0 = 1) at which memory cells in odd rows (word lines WL1, 3,...) Are selected (“H” level) is input, reference word line WLR0 in even rows is activated (“ H ”level).

In the normal write mode (write operation) described above, both the reference word lines WLR0 and WLR1 are deactivated ("L" level). Further, in the program mode to the reference cell, for example, when desired data is written (programmed) to the reference cell in the even-numbered row, the reference word line WLR0 is activated (“H” level). When programming into reference cells in odd rows, reference word line WLR1 is activated ("H" level).

FIG. 9 is a cross-sectional view showing a part of the memory array in the semiconductor memory device according to the embodiment of the present invention. 10 and 11 are plan views showing a part of the layout of the memory array in the semiconductor memory device according to the embodiment of the present invention. FIG. 12 is a circuit diagram showing a part of the memory array in the semiconductor memory device according to the embodiment of the present invention. However, FIG. 9 is an AA ′ cross-sectional view in FIGS. 10 and 11. FIG. 10 shows layers below the metal layer M1 in FIG. FIG. 11 shows a layer above the metal layer M1 in FIG. FIG. 12 is a circuit diagram corresponding to FIGS. 10 and 11 extracted from FIG.

As shown in FIGS. 9 to 11, for example, the first transistor 11 of the memory cell C00 is a dual gate type transistor. The first transistor 11 includes a diffusion layer 61-1, a diffusion layer 61-2, and a gate 62. Diffusion layer 61-1 is connected to write bit line WBL0 via contact D1. The diffusion layer 61-2 is connected to one end of the write line 15 through contacts D2, M1, and V1. The gate 62 is connected to the word line WL0 and is provided immediately below the word line WL0. Similarly, the second transistor 12 includes a diffusion layer 61-1, a diffusion layer 61-2, and a gate. Diffusion layer 61-1 is connected to write bit line / WBL0 via contact D1. The diffusion layer 61-2 is connected to the other end of the write line 15 via contacts D2, M1, and V1. The gate 62 is connected to the word line WL0 and is provided immediately below the word line WL0. An MTJ element 13 is disposed on the write line 15. The MTJ element 13 is connected to the upper read bit line RBL0 via the MTJ via.

However, although not shown, the MTJ element 13 may be disposed below the write line 15. In that case, the MTJ element 13 is connected to the lower read bit line RBL0 via the MTJ via. In that case, the contacts D2, M1, and V1 are provided with a sufficient height so that the read bit line RBL0 and the write bit line WBL0 do not contact each other.

Similarly, the first transistor 11 of the memory cell C01 is a dual gate transistor. The first transistor 11 includes a diffusion layer 61-1 connected to the write bit line WBL1 through a contact D1, a diffusion layer 61-2 connected to one end of the write line 15 through contacts D2, M1, and V1. The gate 62 is connected to the word line WL0. The second transistor 12 is a dual gate transistor. The second transistor 12 includes a diffusion layer 61-1 connected to the write bit line / WBL1 via a contact D1, and a diffusion layer 61-2 connected to the other end of the write line via contacts D2, M1, and V1. The gate 62 is connected to the word line WL0. An MTJ element 13 is disposed on the write line 15. The MTJ element 13 is connected to the upper read bit line RBL1 via an MTJ via.

Similarly, the first transistor 11 of the memory cell C10 is a dual gate transistor. The first transistor 11 includes a diffusion layer connected to the write bit line / WBL0 through the contact D1, a diffusion layer connected to the write wiring through the contacts D2, M1, and V1, and a gate connected to the word line. Is done. The second transistor is a dual gate type transistor, and is connected to the diffusion layer connected to the write bit line WBL1 through the contact D1, connected to the write wiring through the contacts D2, M1, and V1, and connected to the word line. Composed of gates. An MTJ element is disposed on the write wiring and is connected to the read bit line / RBL0 above the MTJ element. The same applies hereinafter.

Here, in the circuit diagrams of FIGS. 5, 6, and 12, each memory cell C shows an example in which normal transistors are used as the first transistor 11 and the second transistor 12. However, as shown in FIG. 10, each memory cell can use a dual gate type transistor as the first transistor 11 and the second transistor 12. That is, two first transistors 11 and second transistors 12 may be provided. In this case, two word lines WL are provided.

Further, on the side where the memory cell C00 and the memory cell C10 are adjacent to each other, the contact D1 and the diffusion layer 61-1 connected thereto are the same and are shared. That is, the diffusion layer 61-1 and the contact D1 are shared between the memory cells (example C00) along the word line WL0 and the memory cells (example C10) along the word line WL1. In the case of a dual gate transistor, the diffusion layer 61-1 and the contact D1 are shared on one side of the memory cell C along the word line WL. On the other hand, in the case of a single gate type transistor, the diffusion layer and the contact are shared on one side of the memory cell along the word line. In either case, the area of the diffusion layer and the contact can be reduced, which is preferable.

Here, the semiconductor memory device shown in FIGS. 9 to 12 is compared with other semiconductor memory devices.
14 and 15 are plan views showing a part of the layout of the memory array in the semiconductor memory device to be compared. FIG. 16 is a circuit diagram showing a part of a memory array in a semiconductor memory device to be compared. 14 corresponds to FIG. 10, FIG. 15 corresponds to FIG. 11, and FIG. 16 corresponds to FIG. Also, the reference numerals of the components in FIGS. 14 to 16 are the same as those of the corresponding components in FIGS.

14 and 15, for example, the first transistor 11 of the memory cell C00 is a dual gate transistor. The first transistor 11 includes a diffusion layer 61-1 connected to the write bit line WBL0 via a contact D1, a diffusion layer 61-2 connected to the write line 15 via contacts D2, M1, and V1, and a word line WL0. And a gate 62 provided immediately below the word line WL0. The second transistor 12 is a dual gate transistor. The second transistor 12 includes a diffusion layer 61-1 connected to the write bit line / WBL0 via a contact D1, a diffusion layer 61-2 connected to the write line 15 via contacts D2, M1, and V1, a word line The gate 62 is connected to WL0 and provided immediately below the word line WL0. An MTJ element 13 is disposed on the write line 15. The MTJ element 13 is connected to the read bit line RBL0 above the MTJ element 13 through an MTJ via.

Similarly, the first transistor 11 of the memory cell C01 is a dual gate transistor. The first transistor 11 includes a diffusion layer 61-1 connected to the write bit line WBL1 through a contact D1, a diffusion layer 61-2 connected to the write line 15 through contacts D2, M1, and V1, and a word line WL0. And a gate 62 provided immediately below the word line WL0. The second transistor 12 is a dual gate transistor. The second transistor 12 includes a diffusion layer 61-1 connected to the write bit line / WBL1 through a contact D1, a diffusion layer 61-2 connected to the write line 15 through contacts D2, M1, and V1, a word line The gate 62 is connected to WL0 and provided immediately below the word line WL0. An MTJ element 13 is disposed on the write line 15. The MTJ element 13 is connected to the read bit line RBL1 above the MTJ element 13 through an MTJ via.

Similarly, the first transistor 11 of the memory cell C10 is a dual gate transistor. The first transistor 11 includes a diffusion layer 61-1 connected to the write bit line WBL0 via a contact D1, a diffusion layer 61-2 connected to the write line 15 via contacts D2, M1, and V1, and a word line WL1. And a gate 62 provided immediately below the word line WL1. The second transistor 12 is a dual gate transistor. The second transistor 12 includes a diffusion layer 61-1 connected to the write bit line / WBL0 via a contact D1, a diffusion layer 61-2 connected to the write line 15 via contacts D2, M1, and V1, a word line The gate 62 is connected to WL1 and provided immediately below the word line WL1. An MTJ element 13 is disposed on the write line 15. The MTJ element 13 is connected to the read bit line RBL0 above the MTJ element 13 through an MTJ via. The same applies hereinafter.

Here, in the circuit diagram of FIG. 16, each memory cell C shows an example in which normal transistors are used as the first transistor 11 and the second transistor 12. However, as shown in FIG. 14, each memory cell can use a dual gate transistor as the first transistor 11 and the second transistor 12. That is, two first transistors 11 and second transistors 12 may be provided. In this case, two word lines WL are provided.

Hereinafter, the semiconductor memory device shown in FIGS. 9 to 12 and the semiconductor device shown in FIGS. 14 to 16 will be specifically compared.
Comparing the layout of FIG. 10 and the layout of FIG. 14, the layout of the transistor layers (diffusion layers 61-1, 61-2, gate 62, word line WL, contacts D1, D2) is the same in both. However, the writing line 15 is drawn out differently in both cases. That is, in FIG. 10, the even-numbered write bit line WBL (of the memory cell C) and the odd-numbered write bit line WBL can be shared. Thereby, the memory cells C can be densely arranged. That is, the memory array of FIG. 10 can be formed without increasing the area of the memory cell as compared with the memory cell array of FIG. On the other hand, in the memory array described in Japanese Patent Laid-Open No. 2002-197852, an increase in the area of the memory cell is inevitable due to a dead area caused by staggering the memory cells.

11 is compared with the memory cell of FIG. 15, the minimum distance between the MTJ elements 13 is different between them. That is, the distance D0 between the MTJ elements 13 in adjacent rows in FIG. 11 (embodiment) is larger than the distance D1 between the MTJ elements 13 in FIG. Thereby, in the MTJ element 13 in FIG. 11 (embodiment), the magnetic interaction between the MTJ elements 13 can be reduced. Reducing the magnetic interaction between the MTJ elements 13 is effective for improving data retention characteristics and reducing write defects and read defects.

Further, when the memory cell of FIG. 11 and the memory cell of FIG. 15 are further compared, the layout of the write line 15 differs between them. That is, in the memory cell of FIG. 11, the write line 15 is narrower in the Y direction at both ends connected to the via V1 than in the case of FIG. 15 (width CY2 in FIG. 11 <width CY0 in FIG. 15). . On the other hand, the write line 15 is the central part connected to the MTJ element 13 and the width in the Y direction is the same as in FIG. 15 (width CY1 in FIG. 11 = width CY0 in FIG. 15). That is, the central part of at least one side (both sides in the figure) along the row direction (X direction) protrudes in the column direction (Y direction) as compared to both ends. That is, the center part forms the convex part 15a, and both ends form the branch part 15c. For example, the convex portion 15a of the memory cell C10 is disposed so as to face the concave portion 15b formed by the branch portion 15c between the convex portion 15a of the memory cell C00 and the convex portion 15a of the memory cell C01. Therefore, the minimum space between adjacent cells in the Y direction on the write line 15 can be made larger in FIG. 11 (the embodiment) than in FIG. 15 (distance S0 in FIG. 11> distance in FIG. S1). 11 makes it easier to process the write line 15 and contributes to the improvement of the yield. Further, in FIG. 11, the MTJ element 13 can be enlarged without changing the size of the memory cell by the amount of the generated space. When the MTJ element 13 is enlarged, the data retention characteristic is improved. In addition, the fact that the MTJ element 13 can be enlarged improves the consistency between the manufacturing process of the MTJ element 13 and the manufacturing process of the transistor. This is because the MTJ element 13 that can be processed is larger than the mature transistor.

Note that the write line 15 in FIG. 11 (embodiment) has a central portion (convex portion 15a) having a rectangular shape, and both end portions (branches 15c) are elongated extending in the row direction (X direction) from the central portion. It has a rectangular shape. However, the write line 15 is not limited to this shape, and the central portion (convex portion 15a) may have an elliptical shape like the MTJ element 13 or a rounded substantially rectangular shape. It may be.

Note that the write line 15 in FIG. 11 (embodiment) is plane-symmetric with respect to a zx plane (substantially perpendicular to the substrate) passing through the central axis in the row direction (X direction) of the memory cell C. However, the central axis is an axis passing through the center of the MTJ element 13 of the memory cell C adjacent in the row direction (X direction). However, the writing line 15 does not necessarily have plane symmetry with respect to the zx plane passing through the central axis. Even if it is not plane-symmetric, the same effect can be obtained by arranging as follows. For example, the arrangement of the write lines 15 of even-numbered memory cells C and the write lines 15 of odd-numbered memory cells C is determined as follows. That is, the position of one of the write lines 15 of both memory cells C is reversed with respect to the axis in the row direction (X direction), and then both write lines 15 are written. What is necessary is just to arrange | position by 15 bit shift | offset | difference to the row direction (X direction) so that 15 convex parts may mutually engage. However, this axis is an axis in the row direction (X direction) that substantially passes through the C boundary of both memory cells or is equidistant from the MTJ element 13 of both memory cells C. As a result, the projections of the writing line 15 having larger projections can be engaged with each other while the projections of the projection of the writing line 15 having smaller projections can be engaged with each other. As a result, the protruding state of the convex portion and the retracting state of the concave portion can be appropriately combined.
Note that FIGS. 11 and 13 (described later) satisfy this requirement.

Note that, in the write line 15 of FIG. 11 (embodiment), the magnitude of the write current required for writing data to the MTJ element 13 is not so different from that of the write line of FIG. This is because the write current is most affected by the current distribution passing directly under the MTJ element 13, but the shape of the write wiring immediately under the MTJ element 13 does not change between FIG. 11 and FIG. 15.

FIG. 13 is a plan view showing a part of the layout of the memory array in the semiconductor memory device according to the modification of the embodiment of the present invention. However, FIG. 13 corresponds to FIG. 11, and the reference numerals of the respective components in FIG. 13 are the same as those of the corresponding respective components in FIG.

13 is compared with the layout of FIG. 11, the cell size in the Y direction is smaller. In the example of this figure, CY (FIG. 11) is (CY-dY) (FIG. 13). That is, with respect to the layout of FIG. 11 in which the width in the Y direction at both ends of the write line 15 is narrowed and the memory cells C are arranged in a staggered manner, the space generated by the layout is further filled in the Y direction. Cell C can be placed. Therefore, the modification of this embodiment can increase the degree of integration of memory cells.

At this time, for example, the layout of FIG. 13 shows that the tip (in the −Y direction) of the projection 15a of the write line 15 of the memory cell C10 is the tip (in the + Y direction) of the projection of the write line 15 of the memory cell C00. And closer to the memory cell C00 and the memory cell C01 than the line Q connecting the leading end of the convex portion of the write line 15 of the memory cell C01 (in the + Y direction). Accordingly, the convex portion 15a of the write line 15 of the memory cell C10 faces the concave portion 15b formed between the convex portion 15a of the write line 15 of the memory cell C00 and the convex portion 15a of the write line 15 of the memory cell C01. As compared with the case of FIG. 11, it arrange | positions so that it may fit deeply into the recessed part 15b.

In addition, such a structure in which the convex part and the concave part face each other is made only on the side facing each other for each group (one even line and one odd line group), and the other group and back to back. It is not necessary to provide a convex part / concave part on the side to be. Even in such a case, the effect of increasing the degree of integration can be obtained as compared with the case where no protrusion / recess is provided.

As described above, according to the present embodiment, the reading speed can be remarkably improved as compared with the MRAM memory array described in each document. That is, in the 2T1MTJ cell shown in FIG. 4 and the 1T1MTJ cell (1-Transistor-1-MTJ element type cell) described in Japanese Patent Laid-Open No. 2002-197852, the bit line is shared for reading and writing. Therefore, a write circuit (or a current switch for driving a write current) is added to the bit line. As a result, the load capacity of the bit line is increased, which causes a decrease in read speed. In the writing method using the MTJ inversion threshold curve described in Japanese Patent Laid-Open No. 2002-197852, it is difficult to reduce the writing time to 10 ns or less due to the complexity of the writing circuit. Therefore, even if the read time can be shortened to 10 ns or less, the random access time will be 10 ns or more.

However, in this embodiment, the bit lines are separated for reading and writing (read bit line RBL and write bit line WBL). Therefore, the load capacity of the read bit line RBL can be reduced. In addition, as shown in FIGS. 9 and 11, in this embodiment, the number of MTJ elements 13 connected to one read bit line RBL is halved compared to the conventional case. Has been reduced. The capacity of the tunnel insulating film of the MTJ element 13 is very large compared to the wiring capacity. Therefore, the load capacity of the read bit line RBL can be remarkably reduced by reducing the MTJ element 13. Further, the load capacity of read bit line RBL is equal to the load capacity of read bit line / RBL. Therefore, the settling time of the sense signal and the settling time of the reference signal can be made equal. Therefore, even if the sense signal and the reference signal are not set, if the difference signal is sufficiently large, it is possible to sense with high reliability.

For the above reasons, it is possible to reduce the read time, which took 10 ns or more in the conventional MRAM, to about 5 ns in this embodiment. Originally, the 2T1MTJ cell is a cell system that can shorten the writing time to about 1 ns. Therefore, according to the present invention, the random access time of the MRAM can be increased to about 5 ns. This is approximately equal to the random access time required for SRAM macros mounted on many system LSIs.

Next, a first modification of the semiconductor memory device according to the embodiment of the present invention will be described.
FIG. 17 is a cross-sectional view showing a part of a first modification of the memory array in the semiconductor memory device according to the embodiment of the present invention. FIG. 18 is a plan view showing a part of the layout of the first modification of the memory array in the semiconductor memory device according to the embodiment of the present invention. However, FIG. 17 is a BB ′ cross-sectional view in FIG. FIG. 18 shows a layer above the metal layer M2 in FIG. The metal layer M1 and the subsequent layers are the same as those in FIG.

As shown in FIG. 17 and FIG. 18, the present method can be applied to a domain wall motion type memory element. For example, the domain wall motion type memory element includes a magnetic layer 50 having perpendicular magnetization and an MTJ element 55 having in-plane magnetization. The magnetic layer 50 includes a first fixed region 51, a second fixed region 52, and a free region 53. The MTJ element 55 changes to a low resistance state or a high resistance state in response to a perpendicular magnetization leakage magnetic field in the free region 53. The MTJ element 55 includes a free layer whose magnetization direction changes due to a leakage magnetic field from the free region 53, a barrier layer that is an insulating layer, and a pinned layer whose magnetization direction is fixed. In this element, a write current is passed through the perpendicular magnetic film (magnetic layer 50), and the magnetization direction of the free region 53 can be freely changed by the effect of spin torque. In addition, since this element can write data with a small write current, low power consumption and a reduction in cell transistor can be expected.

For example, the first transistor 11 of the memory cell C00 is a dual gate transistor. The first transistor 11 includes a diffusion layer 61-1, a diffusion layer 61-2, and a gate 62. Diffusion layer 61-1 is connected to write bit line WBL0 via contact D1. The diffusion layer 61-2 is connected to the first fixed region 51 of the magnetic layer 50 through contacts D2, M1, V1, M2, V2, M3, and V3. The gate 62 is connected to the word line WL0 and is provided immediately below the word line WL0. Similarly, the second transistor 12 includes a diffusion layer 61-1, a diffusion layer 61-2, and a gate. Diffusion layer 61-1 is connected to write bit line / WBL0 via contact D1. The diffusion layer 61-2 is connected to the second fixed region 52 of the magnetic layer 50 through contacts D2, M1, V1, M2, V2, M3, and V3. The gate 62 is connected to the word line WL0 and is provided immediately below the word line WL0. An MTJ element 55 is disposed under the magnetic layer 50. The MTJ element 55 is connected to the lower read bit line RBL0 via M3, V2, and M2.

However, although not shown, the read bit line RBL0 may be arranged on the upper side of the magnetic layer 50. In that case, the wiring layer M3 is connected to the read bit line RBL0 via a via. Further, although not shown, the MTJ element 53 may be disposed on the upper side of the magnetic layer 50. In this case, the MTJ53 element is connected to the upper read bit line RBL0.

Similarly, the first transistor 11 of the memory cell C01 is a dual gate transistor. The first transistor 11 includes a diffusion layer 61-1 connected to the write bit line WBL1 through a contact D1, and a first fixed region of the magnetic layer 50 through contacts D2, M1, V1, M2, V2, M3, and V3. A diffusion layer 61-2 connected to 51 and a gate 62 connected to the word line WL0. The second transistor 12 is a dual gate transistor. The second transistor 12 includes a diffusion layer 61-1 connected to the write bit line / WBL1 through a contact D1, and a second fixed layer of the magnetic layer 50 through contacts D2, M1, V1, M2, V2, M3, and V3. A diffusion layer 61-2 connected to the region 52 and a gate 62 connected to the word line WL0 are included. An MTJ element 55 is disposed under the magnetic layer 50. The MTJ element 55 is connected to the lower read bit line RBL1 via M3, V2, and M2.

Similarly, the first transistor 11 of the memory cell C10 is a dual gate transistor. The first transistor 11 has a diffusion layer connected to the write bit line / WBL0 through the contact D1, and the first fixed region 51 of the magnetic layer 50 through the contacts D2, M1, V1, M2, V2, M3, and V3. It consists of a connected diffusion layer and a gate connected to a word line. The second transistor 12 is a dual gate transistor. The second transistor 12 is connected to the second fixed region 52 of the magnetic layer 50 through a contact connected to the write bit line WBL1 through the contact D1, and through the contacts D2, M1, V1, M2, V2, M3, and V3. And a gate connected to a word line. An MTJ element is disposed under the magnetic layer 50 and is connected to the read bit line / RBL0 below the MTJ element. The same applies hereinafter.

Next, data writing will be described. For example, in the even-numbered C00 memory cell, if the magnetization of the first fixed region 51 is fixed in the + Z direction and the magnetization of the second fixed region 52 is fixed in the −Z direction, the second fixed region 52 to the first fixed region When a current is passed toward the region 51, electrons flow from the first fixed region 51 to the second fixed region 52. Then, due to the effect of the spin torque, the magnetization direction of the free region 53 is directed to the + Z direction, which is the same as the magnetization direction of the first fixed region 51. At this time, the magnetization of the free layer of the MTJ element 55 is in the −Y direction. When the in-plane magnetization direction of the pinned layer of the MTJ element 55 is fixed in the −Y direction, the MTJ element 55 is in a low resistance state, and data “0” is written. Conversely, when a current is passed from the first fixed region 51 toward the second fixed region 52, the magnetization direction of the free region 53 is in the same −Z direction as the magnetization direction of the second fixed region 52. At this time, the magnetization of the free layer of the MTJ element 55 is oriented in the + Y direction. When the in-plane magnetization direction of the pinned layer of the MTJ element 55 is fixed in the −Y direction, the MTJ element 55 is in a high resistance state, and data “1” is written.

In the odd-numbered C10 memory cell, unlike the even-numbered row, the magnetization of the first fixed region 51 is fixed in the -Z direction and the magnetization of the second fixed region 52 is fixed in the + Z direction. When current flows from the second fixed region 52 toward the first fixed region 51, electrons flow from the first fixed region 51 to the second fixed region 52. Then, due to the effect of the spin torque, the magnetization direction of the free region 53 is in the same −Z direction as the magnetization direction of the first fixed region 51. At this time, the magnetization of the free layer of the MTJ element 55 is in the −Y direction. When the in-plane magnetization direction of the pinned layer of the MTJ element 55 is fixed in the −Y direction, the MTJ element 55 is in a low resistance state, and data “0” is written. Conversely, when a current is passed from the first fixed region 51 toward the second fixed region 52, the magnetization direction of the free region 53 is directed to the + Z direction, which is the same as the magnetization direction of the second fixed region 52. At this time, the magnetization of the free layer of the MTJ element 55 is oriented in the + Y direction. When the in-plane magnetization direction of the fixed layer of the MTJ element 55 is fixed in the −Y direction, the MTJ element 55 is in a high resistance state, and data “1” is written.

As described above, by creating fixed regions having different magnetization directions for the even-numbered and odd-numbered memory cells, the magnetization direction of the pinned layer of the MTJ element 55 can be made constant, and FIGS. The circuit shown in FIG.

Further, the memory cell layout of FIG. 18 can increase the degree of integration of the memory cells as in FIG. That is, the tip of the convex portion (M3) of the memory cell C10 faces the concave portion (the region between the end portions of the magnetic layer 50 facing each memory cell) composed of the memory cell C00 and the memory cell C01. It is arranged to fit deeply. Thereby, the same effect as in the case of FIG. 13 can be obtained.

Next, a second modification of the semiconductor memory device according to the embodiment of the present invention will be described.
FIG. 19 is a cross-sectional view showing a part of a second modification of the memory array in the semiconductor memory device according to the embodiment of the present invention. FIG. 20 is a plan view showing a part of the layout of the second modification of the memory array in the semiconductor memory device according to the embodiment of the present invention. However, FIG. 19 is a CC ′ cross-sectional view in FIG. FIG. 20 shows layers above the magnetic layer 50 in FIG. The metal layer M1 and the subsequent layers are the same as those in FIG.

19 and 20, the present method can be applied to a domain wall motion type memory element. For example, the domain wall motion type memory element includes a magnetic layer 50 having perpendicular magnetization and an MTJ element 55 having perpendicular magnetization. The magnetic layer 50 includes a first fixed region 51, a second fixed region 52, and a free region 53. The MTJ element 55 includes a free layer that also serves as the free region 53, a barrier layer 56 that is an insulating layer formed on the free region 53, and a pinned layer 57 that has a fixed magnetization direction. The MTJ element 55 changes to a low resistance state or a high resistance state depending on the magnetization direction of the free region 53, that is, the free layer. In this element, a write current is passed through the perpendicular magnetic film (magnetic layer 50), and the magnetization direction of the free region 53 can be freely changed by the effect of spin torque. In addition, since this element can write data with a small write current, low power and a reduction in cell transistor can be expected.

For example, the first transistor 11 of the memory cell C00 is a dual gate transistor. The first transistor 11 includes a diffusion layer 61-1, a diffusion layer 61-2, and a gate 62. Diffusion layer 61-1 is connected to write bit line WBL0 via contact D1. The diffusion layer 61-2 is connected to the first fixed region 51 of the magnetic layer 50 through contacts D2, M1, and V1. The gate 62 is connected to the word line WL0 and is provided immediately below the word line WL0. Similarly, the second transistor 12 includes a diffusion layer 61-1, a diffusion layer 61-2, and a gate. Diffusion layer 61-1 is connected to write bit line / WBL0 via contact D1. The diffusion layer 61-2 is connected to the second fixed region 52 of the magnetic layer 50 through contacts D2, M1, and V1. The gate 62 is connected to the word line WL0 and is provided immediately below the word line WL0. On the magnetic layer 50, the barrier layer 56 and the pinned layer 57 of the MTJ element 555 are disposed. The MTJ element 55 is connected to the upper read bit line RBL0 via the MTJ via 59.

However, although not shown, the MTJ element 55 may be disposed below the magnetic layer 50. In that case, the MTJ element 55 is connected to the lower read bit line RBL0 via the MTJ via 59. In that case, the contacts D2, M1, and V1 are provided with a sufficient height so that the read bit line RBL0 and the write bit line WBL0 do not contact each other.

Similarly, the first transistor 11 of the memory cell C01 is a dual gate transistor. The first transistor 11 includes a diffusion layer 61-1 connected to the write bit line WBL1 through a contact D1, and a diffusion layer 61 connected to the first fixed region 51 of the magnetic layer 50 through contacts D2, M1, and V1. -, Comprising a gate 62 connected to the word line WL0. The second transistor 12 is a dual gate transistor. The second transistor 12 includes a diffusion layer 61-1 connected to the write bit line / WBL1 through a contact D1, and a diffusion layer connected to the second fixed region 52 of the magnetic layer 50 through contacts D2, M1, and V1. 61-2, comprising a gate 62 connected to the word line WL0. On the magnetic layer 50, the barrier layer 56 and the pinned layer 57 of the MTJ element 555 are disposed. The MTJ element 55 is connected to the upper read bit line RBL1 via the MTJ via 59.

Similarly, the first transistor 11 of the memory cell C10 is a dual gate transistor. The first transistor 11 includes a diffusion layer connected to the write bit line / WBL0 via the contact D1, a diffusion layer connected to the first fixed region 51 of the magnetic layer 50 via the contacts D2, M1, and V1, a word line It consists of a gate connected to. The second transistor 12 is a dual gate transistor. Second transistor 12, diffusion layer connected to write bit line WBL1 via contact D1, diffusion layer connected to second fixed region 52 of magnetic layer 50 via contact D2, M1 and V1, connected to word line Composed of gates. On the magnetic layer 50, the barrier layer 56 and the pinned layer 57 of the MTJ element 555 are disposed. The MTJ element 55 is connected to the upper read bit line / RBL0 via the MTJ via 59. The same applies hereinafter.

Next, data writing will be described. For example, in the even-numbered C00 memory cell, if the magnetization of the first fixed region 51 is fixed in the + Z direction and the magnetization of the second fixed region 52 is fixed in the −Z direction, the second fixed region 52 to the first fixed region When a current is passed toward the region 51, electrons flow from the first fixed region 51 to the second fixed region 52. Then, due to the effect of the spin torque, the magnetization direction of the free region 53 is directed to the + Z direction, which is the same as the magnetization direction of the first fixed region 51. When the in-plane magnetization direction of the pinned layer 57 of the MTJ element 55 is fixed in the + Z direction, the MTJ element 55 is in a low resistance state, and data “0” is written. Conversely, when a current is passed from the first fixed region 51 toward the second fixed region 52, the magnetization direction of the free region 53 is in the same −Z direction as the magnetization direction of the second fixed region 52. When the in-plane magnetization direction of the pinned layer 57 of the MTJ element 55 is fixed in the + Z direction, the MTJ element 55 is in a high resistance state, and data “1” is written.

In the odd-numbered C10 memory cell, when the magnetization of the first fixed region 51 is fixed in the + Z direction and the magnetization of the second fixed region 52 is fixed in the −Z direction, the second fixed region 52 to the first fixed region 51 When an electric current is passed toward, electrons flow from the first fixed region 51 to the second fixed region 52. Then, due to the effect of the spin torque, the magnetization direction of the free region 53 is directed to the + Z direction, which is the same as the magnetization direction of the first fixed region 51. When the in-plane magnetization direction of the pinned layer 57 of the MTJ element 55 is fixed in the + Z direction, the MTJ element 55 is in a low resistance state, and data “0” is written. Conversely, when a current is passed from the first fixed region 51 toward the second fixed region 52, the magnetization direction of the free region 53 is in the same −Z direction as the magnetization direction of the second fixed region 52. When the in-plane magnetization direction of the pinned layer 57 of the MTJ element 55 is fixed in the + Z direction, the MTJ element 55 is in a high resistance state, and data “1” is written.

In the magnetic layer 50 of the domain wall motion type memory cell shown in FIG. 20, the width in the Y direction of the free region 53 (the free layer of the MTJ element 55) is wider than that of the first and second fixed

layer regions

51 and 52. Has characteristics. As a result, the energy of the domain wall becomes higher in the free region 53, and the domain wall tends to stay at a bistable position at the boundary between the free region 53 and the first and second fixed

layer regions

51 and 52. That is, it is possible to prevent a failure mode in which the domain wall stops in the free area when data is written, or the domain wall to move to the free area during data holding.

Further, the memory cell layout of FIG. 20 can increase the degree of integration of the memory cells as in FIG. That is, the tip of the convex portion (M3) of the memory cell C10 faces the concave portion (the region between the end portions of the magnetic layer 50 facing each memory cell) composed of the memory cell C00 and the memory cell C01. It is arranged to fit deeply. Thereby, the same effect as in the case of FIG. 13 can be obtained.

As described above, according to the present invention, it is possible to obtain a semiconductor memory device that has a high degree of integration of memory cells and can perform high-speed operations (read operation and write operation) similar to SRAM.

Although the present invention has been described above with reference to the embodiment, the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. Further, the embodiments can be applied to each other as long as no technical contradiction occurs.

This application is based on Japanese Patent Application No. 2008-272870 filed on Oct. 23, 2008 and claims the benefit of the priority of the application, and the disclosure of that application should be cited Is incorporated here as it is.

Claims

Comprising a memory array comprising a plurality of memory cells;
The plurality of memory cells include
A first memory cell and a third memory cell disposed along one of the even-numbered row and the odd-numbered row;
A second memory cell disposed along the other,
Each of the plurality of memory cells includes
Including a magnetoresistive element connected at one end to the wiring in the cell;
In the central part of at least one side of the side along the row direction has a convex part including the in-cell wiring,
The convex portion of the second memory cell is arranged facing a concave portion formed between the convex portion of the first memory cell and the convex portion of the third memory cell.
The semiconductor memory device according to claim 1,
The in-cell wiring is a write line for writing data into the magnetoresistive element by a magnetic field or spin torque induced by a write current flowing through the semiconductor memory device.
The semiconductor memory device according to claim 2,
The write line is
The convex portion to which the magnetoresistive element is connected;
And a branch portion provided on both sides of the convex portion and extending in the row direction.
The semiconductor memory device according to claim 3,
The layout of the write line of the second memory cell is different from the layout of the write line of the first memory cell with respect to an axis in the row direction passing through a boundary between the first memory cell and the second memory cell. A semiconductor memory device provided by being inverted and translated in the row direction by a predetermined interval.
The semiconductor memory device according to claim 3,
The write line is plane-symmetric with respect to a plane that passes through the center of the write wiring in the row direction and is substantially perpendicular to the substrate.
The semiconductor memory device according to claim 3,
The magnetoresistive element is disposed above or below a region of the convex portion of the write line.
The semiconductor memory device according to claim 3,
The tip of the convex portion of the write line of the second memory cell is connected to the tip of the convex portion of the write line of the first memory cell and the tip of the convex portion of the write line of the third memory cell. A semiconductor memory device located closer to the first memory cell and the third memory cell than a connecting line.
The semiconductor memory device according to claim 1,
The in-cell wiring is a read line through which a read current flowing in the magnetoresistive element passes. Semiconductor memory device.
The semiconductor memory device according to claim 8,
Each of the plurality of memory cells includes
A write line extending in the row direction and provided near the magnetoresistive element on the side opposite to the read line;
The center of gravity of the magnetoresistive element is biased from the central axis in the row direction of the write line,
The read line extends in a direction substantially perpendicular to the row direction.
The semiconductor memory device according to claim 9,
The layout of the convex portion of the second memory cell is such that the layout of the convex portion of the first memory cell is relative to the axis in the row direction passing through the boundary between the first memory cell and the second memory cell. A semiconductor memory device provided by being inverted and translated in the row direction by a predetermined interval.
The semiconductor memory device according to claim 9,
The tip of the convex part of the second memory cell is more than the line connecting the tip part of the convex part of the first memory cell and the tip part of the convex part of the third memory cell, and A semiconductor memory device on a side closer to the third memory cell.
The semiconductor memory device according to claim 9,
The write line includes a magnetic material,
The magnetic body is
Two fixed regions with fixed magnetization directions;
A free region provided between the two fixed regions, the direction of magnetization of which changes, and
The semiconductor memory device, wherein the magnetization of the free region is controlled by the direction of the write current flowing from one of the two fixed regions to the other.
The semiconductor memory device according to claim 2,
The write line includes a magnetic material,
The magnetic body is
Two fixed regions with fixed magnetization directions;
A free region provided between the two fixed regions, the direction of magnetization of which changes, and
The semiconductor memory device, wherein the magnetization of the free region is controlled by the direction of the write current flowing from one of the two fixed regions to the other.
The semiconductor memory device according to claim 13,
The convex portion is formed from the free region,
Branch portions provided on both sides of the convex portion and extending in the row direction are formed from the two fixed regions. Semiconductor memory device.
15. The semiconductor memory device according to claim 1, wherein:
Each of the plurality of memory cells includes
A first transistor including a first diffusion layer and a second diffusion layer;
A second transistor including a third diffusion layer and a fourth diffusion layer;
The semiconductor memory device, wherein the second diffusion layer and the third diffusion layer are electrically connected via the write line.
The semiconductor memory device according to claim 15,
The fourth diffusion layer of the first memory cell and the first diffusion layer of the second memory cell are shared;
A semiconductor memory device in which the fourth diffusion layer of the second memory cell and the first diffusion layer of the third memory cell are shared.