WO2010043993A1

WO2010043993A1 - Amplifier

Info

Publication number: WO2010043993A1
Application number: PCT/IB2009/054317
Authority: WO
Inventors: Gerben Willem De Jong; Dennis Jeurissen; Jan Van Sinderen; Frank Harald Erich Ho Chung Leong
Original assignee: Nxp B.V.
Priority date: 2008-10-15
Filing date: 2009-10-02
Publication date: 2010-04-22

Abstract

An amplifier (200) for an input stage of a radio receiver, the amplifier comprising: an inverting gain stage amplifier (210) comprising a complementary pair of transistors; a first series feedback impedance (2Z_sf) connected between the inverting gain stage amplifier and a supply voltage connection; a second series feedback impedance (2Z_sf) connected between the inverting gain stage amplifier and a ground voltage connection; a decoupling capacitor (C_d1) connected between the first and second series feedback impedance; and a parallel feedback impedance (Z_p) connected between the output and input of the amplifier.

Description

AMPLIFIER

FIELD OF THE INVENTION

The invention relates to wide band low noise amplifiers for use in radio receivers.

BACKGROUND OF THE INVENTION A typical modern state-of-the-art radio receiver 100, as shown schematically in figure 1, is conventionally formed by a chain of components comprising the following: an antenna 101, a band-pass filter (BPF) 102, a low-noise amplifier (LNA) 103, a complex mixer 104a, 104b, a quadrature local oscillator (LO) 105, intermediate-frequency (IF) filter/amplifiers 106a, 106b, analogue-to-digital converters (ADCs) 107a, 107b, and a digital baseband (BB) processor 108.

The antenna 101 converts the radio-frequency (RF) electromagnetic (EM) waves to an electrical signal. This electrical signal is filtered by the BPF 102, which lets through the frequency band of interest and suppresses frequencies outside the desired band. The resulting signal is subsequently amplified by the LNA 103 to make the signal more robust against noise that may be introduced by the subsequent stages. The mixer 104a, 104b converts the received and amplified signals down in frequency by a fixed amount. This fixed amount is equal to the frequency of a single-tone signal produced by the LO 105. The LO is tuneable to a desired radio frequency (RF) signal. The frequency-down-converted signals are known as IF (intermediate frequency) signals. These IF signals are filtered by an IF filter and subsequently amplified by an IF amplifier. These may be combined in an IF filter/amplifier 106a, 106b. The resulting analogue signals are converted to the digital domain by the analog to digital converters (ADC) 107a, 107b. The signals are then demodulated in the digital domain by the baseband processor 108. Further functions such as channel filtering, de- rotation, offset correction and the like may also be carried out in the digital domain. Typical wide-band low-noise amplifiers currently in use in modern radio receivers may suffer from one or more of the following problems: i) Amplifier non-linearity, caused by characteristics and/or configuration of the active components of the amplifier; ii) Saturation, due to strong interference signals; and iii) Noise, e.g. generated by the LNA, which negatively affects the signal-to-noise ratio (SNR) of the amplifier.

OBJECT OF THE INVENTION It is an object of the invention to address one or more of the above mentioned problems.

SUMMARY OF THE INVENTION

In accordance with the invention there is provided an amplifier for an input stage of a radio receiver, the amplifier comprising: an inverting gain stage amplifier comprising a complementary pair of transistors; a first series feedback impedance connected between the inverting gain stage amplifier and a supply voltage connection; a second series feedback impedance connected between the inverting gain stage amplifier and a ground voltage connection; a decoupling capacitor connected between the first and second series feedback impedances; and a parallel feedback impedance connected between the output and input of the amplifier.

The proposed LNA exhibits a high linearity due to the overall dual-loop feedback and high loop-gain of the amplifier. The input impedance and gain are accurately defined by linear passive feedback elements. Hence the non-linear active components do not significantly affect the overall linearity. The amplifier may comprise a plurality of said inverting gain stage amplifiers connected in a cascade configuration between an input and an output of the amplifier. The open-loop gain of the amplifier can thereby be increased, and reverse isolation is improved. In such an arrangement, the first and second series feedback impedances are connected to each of the plurality of inverting gain stage amplifiers. The number of inverting gain stage amplifiers in the amplifier is necessarily an odd number, i.e. 3, 5, 7, 9 etc. One or more non-inverting stages may also be included.

The complementary pair of transistors in each of the inverting gain stage amplifiers can be either a CMOS pair, i.e. an NMOS and a PMOS transistor, or a bipolar pair, i.e. an NPN and a PNP transistor. Making at least some of the passive feedback elements programmable, opens the way to the performance of the amplifier being changed on demand, allowing for software-defined radio (SDR). This may be achieved by having one or more of the feedback impedances composed of a parallel network of switchable impedances configured to provide a plurality of values for the feedback impedance in question. The switchable impedances may be switched in and out by means of voltage signals applied to respective transistor switches.

In each of the inverting gain stage amplifiers, a further complementary pair of transistors may be provided, connected in a cascode configuration. Advantages of the invention include one or more of the following:

Large signals due to strong interferers can efficiently be handled by the class- AB inverting gain stages.

A large-trans-conductance common source (or emitter) input stage and a properly designed feedback network allow for low-noise behaviour. Since a common source (or emitter) stage has both voltage gain and current gain, the voltage and current noise of the second and subsequent stages do not play an important role in the over-all noise behaviour of the amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS figure 1 is a schematic diagram of a modern radio receiver; figure 2 is a circuit diagram illustrating the topology of a low noise amplifier according to the invention; figure 3 illustrates a symbol used to represent an inverting gain stage for use in a low noise amplifier; figure 4a is a circuit diagram of an exemplary inverting gain stage implemented with complementary NMOS and PMOS transistors; figure 4b is a circuit diagram of an exemplary inverting gain stage implemented with NPN and PNP transistors; figure 5a is a circuit diagram of an exemplary inverting gain stage implemented with complementary NMOS and PMOS transistors together with additional cascode transistors; figure 5b is a circuit diagram of an exemplary inverting gain stage implemented with NPN and PNP transistors together with additional cascode transistors; figure 6 is a circuit diagram of an exemplary amplifier implemented with three inverting gain stages; figure 7 is a circuit diagram of an alternative exemplary amplifier implemented with three inverting gain stages; figure 8 is a circuit diagram showing the active part of an exemplary amplifier implemented with five inverting gain stages; figure 9 is a circuit diagram showing an alternative active part of an exemplary amplifier implemented with five inverting gain stages; figure 10 is a circuit diagram of an alternative exemplary amplifier; figure 11 is a circuit diagram of a further alternative exemplary amplifier; figure 12 is a schematic diagram showing a test bench view of an exemplary low noise amplifier; figure 13 is a schematic diagram showing a test bench view of the active component of the low noise amplifier of figure 12; figure 14 is a schematic diagram showing a test bench view of an exemplary programmable impedance arrangement for use with the low noise amplifier of figures 12 and 13; and figure 15 is a circuit diagram of a NMOS transistor with modelled parasitic capacitances.

SPECIFIC DESCRIPTION OF THE EMBODIMENTS

The basic topology of a low noise amplifier circuit 200 according to the invention is shown in figure 2. V_s represents the source voltage, Z_s represents the source impedance, and C_c a coupling capacitance. Together these form the Thevenin equivalent of the source 230 (i.e. the antenna/filter combination). A load 240 on the LNA is represented by a load impedance Z/, which is connected to ground by a decoupling capacitance Cd2- A supply voltage V_sup is provided by a voltage supply 250.

The LNA itself 220 consists of an active part 210 (described below), two series-feedback impedances 2Z_sf, a parallel feedback impedance Z_p, and a decoupling capacitor Cdi. The two series feedback impedances 2Z_sf are connected across the active part 210 and to the supply voltage line V_sup and ground. The series feedback impedances 2Z_sf can be considered to be connected in parallel for the RF signal, due to the equivalence of supply and ground and the presence of the decoupling capacitor CdI across the active part 210. Although the series feedback impedances are shown in figure 2 as having the same value, the values do not necessarily need to be the same. The active low-noise input impedance Z₁ of the circuit is a result of the Miller effect of parallel-feedback impedance Z_p, determined according to the following formula:

z. = ^Z' (1)

1 - 4.

where A_v represents the (loaded) voltage gain.

Hence Z_p can be calculated when Z₁ and A_v are given:

Z_p = (\ - A_v)Z, (2)

The voltage gain is given by:

Hence Z₅/ can be calculated when_^4_v, Z_/, and Z₁ are given:

Alternatively, the value of Z/ can be evaluated when A_v, Z₁, and Z_s/ are given:

^Z' ⁼ 1 ' 1 ⁽⁵⁾

- ΛA, z, - z,

In a limited number of cases, the overall load impedance Z/ will be formed by the parallel connection of a useful load (the input impedance of the next stage for example) in combination with a dummy load chosen to arrive at a required value for Z_/.

Normally, the resistive part of the series feedback impedance Zs/ will be chosen small compared to the resistive part of the source impedance Z_s in order to keep the noise figure low. Equations 1 to 5 above demonstrate that the main characteristics of the LNA are determined by the linear passive feedback elements and not by the non-linear active components making up the active part 210.

The active part 210 contains the active elements of the amplifier, either in the form of MOS- or bipolar transistors (or possibly a combination of both types). The active part can be considered as a cascade of an odd number of inverting gain stages, otherwise the input impedance becomes negative and the amplifier becomes unstable. If desired, non- inverting gain stages might also be applied and the total number of stages chosen so as to provide a stable amplifier. A typical non-inverting gain stage would, for example, be a common drain/collector stage, a common gate/base stage or a combination of both, resulting in a differential pair. A pseudo-differential implementation of the LNA might be considered, for example with one amplifier connected to a positive input and another to a negative input, resulting in two single-ended amplifiers with no common mode suppression (unlike for a true differential amplifier). This enables the possibility of active or passive cross connections, which allows for a greater degree of design freedom, for example to improve frequency compensation to improve stability.

Each inverting gain stage 310 can be represented with the symbol shown in figure 3. One such inverting gain stage 310 (or inverter for short) can be implemented with a complementary pair of transistors, either using one NMOST 410 and one PMOST 420, as shown in figure 4a, or with one NPN transistor 430 and one PNP transistor 440, as shown in figure 4b.

The inverting gain stage 310 could alternatively be implemented with additional CMOS cascode-transistors 510, 520, as shown in figure 5a for a NMOST/PMOST implementation and bipolar transistors 530, 540 in figure 5b for a NPN/PNP transistor implementation.

The minimum number of inverters 310 for the active part 210 is one. However, in such a case the overall loop-gain will not be sufficient. Figure 6 illustrates an exemplary embodiment where the active part of the amplifier is implemented with three inverters 310a, 310b, 310c. To improve the phase margin and therefore the stability, frequency compensation might be applied, as shown in figure 7. Miller capacitors C_mi and C_m3 cause pole splitting around the input stage and output stage respectively. R_mi and R_m3 prevent right- half-plane zeroes from appearing in the pole-zero diagram. Finally, the capacitors C_s, C_p, and Ci produce two phantom zeroes, i.e. zeros which are present in the loop gain function but not in the closed-loop transfer function. A third phantom zero might be generated by putting a small inductor in series with 2Z_sf. However, in general this is not necessary.

More freedom with respect to frequency compensation might be obtained by using a pseudo-differential implementation of the LNA. In that case cross connections can be implemented. However, care should be taken to ensure common-mode stability, for example by means of an additional common-mode loop.

In order to improve the linearity even further, the loop-gain of the amplifier could be increased by extending the number of inverting gain stages (inverters) to 5, 7, 9, etc. In figure 8 an example where the active part has been implemented with five inverters 810a- e is shown. For simplicity, the series impedances which prevent right-half-plane zeroes from appearing are not shown in this figure, but can be assumed to be present in series with each Miller capacitor C_mi, C_m2, C_m3. For the same reason, the series feedback is also not shown.

In addition to the three inner Miller capacitors C_mi, C_m3, and C_ms, an outer Miller capacitor C_m35 is provided, connected across stages 3 to 5. Alternatively, an outer Miller capacitor C_mi3 may be provided, connected across stages 1 to 3, as shown in figure 9.

Returning to the basic schematic diagram of the low noise amplifier 200 shown in figure 2, the special case of a voltage gain of around 0 dB could be problematic since the output stage 240 then has to cope with twice the output voltage swing. This is because the output voltage and the input voltage have the opposite phase. In order to improve the voltage-handling capabilities for this special case, an additional impedance Z_1S could be added in series with the input to the LNA 220, as shown in figure 10. The amplifier circuit 200 is otherwise the same as that in figure 2.

The resistive part of Z_1S adds noise to the input signal of the amplifier. Feedback impedances Z_p, Z_Sf, and Z/ should be changed in order to provide the same input impedance Z₁ as before. The voltage swing on the sources/emitters of the output stage is then reduced.

A series impedance Z_os may alternatively or additionally be added to the output side of the amplifier, in order to allow for the desired value for the output impedance. This modification is shown in the amplifier circuit 1100 of figure 11. In this circuit, a dummy load Zu is provided in parallel with the actual load impedance Z/.

A further possible modification is to provide some or all of the passive feedback elements in the amplifier as programmable impedances. The amplifier can then be configured by means of software instructions, allowing the amplifier parameters to be altered as required. Such implementations can make such an amplifier circuit suitable for use with software-defined radio (SDR) systems.

The particular specifications of a given LNA according to the invention are a function of the particular values for the components used in the circuit. As an exemplary worked embodiment, figures 12 to 15 illustrate simulation results obtained for a 65 nm CMOS-type amplifier having an IIP3 of 20 dBm, an IIP2 of 63 dBm, a noise figure of 2.0 dB, a voltage gain of 15 dB, an S₁₁ of -23 dB, and a -3 dB-bandwidth of 4 GHz, all at a total current consumption of 13 niA. IIP refers to the Input-referred Intercept Point, being the extrapolated value where the distortion component considered has equal amplitude to the wanted signal. IIP2 and IIP3 refer to the 2nd and 3rd order distortion, respectively. The scatter parameter Sn represents the input reflection coefficient. The supply voltage across the inverters amounts to 1.2 V. The overall current consumption can be lowered further at the expense of a higher noise figure, for example 3.3 dB at 7 mA or 4.3 dB at 3.6 mA. Figure 12 shows a schematic circuit diagram of the LNA test bench, with the amplifier circuit 1210 connected to various passive components including inductances and capacitances that take into account the inductive and capacitive effects of bond wires and bond pads.

Figure 13 illustrates the components of the amplifier circuit 1210 of figure 12, with three inverting gain stages 1310a, 1310b, 1310c connected in a cascade between an input 1320 and output 1330 of the circuit 1210. To support SDR functionality for the amplifier, feedback impedances 1340a-c and load impedance 1350 can be configured to be programmable. An implementation of an exemplary parallel-feedback impedance network is shown in figure 14. Impedances RlO, R9, R8, R7 and RO are selectable by means of MOS transistors MN7, MN6, MN5, MN4 and MN3, with a maximum value impedance R8 in default of any of the other impedances being selected. Voltage signals VdO, VdI, Vd2, Vd3, Vd4 can be applied to the transistors MN3, MN4, MN5, MN6 or MN7 to select one or more of impedances RO, R7, R8, R9 or RlO respectively. The other programmable impedances may be implemented in a similar fashion.

Figure 15 illustrates an exemplary MO S -transistor circuit model, comprising additional capacitances for modelling the layout-parasitic capacitances. The NMOST version is shown in figure 15, and the PMOST version is similar.

Applications for the low noise amplifier circuit according to the invention include multi-band multi-mode multi- standard radio receivers, software-defined radio (SDR), radio receivers for broadcast, radio receivers for cellular telephone applications (such as GSM, EDGE, UMTS, 4G and the like) and wireless connectivity (WPAN, BlueTooth, WLAN), among others.

Other embodiments are intentionally within the scope of the invention as defined by the appended claims.

Claims

CLAIMS:

1. An amplifier for an input stage of a radio receiver, the amplifier comprising: an inverting gain stage amplifier comprising a complementary pair of transistors; a first series feedback impedance connected between the inverting gain stage amplifier and a supply voltage connection; a second series feedback impedance connected between the inverting gain stage amplifier and a ground voltage connection; a decoupling capacitor connected between the first and second series feedback impedances; and - a parallel feedback impedance connected between the output and input of the amplifier.

2. The amplifier of claim 1 comprising a plurality of said inverting gain stage amplifiers connected in a cascade configuration between an input and an output of the amplifier.

3. The amplifier of claim 2 wherein the first and second series feedback impedances are connected to each of the plurality of inverting gain stage amplifiers.

4. The amplifier of claim 2 or claim 3 wherein the plurality of said inverting gain stage amplifiers consists of an odd number of inverting gain stage amplifiers.

5. The amplifier of claim 1 wherein the complementary pair of transistors comprise NMOS and PMOS transistors connected in a common source arrangement.

6. The amplifier of claim 1 wherein the complementary pair of transistors comprise NPN and PNP bipolar transistors connected in a common emitter arrangement.

7. The amplifier of claim 1 wherein one or more of the feedback impedances is composed of a network of switchable impedances configured to provide a plurality of values for the feedback impedance.

8. The amplifier of claim 1 wherein the inverting gain stage amplifier comprises a further complementary pair of transistors connected in a cascode configuration with the complementary pair of transistors.

9. The amplifier of claim 1 comprising three of said inverting gain stage amplifiers connected to one another in a cascade arrangement from an input to an output of the amplifier.

10. The amplifier of claim 9 wherein frequency compensation capacitors are connected across a first one of the inverting gain stage amplifiers connected to the input of the amplifier and across a third one of the inverting gain stage amplifiers connected to the output of the amplifier.

11. The amplifier of claim 1 comprising five of said inverting gain stage amplifiers, first to fifth inverting gain stage amplifiers being connected to one another in a cascade arrangement from an input to an output of the amplifier.

12. The amplifier of claim 11 wherein frequency compensation capacitors are connected across the first, third and fifth inverting gain stage amplifiers.

13. The amplifier of claim 12 wherein a further frequency compensation capacitor is connected between an input of the first inverting gain stage amplifier and an output of the third inverting gain stage amplifier.

14. The amplifier of claim 12 wherein a further frequency compensation capacitor is connected between an input of the third inverting gain stage amplifier and an output of the fifth inverting gain stage amplifier.

15. The amplifier of claim 1 wherein the feedback impedances are resistive.

16. The amplifier of claim 1 comprising one or more non- inverting gain stage amplifiers.

17. A radio receiver having an input stage comprising an amplifier according to any one of claims 1 to 16.