WO2010041793A1

WO2010041793A1 - Method and apparatus for transformation of memory access interface

Info

Publication number: WO2010041793A1
Application number: PCT/KR2008/007656
Authority: WO
Inventors: Jin-Hyeock Im
Original assignee: Chips & Media, Inc.
Priority date: 2008-10-07
Filing date: 2008-12-24
Publication date: 2010-04-15
Also published as: KR20100039147A; KR101035732B1

Abstract

Memory access interface transformation method and apparatus are provided. The memory access interface transformation method includes: receiving a data processing command for a memory area of a second client from a first client; acquiring access interface information for the memory area of the second client from the data processing command; and converting access in¬ formation of the first client into access information of the second client by using the access interface information. Accordingly, the clients having different memory access interfaces may effectively share the memory.

Description

METHOD AND APPARATUS FOR TRANSFORMATION OF MEMORY ACCESS INTERFACE

Technical Field

[1] The present invention relates to a method and apparatus for transformation of memory access interface. Background Art

[2] Generally, electronic apparatuses including conventional computers are configured with several clients, e.g., CPUs or graphic devices. Such clients read necessary data from an external memory, or write the read data thereto. However, two problems largely occur when such clients use the memory.

[3] First, when using the memory, each client uses a logic address or a linear address converted from the logic address in order to designate locations of data. In the procedure of converting or mapping the logic address or the linear address into a physical address on a memory, each client may adopt a different conversion scheme (this may be changed according to actual memory specifications or other limitations). For example, when a linear address is converted into a physical address, the orders of a bank address and a row address included in the physical address are different. A certain client may adopt a scheme that locates a bank address prior to a row address, and another client may adopt a scheme that locates a row address prior to a bank address.

[4] Second, endianness of each client is problematic. Endianness refers to a byte order of data stored in a memory. When the least significant bit (LSB) is located at a lower address, it is simply referred to as a little endian. When the most significant bit (MSB) is located at a lower address, it is simply referred to as a big endian. There is no problem if the respective clients use a single endian in a single system. However, with the recent development of technology, clients having different endians tend to be integrated into a single system. Therefore, when a certain client intends to refer to data of other client, the different endianness may cause a problem.

[5] In order to solve problems caused by different address conversion schemes and endians between clients, that is, different memory access interfaces, several system configurations have been attempted. One method is to match interfaces of clients inside the system with a single address conversion scheme and a single endianness. That is, if each client is designed to be suitable for a decided single address conversion scheme and single endianness, the decided address conversion scheme and endianness are used as they are. If not, an interface transformer such as an address transformer and an endianness transformer is added to each client. In this case, however, there are problems in that the address converter and the endianness converter are required for each client, it is difficult to flexibly cope with external variation because the system operates based on only the specific address conversion scheme and endianness, and the efficient operation of each client cannot be ensured.

[6] If the use of hardware methods such as the interface transformer within the system is impossible, software methods must be used. That is, data is read or written using an address or endianness conversion program installed in a programmable core such as a CPU or a digital signal processor (DSP). In the case of using such methods, it is difficult to expect efficient performance of each client or overall system due to limitations of software approaches, and computing power of the programmable core is consumed.

[7] In addition to the above-described two problems, there may be another problem about endianness when two systems have different data bus widths. When assuming that a device having 32-bit data buses is connected to a device having 64-bit data buses, it is necessary to select the preference of LSB and MSB when 64-bit data are divided by 32 bits. When next 32 bits are mapped into 32 bits, the conversion of endianness is required. For example, when assuming that 64 bits are divided on a byte basis and expressed with 8 bytes and data ABCDEFGH is transmitted to a 32-bit system, four cases are possible: ABCD EFGH, DCBA HGFE, EFGH ABCD, and HGFE DCBA.

[8] Consequently, there is a need for address conversion and endianness conversion management methods which can solve the above-described problems, flexibly cope with temporal variation of the system, and ensure a more efficient operation. Disclosure of Invention Technical Problem

[9] An embodiment of the present invention is directed to a method and apparatus which enable clients to operate with the maximized performance by making it possible for the respective clients of a single system to read or write their desired data through the memory, without regard to the address conversion scheme and endianness of other clients.

[10] Another embodiment of the present invention is directed to a method and apparatus which are capable of coping with the system's external environment or internal state or the variation of each client by making it possible to change the address conversion scheme of each client or the setting of the endianness changed in real time according to the necessity of a system operator or a system itself.

[11] Another embodiment of the present invention is directed to a method and apparatus which support various address conversion schemes and endianness of various clients simultaneously by changing the address conversion scheme and endianness of other clients.

[12] Other objects and advantages of the present invention can be understood by the following description, and become apparent with reference to the embodiments of the present invention. Also, it is obvious to those skilled in the art to which the present invention pertains that the objects and advantages of the present invention can be realized by the means as claimed and combinations thereof. Technical Solution

[13] In accordance with an aspect of the present invention, a memory access interface transformation method includes: receiving a data processing command for a memory area of a second client from a first client; acquiring access interface information for the memory area of the second client from the data processing command; and converting access information of the first client into access information of the second client by using the access interface information.

[14] In accordance with another aspect of the present invention, a memory access interface transformation method includes: receiving a data read command for a memory area of a second client from a first client; acquiring access interface information for the memory area of the second client from the data read command; and converting access information of the first client into access information of the second client by using the access interface information.

[15] In accordance with another aspect of the present invention, a memory access interface transformation method includes: receiving a data write command for a memory area of a second client from a first client; acquiring access interface information for the memory area of the second client from the data write command; and converting access information of the first client into access information of the second client by using the access interface information.

[16] In accordance with another aspect of the present invention, a memory access interface transformation apparatus includes: a command reception unit configured to receive a data processing command for a memory area of a second client from a first client; and an access information conversion unit configured to acquire access interface information for the memory area of the second client from the data processing command, and convert access information of the first client into access information of the second client by using the access interface information.

Advantageous Effects

[17] As described above, the respective clients constituting the single system may read or write their desired data through the memory, without regard to the address conversion scheme and endianness of other clients. Therefore, the respective clients may be designed to operate with the maximized performance. [18] Furthermore, since the address conversion scheme of each client or the setting of the endianness is changed in real time according to the necessity of a system operator or a system itself, it is possible to flexibly cope with the system's external environment or internal state or the variation of each client. [19] Moreover, by changing the address conversion scheme and endianness of other clients, various address conversion schemes and endianness of various clients may be simultaneously supported.

Brief Description of Drawings [20] Fig. 1 is a configuration diagram illustrating a connection relationship of a memory access interface transformation apparatus, clients, and a memory in accordance with an embodiment of the present invention. [21] Fig. 2 is a configuration diagram of the memory access interface transformation apparatus 108 in accordance with an embodiment of the present invention. [22] Fig. 3 illustrates a real memory configuration and real memory map for explaining a memory access interface transformation method in accordance with an embodiment of the present invention. [23] Fig. 4 is a flowchart illustrating a procedure of processing a data read command in accordance with an embodiment of the present invention. [24] Fig. 5 is a flowchart illustrating a procedure of processing a data write command in accordance with an embodiment of the present invention. [25] Fig. 6 is a flowchart illustrating a process 406 of converting an access information of a first client into an access information of a second client in Fig. 4.

Best Mode for Carrying out the Invention [26] The above objects, features and advantages will be described below in detail with reference to the accompanying drawings, and the technical spirit of the invention can be easily carried out by those skilled in the art. Moreover, detailed description related to well-known functions or configurations will be ruled out in order not to unnecessarily obscure subject matters of the present invention. [27] Hereinafter, preferred embodiments of the present invention will be described in detail. Like reference numerals are used to refer to like elements throughout the drawings. [28] The term 'memory access interface' refers to a variety of protocols for each client to access a memory. The memory access interface include 'memory access information' such as address conversion scheme or address representation scheme of each client, and 'type of data' such as endianness. [29] In addition, specific bits of a certain address are represented by [3:0]. This represents a total four bits from the zeroth bit to the third bit among the entire bits.

[30] Fig. 1 is a configuration diagram illustrating a connection relationship of a memory access interface transformation apparatus, clients, and a memory in accordance with an embodiment of the present invention.

[31] Referring to Fig. 1, the first client 102, the second client 104, and the third client 106 use the memory 110 to read or write data. The clients refer to constituent elements, such as CPUs, bit-stream modules, and graphic modules, which constitute a single system and use the memory 110 to read or write data. Although the first to third clients 102, 104 and 106 are illustrated in Fig. 1 for convenience's sake, it is apparent that a larger number of clients may be provided.

[32] As illustrated in Fig. 1, storage areas for the respective clients are allocated in the memory 110. For example, when the capacity of the memory 110 is 256 MB (Mega Byte), 64 MB may be allocated to CPU data, 32 MB may be allocated to bit-stream data and graphic data, respectively, and 64 MB may be allocated to video and auxiliary data. Furthermore, addresses for accessing the real memory may also be determined according to the allocation of the storage areas for the respective clients.

[33] As such, the first client 102, the second client 104, and the third client 106 access the memory 110, and read or write data. Meanwhile, in such an operation, the memory access interfaces for the respective clients, for example, memory access information (including an address conversion scheme) for the respective memory areas or en- dianness used by the respective clients, may be different. Therefore, as described above, when a certain client intends to access a memory area of other client and read or write data, a problem is caused by the different memory access interfaces.

[34] In accordance with the embodiment of the present invention, when a certain client accesses a memory area of other client having a different memory access interface and read or write data, the memory access interface transformation apparatus 108 located between each client and the memory 110 transforms the memory access interface.

[35] For further understanding of the invention, the following description will be made taking an example of memory access information of each client, specifically, address conversion scheme for each client.

[36] When accessing a real memory, addresses of the clients using a typical linear address representation scheme may be converted in various methods according to actual memory specifications or limitations. For example, when the real memory is an external SDRAM, the SDRAM have three address components, that is, a bank address (BA), a row address (RA), and a column address (CA). Therefore, the following two methods are generally used as the method of converting linear addresses into physical addresses, while maintaining the format of the linear addresses as it is. [37]

[38] A. LA => BA : RA : CA

[39] B. LA => RA : BA : CA

[40] where LA represents a linear address.

[41]

[42] For example, when assuming that LA, BA, RA, and CA are 22 bits, 2 bits, 12 bits, and 8 bits, respectively, the case of the format A is mapped as follows: LA[21:20] => BA[l:0], LA[19:8] => RA[I hO], LA[7:0] => CA[7:0], and the case of the format B is mapped as follows: LA[21:10] => RA[I hO], LA[9:8] => BA[l:0], LA[7:0] => CA[7:0].

[43] In the case of the format A, a single bank of the SDRAM may be considered as a single bus memory. When low power characteristic is important, the format A is advantageous because the banks can be individually on/off. In addition, the format A is adopted when the number of the clients using the memory is small, and different banks are mapped to the respective clients.

[44] The format B is used when a more efficient memory operation than the format A is wanted. That is, due to characteristics of the SDRAM in which the respective banks are pre-charged and row-opened, a bank charge is actively used for suppressing the frequent pre-charge and row-open, which is called a bank interleaving. Therefore, the format B may obtain higher memory bandwidth than the format A. Hence, when the memory bandwidth is an important factor, the format B is preferred to the format A.

[45] When the linear address is unnecessary, the format B may be developed in a more extreme format which is capable of further maximizing the bank interleaving. In particular, a 2-D map or a tiled map is used when data is arranged not 1-D manner but 2-D manner. The 2-D map is a scheme proposed for application products and is used by creating a conversion formula. Therefore, a variety of conversion schemes have been proposed and used. As example of a conversion scheme used in an MPEG video decoder is as follows.

[46] C. Display address (x[9:0], y[9:0]) => SDRAM address (RA[11:0], BA[l:0],

CA[7:0])

[47] - x[2:0] => CA[2:0]

[48] - y[2:0] => CA[5:3]

[49] - x[3] => BA[O]

[50] - y[3] => BA[I]

[51] - x[5:4] => CA[7:6]

[52] - x[10:6] => RA[4:0]

[53] - y[10:4] => RA[11:5]

[54] [55]

[56] *The above-described conversion scheme or mapping is merely exemplary, and a variety of methods may also be used in the real memory.

[57] In Fig. 1, the memory access interface transformation apparatus 108 transforms the different memory access interfaces based on the clients and thus enables a certain client to read or write data in a memory area of other client, regardless of the memory access interface.

[58] Fig. 2 is a configuration diagram of the memory access interface transformation apparatus 108 in accordance with an embodiment of the present invention.

[59] Referring to Fig. 2, the memory access interface transformation apparatus 108 may include a command reception unit 202, a control register 204, a tag memory 206, an access information conversion unit 208, a data type conversion unit 210, and a command processing unit 212. In addition, the access information conversion unit 208 may include an access information division unit 208a and an access information merging unit 208b.

[60] The command reception unit 202 receives a data processing command for a memory area of the second client from the first client. In this embodiment, the data processing command includes a data read command or a data write command. The data processing command may have a format of (linear address, read or write command, read or write number), e.g., (0x1236, read, 3) or (0x1234, write, 5). For example, in the case of (0x1236, read, 3), 3-byte successive data starting from a position corresponding to 0x1236 is read, or successive data are read three times. Furthermore, when the write command is included in the data processing command, the command reception unit 202 may receive data the first client wants to write in the memory, together with the data processing command, from the first client.

[61] The control register 204 controls the access information conversion unit 208 and the data type conversion unit 210 in order to execute the data processing command received through the command reception unit 202. In an embodiment which will be described later, the control register 204 refers the memory access interface information of the respective clients, which is previously set based on the access information on the memory the memory area of the second client obtained from the data processing command, and converts the access information of the first client into the access information of the second client. Therefore, the conversion of the access information such as the address conversion by the access information conversion unit 208, or the data type conversion such as the endianness conversion by the data type conversion unit 210 may be achieved by referring the memory access interface information previously set to the control register 204.

[62] The tag memory 206 serves as a temporary storage space, and stores the access interface information on the memory area of the second client, which is contained in the data processing command received through the command reception unit 202. For example, the upper six bits of the linear address included in the data processing command contain the address conversion information of the memory area of the second client and the endianness information. The tag memory 206 may store the upper six bits after the command reception unit 202 receives the data processing command. Since the time point when the command reception unit 202 receives the data processing command may be different from the time point when the access information conversion unit 208 or the data type conversion unit 210 operates, the temporary storage space is required in order to prevent malfunctions such as loss of the access interface information due to the time difference. By storing the access interface information in the tag memory 206, the execution of the previous data processing command without error by referring the access interface information stored in the tag memory 206, even though a new data processing command is received during the execution of the data processing command and is processed concurrently.

[63] The access information conversion unit 208 acquires the access interface information on the memory area of the second client from the data processing data received by the command reception unit 202, and converts the access information of the first client into the access information of the second client by using the acquired access interface information. For example, the access information conversion unit 208 may receive the data processing command from the first client, and acquire information on the address scheme and the endianness used in the memory area of the second client from the upper six bits of the linear address included in the data processing command. Using this information, the access information conversion unit 208 may convert the linear address of the data processing command into the physical address which is accessible to the second client memory area.

[64] The access information conversion unit 208 may include the access information division unit 208a or the access information merging unit 208b. As described above, the data processing command having a format such as (0x1236, read, 10) may be used. However, if one address is designated and a read or write operation for the address and the continuous area is required, the operation may not be supported in the real memory. This may occur when the number of times (or bit number) of the operations for the continuous area is too large, or the address exceed the address limit which can be designated at a time in the real memory. In this case, the access information division unit 208a serves to enable the data processing command to be properly executed within the memory by dividing the access information of the data processing command. For example, in the case of the command such as (0x89AB, read, 10), if the 5-byte based read operation of the memory is suitable for execution of the data command, the access information division unit 208a divides the data processing command in such a manner as (0x89AB, read, 5) and (0x89B0, read, 5).

[65] The access information divided by the access information division unit 208a is converted into access information of the second client by the access information conversion unit 208. In some cases, however, it may be preferable that the converted access information of the second client should be merged into the single information. For example, when the divided and converted access information is configured in such a manner as (0x1234, read, 2) and (0x126, read, 3), this access information may be merged into the access information such as (0x1234, read, 5). Therefore, in this case, the access information merging unit 208b merges the divided and converted access information into the single access information. However, the access information merging process may cause a side effect that lengthens the response time of the memory system. Thus, only when required, the access information merging unit 208b may perform the access information merging process.

[66] The data type conversion unit 210 appropriately converts the type of data, which is to be processed by the data processing command, by using the access interface information acquired from the data processing command. If the data processing command includes the read command, the data type conversion unit 210 converts the type of the data read by the command processing unit 212, e.g., data endianness, depending on the endianness used by the first client. This is because the data read from the memory area of the second client by the command processing unit 212 may have the endianness the second client uses. Likewise, if the data processing command includes the write command, the data to be written to the memory area of the second client by the data processing command may have the endianness the first client uses. In this case, before executing the write command, the data type conversion unit 210 may convert the endianness of the data to be written by the write command into the endianness the second client use.

[67] The command processing unit 212 accesses the memory area of the second client by using the access information of the second client, which is converted by the access information conversion unit 208, and executes the data processing command, i.e., the data read or data write command, in the accessed memory area. If the data processing command is the read command, the command processing unit 212 may transfer the read data to the first client.

[68] Fig. 3 illustrates a real memory configuration and real memory map for explaining a memory access interface transformation method in accordance with an embodiment of the present invention. The memory access interface transformation method in accordance with the embodiment of the present invention will be described in more detail with reference to Fig. 3. [69] Referring to Fig. 3, a memory 304 is connected to a plurality of clients. Areas 304a to 304e used by the respective clients are allocated in the memory 304. As illustrated in Fig. 3, A CPU code and data area 304a, a bit-stream data area 304b, a graphic data area 304c, a video data area 304d, and an auxiliary data area 304e are allocated in the memory 304.

[70] In this embodiment, it is assumed that the capacity of the memory 304 is 256 MB.

Also, it is assumed that 64 MB is allocated to the CPU code and data area 304a; 32 MB is allocated to the bit-stream data area 304b; 32 MB is allocated to the graphic data area 304c; 64 MB is allocated to the video data area 304d; and 64 MB is allocated to the auxiliary data area 304e. In order to access the memory 304, a 28-bit address may be used. The respective areas 304a to 304e may be represented by values 0 to 7 which are expressed by the upper three bits of the 28-bit address, i.e., [27:25]. That is, if the upper three-bit value of a certain linear address is 0 or 1, it represents the CPU code and data area 304a; if the upper three-bit value of the certain linear address is 2, it represents the bit-stream data area 304b; if the upper three-bit value of the certain linear address is 3, it represents the graphic data area 304c; if the upper three-bit value of the certain linear address is 4 or 5, it represents the video data area 304d; and if the upper three-bit value of the certain linear address is 6 or 7, it represents the auxiliary data area 304e. This setting may be generally designated at a system level in real time, and it should be noted that this setting is merely exemplary.

[71] In this embodiment, in addition to the 28-bit address, additional bits are used to represent the access interface information, that is, information regarding the address conversion scheme and the endianness used by the memory areas which are represented by the respective addresses. If three bits, i.e., [30:28], are additionally used, a plurality of different access interface information may be represented by values 0 to 7 which are expressed by the three bits. For example, 0 represents the use of a BA:RA:CA scheme and a big endian; 1 represents the use of a BA:RA:CA scheme and a little endian; 2 represents the use of an RA:BA:CA scheme and a big endian; 3 represents the use of an RA:BA:CA scheme and a little endian; 4 represents the use of a 2-D map specialized for graphic data; and 5 represents the use of a 2-D map specialized for video data.

[72] A memory map 302 of Fig. 3 shows the results obtained by using the allocation of the memory 304 and the setting of the access interface information. According to those setting, the size of the areas 302a to 302f corresponding to the respective access interface information is 256 MB, which is the same as that of the memory 304, and it is possible to obtain the memory map 302 including all the areas 304a to 304e of the memory 304 at the respective areas 302a to 302f. For example, as illustrated in Fig. 3, all the areas 304a to 304e of the memory 304 are included in the BA:RA:CA scheme and the big endian area 302a. This is also applied to the remaining areas 302b to 302f of the memory map 302 (for convenience's sake, only the area 302a is illustrated in Fig. 3).

[73] A memory access interface transformation method in accordance with an embodiment of the present invention will be described below, based on the above- described memory map 302 and setting of the access interface information.

[74] In this embodiment, the respective clients are set to use a different address conversion scheme and endianness. For example, it is assumed that a CPU uses a RA:BA:CA scheme and a big endian, a bit-stream engine uses an RA:BA:CA scheme and a little endian, and a video engine uses a 2-D Map #2. As described using the memory map 302 of Fig. 2, when the respective clients generate addresses for memory access, 2, 3 and 5 corresponding to the access interface information used by the respective clients are used in [30:28]. In addition, since the memory 304 is divided into the areas 304a to 304e of Fig. 3 and the upper three-bit values are designated to them, the respective clients may have the values 0 or 1, 2, 4 or 5 in [27:25]. Therefore, a certain client uses an address 010000 or 0100001 as [27:25] in order to access the CPU code and data area 304a in the memory 304, an address 011010 as [30:25] in order to access the bit-stream data area 304b, and an address 101100 or 101101 as [30:25] in order to access the video data area 304d.

[75] The following description will be made on the procedure of the CPU's reading the data stored by the bit-stream engine. In order to read the data stored by the bit-stream engine, the CPU sends the data processing command of (0x34001234, read, 30) to the memory. The command reception unit 202 of the memory access interface transformation apparatus 108 receives the data processing command.

[76] A binary expression of a linear address 0x34001234 included in the data processing command is 0011_0100_0000_0000_0001_0010_0011_0100. The access information conversion unit 208 may know the memory access interface which is used in the bit- stream engine area the CPU intends to access through the linear address. That is, since the [30:25] bits of the linear address are 011010, the access information conversion unit 208 may know that the memory area the CPU intends to access is the bit-stream data area (the lower three bits are 010) and this area uses the RA:BA:CA scheme and the little endian, by referring the memory access interface for each client or the memory map 302 included in the control register 204. Therefore, using this information, the access information conversion unit 208 may convert the linear address included in the data processing command of the CPU into the address which allows the access to the bit-stream data area.

[77] Before such an address conversion is executed by the access information conversion unit 208, the access information may be divided by the access information division unit 208a of the access information conversion unit 208. If it is appropriately designed to allow the memory 304 to process data on a 16-bit basis, the access information division unit 208a may divide the command of (0x34001234, read, 30) into three commands, that is, (0x34001234, read, 12), (0x34001240, read, 16), and (0x34001250, read, 2).

[78] The access information conversion unit 208 converts the access information of the

CPU, that is, the linear information, into the access information of the second client. For example, when the memory 304 is a 4-bank, 256-column, 16-bit SDRAM, a binary number of 0x34001234 is 0011_0100_0000_0000_0001_0010_0011_0100, and thus, it is converted into BA: 1, RA:2, and CA:0xlA. Likewise, the next address 0x34001240 is converted into BA: 1, RA:2 and CA:0x20. The address 0x34001250 is converted into BA: 1 RA:2 and CA:0x28. Consequently, the data processing command received by the command reception unit 202 is converted into (BA: 1 RA:2 CA:0xlA, read, 12), (BA: 1 RA:2 CA:0x20, read, 16), and (BA: 1 RA:2 CA:0x28, read, 2).

[79] The command processing unit 212 may execute the data read operation through the converted data processing commands. Those commands are to successively read 12 bytes, 16 bytes, and 2 bytes from the designated addresses, and may be independently processed. However, it can be seen from the respective addresses that the bank address and the column address are equal to each other, whereas only the column address is changed. Therefore, the access information merging unit 208b determines whether the addresses of the data processing commands having undergone the division and conversion process can be merged together and, if necessary, merges those addresses into the single data processing command. As described above, the above process is not necessarily required because the response speed of the system may be lowered.

[80] The command processing unit 212 accesses the bit-stream data area of the memory

304 by using the access information of the bit-stream data area included in the converted data processing command, i.e., the converted address. Then, the command processing unit 212 reads data according to the data processing command. The command processing unit 212 transfers the read data to the CPU. Since the data is the data stored in the bit-stream data area, its endianness may be different from the en- dianness used by the CPU. At this time, the data type conversion unit 210 converts the endianness of the data read by the command processing unit 212.

[81] When the data type conversion unit 210 converts the endianness of the data, the data type conversion unit 210 must obtain the information on the endianness used by the CPU and the bit-stream engine. This may be achieved by several methods. When the command reception unit 202 receives the data processing command, it can know that the data processing command is sent the CPU through the ID confirmation of the CPU. Therefore, the endianness of the CPU can be confirmed using the control register 204 having the endianness information of each client. Furthermore, the endianness of the bit-stream engine can be confirmed through the access interface information on the bit- stream data area obtained by the access information conversion unit 208. At this time, the access interface information may also be confirmed through the tag memory 206.

[82] The command processing unit 212 provides the CPU with the data whose endian is converted by the data type conversion unit 210. In this way, the execution of the data processing command from the CPU is completed. Consequently, the CPU may read the desired data from the memory 304, without regard to what conversion process is executed in the memory 304.

[83] After the CPU processes the data read from the memory 304, the CPU stores the

30-byte processed data in the 2-D Map #2 area. The procedure of storing the 30-byte processed data in the 2-D Map #2 area will be described below in detail.

[84] The command reception unit 202 receives the data processing command of

(0x58001234, read, 30) from the CPU. A binary expression of a linear address 0x58001234 included in the data processing command is

0101_1000_0000_0000_0001_0010_0011_0100. Using 101110 which are [3025] bits of the linear address, the access information conversion unit 208 may know that the memory area the CPU intends to access is the 2-D Map #2 area (the lower bits are 110) and the 2-D Map #2 area uses an address conversion scheme specialized for video device (the upper bits are 101). Therefore, using this information, the access information conversion unit 208 may convert the linear address included in the data processing command of the CPU into the address which allows the access to the 2-D Map #2 area.

[85] Before such an address conversion is executed by the access information conversion unit 208, the access information may be divided by the access information division unit 208a of the access information conversion unit 208. If it is appropriately designed to allow the memory 304 to process data on a 16-bit basis, the access information division unit 208a may divide the write command of (0x58001234, write, 30) into three commands, that is, (0x58001234, write, 12), (0x58001240, write, 16), and (0x58001250, write, 2). If a formula of converting the divided addresses to be suitable for the 2-D Map #2 access is "[3:1] => CA[2:0], y[4:0] => CA[7:3], x[4] => BA[O], y[5] => BA[I], x[9:5] => RA[4:0], y[9:6] => RA[8:5]", the address conversion may be as follows.

[86] Since 0x58001234 is 0101_1000_0000_0000_0001_0010_0011_0100, y[9:0] becomes 00_0000_0100, and x[9:0] becomes 10_0011_0100. Thus, BA[l:0] becomes 01, i.e., 1, and RA[8:0] becomes 0_0001_0001, i.e., 0x011. Also, CA[7:0] becomes 0010J)OlO, i.e., 0x22. Likewise, if 0x58001240 is converted, BA, RA, and CA become 0, 0x12, and 0x20, respectively. Also, if 0x58001250 is converted, BA, RA, and CA become 1, 0x12, and 0x20, respectively. Therefore, the data processing command received from the CPU is converted into (BA: 1 RA:0xl 1, CA:0x22, write, 12), (BA:0 RA:0xl2 CA:0x20, write, 16), and (BA: 1 RA:0xl2 CA:0x20, write, 2). (The reason why x[0] is not referred is that the address unit is byte, but the memory processes data on a 16-bit basis.)

[87] The command processing unit 212 may execute the data read operation through the converted data processing command. However, it can be seen that both the bank address and the column address among the converted three addresses are changed. In this case, it is impossible to merge the addresses, the access information merging unit 208b does not merge the divided and converted addresses.

[88] Since the data processing command of the CPU is the write command, the command reception unit 202 may receive data to be written to the 2-D Map #2 area together with the data processing command from the CPU. Since the data is received from the CPU, it has the endianness which is used by the CPU. Therefore, if the endianness of the corresponding data is different from the endianness of the 2-D Map #2 area, the endianness conversion may be performed by the data type conversion unit 210 before the data is written to the 2-D Map #2 area. Since the endianness conversion has been described above, its further description will be omitted.

[89] When the address conversion and the endianness conversion are completed, the command processing unit 212 accesses the 2-D Map #2 area by using the converted addresses, and write the corresponding data to the corresponding position. In this way, the execution of the data processing command from the CPU is completed.

[90] The procedures of executing the data read command and the data write command and the setting of the memory map 302, which are described above through the embodiments of the present invention, are merely exemplary. Furthermore, the procedure of executing the data processing command may cope with the variation of internal or external environments in real time through a method of changing the memory map 302 or memory access interface set in the control register 204.

[91] Fig. 4 is a flowchart illustrating a procedure of processing a data read command in accordance with an embodiment of the present invention.

[92] First, a data read command for a memory area of a second client is received from the first client (402). The data read command may include access information such as a linear address representing a start position of data the first client intends to read.

[93] Then, access interface information for the memory area of the second client is acquired from the received data read command (404). The access interface information for the memory area of the second client includes access information of the second client such as address conversion scheme used in the second client area, and data type information such as endianness of data stored in the second client area. [94] After acquiring the access interface information, the access information of the first client is converted into the access information of the second client by using the acquired access interface information (406). For example, the linear address included in the data read command received from the first client is converted into the address format which allows the access to the memory area of the second client by using the access interface information.

[95] Then, the access information of the second client is used to access the memory area of the second client (408). Data requested by the first client is read from the memory area of the accessed second client (410).

[96] Since the data read through the process 410 is stored in the memory area of the second client, it may have the data type used by the second client, e.g., the endianness of the second client. Therefore, the type of the read data is converted into the data type of the first client by using the access interface information acquired in the process 404 (412). The read data is transferred to the first client (414), and the execution of the data read command in accordance with the embodiment of the present invention is completed.

[97] Fig. 5 is a flowchart illustrating a procedure of processing a data write command in accordance with an embodiment of the present invention.

[98] First, a data write command for a memory area of a second client is received from the first client (502). The data write command may include access information such as a linear address representing a start position of data the first client intends to write. In addition, data to be written through the data write command may be received in the process 502.

[99] Then, access interface information for the memory area of the second client is acquired from the received data write command (504). The access interface information for the memory area of the second client includes access information of the second client such as address conversion scheme used in the second client area, and data type information such as endianness of data stored in the second client area.

[100] After acquiring the access interface information, the access information of the first client is converted into the access information of the second client by using the acquired access interface information (506). For example, the linear address included in the data write command received from the first client is converted into the address format which allows the access to the memory area of the second client by using the access interface information.

[101] Then, the access information of the second client is used to access the memory area of the second client (508). Since the data read through the process 502 is from the first client, it may have the data type used by the first client, e.g., the endianness of the first client. Therefore, the type of the data to be written to the memory area of the second client is converted into the data type of the second client by using the access interface information acquired in the process 504 (510). The data is written to the accessed memory area of the second client (512), and the execution of the data write command in accordance with the embodiment of the present invention is completed.

[102] Fig. 6 is a flowchart illustrating the process 406 of converting the access information of the first client into the access information of the second client in Fig. 4.

[103] First, the access information of the first client is divided into two or more access information suitable for the execution of the data read command (602). The divided two or more access information are converted into the access information of the second client by using the access interface information (604).

[104] In some cases, the divided and converted access information of the second client may be merged. Therefore, it is determined whether the converted access information of the second client can be merged or not (606). When it is determined that the converted access information of the second client can be merged, the converted access information of the second client is merged into the single access information of the second client (608).

[105] Although the process 406 has been described with reference to Fig. 6, it is apparent that the same process may be executed in the process 506.

[106] In accordance with the above-described embodiments, the respective clients constituting the single system may read or write their desired data through the memory, without regard to the address conversion scheme and endianness of other clients. Therefore, the respective clients may be designed to operate with the maximized performance.

[107] Furthermore, since the address conversion scheme of each client or the setting of the endianness is changed in real time according to the necessity of a system operator or a system itself, it is possible to flexibly cope with the system's external environment or internal state or the variation of each client.

[108] Moreover, by changing the address conversion scheme and endianness of other clients, various address conversion schemes and endianness of various clients may be simultaneously supported.

[109] The above-described methods can also be embodied as computer programs. Codes and code segments constituting the programs may be easily construed by computer programmers skilled in the art to which the invention pertains. Furthermore, the created programs may be stored in computer-readable recording media or data storage media and may be read out and executed by the computers. Examples of the computer- readable recording media include any computer-readable recoding media, e.g., intangible media such as carrier waves, as well as tangible media such as CD or DVD.

[110] While the present invention has been described with respect to the specific em- bodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

[1] A memory access interface transformation method, comprising: receiving a data processing command for a memory area of a second client from a first client; acquiring access interface information for the memory area of the second client from the data processing command; and converting access information of the first client into access information of the second client by using the access interface information.

[2] The memory access interface transformation method of claim 1, further comprising accessing the memory area of the second client by using the access information of the second client.

[3] The memory access interface transformation method of claim 2, further comprising reading data requested by the first client from the accessed memory area of the second client, wherein the data processing command is a data read command.

[4] The memory access interface transformation method of claim 3, further comprising converting a type of the read data into a data type of the first client by using the access interface information.

[5] The memory access interface transformation method of claim 3 or 4, further comprising transferring the read data to the first client.

[6] The memory access interface transformation method of claim 2, further comprising: converting a type of data which the first client wants to write at the memory area of the second client into a data type of the second client by using the access interface information; and writing the data to the accessed memory area of the second client.

[7] The memory access interface transformation method of claim 1, wherein the process of converting the access information of the first client into the access information of the second client comprises: dividing the access information of the first client into two or more access information corresponding to access information processing capacity of the memory; and converting the divided two or more access information into the access information of the second client by using the access interface information.

[8] The memory access interface transformation method of claim 1, wherein the process of converting the access information of the first client into the access information of the second client comprises: determining whether it is possible to merge the converted respective access information of the second client; and merging the converted respective access information of the second client into single access information of the second client when it is possible to merge the converted respective access information of the second client.

[9] A memory access interface transformation method, comprising: receiving a data read command for a memory area of a second client from a first client; acquiring access interface information for the memory area of the second client from the data read command; and converting access information of the first client into access information of the second client by using the access interface information.

[10] The memory access interface transformation method of claim 9, further comprising: accessing the memory area of the second client by using the access information of the second client; and reading data requested by the first client in the accessed memory area of the second client.

[11] A memory access interface transformation method, comprising: receiving a data write command for a memory area of a second client from a first client; acquiring access interface information for the memory area of the second client from the data write command; and converting access information of the first client into access information of the second client by using the access interface information.

[12] The memory access interface transformation method of claim 11, further comprising: accessing the memory area of the second client by using the access information of the second client; converting a type of data which the first client wants to write at the memory area of the second client into a data type of the second client by using the access interface information; and writing the data to the accessed memory area of the second client.

[13] A memory access interface transformation apparatus, comprising: a command reception unit configured to receive a data processing command for a memory area of a second client from a first client; and an access information conversion unit configured to acquire access interface information for the memory area of the second client from the data processing command, and convert access information of the first client into access information of the second client by using the access interface information.

[14] The memory access interface transformation apparatus of claim 13, further comprising a command processing unit configured to access the memory area of the second client by using the access information of the second client, and read data requested by the first client in the accessed memory area of the second client.

[15] The memory access interface transformation apparatus of claim 13, further comprising a command processing unit configured to convert a type of data which the first client wants to write at the memory area of the second client into a data type of the second client by using the access interface information, and write the data to the accessed memory area of the second client.