WO2010038786A1 - Memory element, method for manufacturing the memory element, and memory device comprising memory element - Google Patents

Memory element, method for manufacturing the memory element, and memory device comprising memory element Download PDF

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Publication number
WO2010038786A1
WO2010038786A1 PCT/JP2009/067047 JP2009067047W WO2010038786A1 WO 2010038786 A1 WO2010038786 A1 WO 2010038786A1 JP 2009067047 W JP2009067047 W JP 2009067047W WO 2010038786 A1 WO2010038786 A1 WO 2010038786A1
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Prior art keywords
resistor
memory element
compound
electrode
memory
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PCT/JP2009/067047
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French (fr)
Japanese (ja)
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直 池田
芳博 久保園
高志 神戸
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国立大学法人岡山大学
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Priority to JP2010531886A priority Critical patent/JP5467241B2/en
Publication of WO2010038786A1 publication Critical patent/WO2010038786A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

Definitions

  • the present invention relates to a memory element, a manufacturing method thereof, and a storage device including the memory element.
  • DRAM Dynamic Random Access Memory
  • This DRAM is composed of a capacitor and a transistor formed on a semiconductor substrate, and stores data of one bit of “0” or “1” by controlling the amount of charge accumulated in the capacitor by the transistor. .
  • MRAM Magnetic Random Access Memory
  • a ferromagnetic tunnel junction element is formed by laminating a free magnetic layer that can be magnetized in a free direction and a fixed magnetic layer that is magnetized in a fixed direction.
  • One bit of data “0” or “1” is stored.
  • the magnitude of the electric resistance is different depending on whether the magnetization direction of the free magnetic layer and the magnetization direction of the fixed magnetic layer are parallel or antiparallel. Are different from each other, and data of 1 bit is stored using the state of the different electric resistance (see, for example, Patent Document 1).
  • the inventors of the present invention have studied the compound having a layered triangular lattice structure containing a rare earth element, and have come to realize that a memory element with low power consumption can be provided by utilizing the dielectric properties of the compound. It is made.
  • the memory element of the present invention is a memory element having a resistor whose electrical resistance changes when a voltage is applied and a voltage application electrode for applying a predetermined voltage to the resistor.
  • the body was composed of a compound having a layered triangular lattice structure containing rare earth elements.
  • the memory element of the present invention is also characterized by the following points. That is, (1) In the compound, R is at least one element selected from In, Sc, Y, Dy, Ho, Er, Tm, Yb, Lu, Ti, Ca, Sr, Ce, Sn, and Hf, Ma, and Mb is at least one element selected from Ti, Mn, Fe, Co, Cu, Ga, Zn, Al, Mg, and Cd, n is an integer of 1 or more, m is an integer of 0 or more, ⁇ Is a compound represented by (RMbO 3- ⁇ ) n (MaO) m , where R is a real number of 0 or more and 0.2 or less, or a compound in which a part of R of the compound is substituted with an element less than or equal to positive divalent.
  • the voltage application electrodes are provided as a pair so as to face each other across the resistor, and the voltage application electrode is also used as a voltage detection electrode for detecting the electrical resistance of the resistor. Being.
  • the voltage application electrodes are provided separated in the c-axis direction of the compound constituting the resistor.
  • a memory element having a resistor whose electrical resistance is changed by applying a voltage and an electrode for applying a voltage for applying a predetermined voltage to the resistor is manufactured.
  • the method includes the step of forming the resistor with a compound having a layered triangular lattice structure containing a rare earth element.
  • the memory device of the present invention includes a plurality of memory elements each including a resistor whose electrical resistance changes when a voltage is applied and a voltage application electrode for applying a predetermined voltage to the resistor.
  • the resistor is composed of a compound having a layered triangular lattice structure containing a rare earth element.
  • a memory element that stores predetermined data using different resistance values of a resistor, a manufacturing method thereof, and a memory device including the memory element, the layered triangular lattice containing the rare earth element as the resistor
  • data can be stored by changing the electrical resistance by applying a predetermined voltage to the resistor.
  • the memory element formed using this resistor can reduce power consumption by eliminating the need for a refresh process, and can further reduce the power consumption due to miniaturization of the resistor. Can also be reduced.
  • FIG. 1 is a schematic explanatory diagram of the arrangement of each element in a plan view of a compound having a layered triangular lattice structure.
  • FIG. 2 is a schematic explanatory diagram of the arrangement of each element in a side view of a compound having a layered triangular lattice structure.
  • FIG. 3 is a schematic diagram of a memory element according to the embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a memory device according to another embodiment.
  • FIG. 5 is a schematic diagram of a memory device according to another embodiment.
  • FIG. 6 is a schematic diagram of a memory element according to another embodiment.
  • FIG. 7 is a schematic diagram of a memory device according to another embodiment.
  • FIG. 8 is a schematic diagram of a memory device according to another embodiment.
  • FIG. 9 is a schematic diagram of a storage device according to an embodiment of the present invention.
  • the memory element of the present invention the manufacturing method thereof, and the memory device including the memory element, the memory element is configured by using a resistor whose electric resistance is changed by applying a voltage.
  • the resistor is composed of a compound having a layered triangular lattice structure containing a rare earth element.
  • R is at least one element selected from In, Sc, Y, Dy, Ho, Er, Tm, Yb, Lu, Ti, Ca, Sr, Ce, Sn, and Hf, Ma and Mb. , Ti, Mn, Fe, Co, Cu, Ga, Zn, Al, Mg, Cd, at least one element selected with duplication allowed, n is an integer of 1 or more, m is an integer of 0 or more, and ⁇ is 0 A compound represented by (RMbO 3 - ⁇ ) n (MaO) m as a real number of 0.2 or more or a compound in which a part of R of the compound is substituted with an element of less than or equal to bivalence.
  • LuFe 2 O 4 in which R is Lu and Ma and Mb are Fe as representative examples.
  • LuFe 2 O 4 can be produced by the following procedure. (1) Lutetium oxide (Lu 2 O 3 ) and iron (III) oxide (Fe 2 O 3 ) are mixed at a ratio of 1: 2 and mixed with a ball mill for about 1 hour to form a mixture. (2) The mixture is formed into a predetermined shape and heated to 800 ° C. for 24 hours in an oxygen atmosphere to form a pre-fired body. (3) The temporary fired body is fired by the FZ (Floating Zone) method to obtain single crystal LuFe 2 O 4 . At this time, the crystal is grown in an atmosphere of a CO—CO 2 mixed gas that is a mixed gas of carbon monoxide and carbon dioxide.
  • a CO—CO 2 mixed gas that is a mixed gas of carbon monoxide and carbon dioxide.
  • a CO 2 —H 2 mixed gas may be used instead of the CO—CO 2 mixed gas, and the amount of oxygen is obtained by firing while controlling the oxygen partial pressure in a reducing atmosphere. Is adjusted.
  • the crystal structure of single crystal LuFe 2 O 4 will be described with reference to FIGS.
  • the crystal structure of LuFe 2 O 4 is in a state before so-called charge ordering, in which the ordered structure of Fe 3+ and Fe 2+ does not appear in Fe ions in the crystal.
  • FIG. 1 is a schematic explanatory diagram of the arrangement of each element in a plan view, and shows the positional relationship of a triangular lattice of element A, a triangular lattice of element B, and a triangular lattice of element C.
  • the position of the lattice point in the triangular lattice of element A is “A position”
  • the position of the lattice point in the triangular lattice of element B is “B position”
  • the position of the lattice point in the triangular lattice of element C is “C position”. I will call it.
  • FIG. 2 is a schematic explanatory diagram of the arrangement of each element in a side view, and each element is located at a predetermined position in the following order from the uppermost layer downward.
  • W-Layer a portion composed of four layers marked with a circle is called a W layer (W-Layer), and having this W layer is a characteristic point of LuFe 2 O 4 .
  • a W layer is also formed in a compound having a layered triangular lattice structure other than LuFe 2 O 4 .
  • the W layer has a triangular lattice laminated structure, and the presence of the same number of Fe 2+ and Fe 3+ in LuFe 2 O 4 causes frustration of charges.
  • the region rich in Fe 3+ has a role of positive charge in the W layer, while the region rich in Fe 2+ has a role of negative charge. (Electrical polarization) appears.
  • LuFe 2 O 4 the state of the electric dipole can be controlled by applying an electric field from the outside, and LuFe 2 O 4 has different electric resistances depending on the state of the electric dipole.
  • a compound having a layered triangular lattice structure containing a rare earth element has a W layer and can control the charge order structure in the W layer by an electric field applied from the outside to generate different states of electrical resistance. Therefore, a memory element can be configured.
  • the memory element of the present invention is formed by sequentially laminating a first electrode 21, a resistor 30, and a second electrode 22 on a predetermined insulating substrate 10 from below.
  • the electric resistance of the resistor 30 can be changed by applying an electric field to the resistor 30 with the first electrode 21 and the second electrode 22 set to a predetermined potential.
  • a voltage application device (not shown) is connected to the first electrode 21 and the second electrode 22 so that a predetermined electric field acts on the resistor 30 between the first electrode 21 and the second electrode 22.
  • the first electrode 21 acts on the resistor 30 depending on whether the first electrode 21 has a higher potential than the second electrode 22 or the second electrode 22 has a higher potential than the first electrode 21.
  • the direction of the electric field to be adjusted is adjusted so that the resistor 30 can be changed to two states having different electric resistances.
  • the first electrode 21 and the second electrode 22 are made of a highly conductive metal such as Au or Cu.
  • the resistor 20 is LuFe 2 O 4 in this embodiment.
  • the resistor 20 is not limited to LuFe 2 O 4 , and R is selected from In, Sc, Y, Dy, Ho, Er, Tm, Yb, Lu, Ti, Ca, Sr, Ce, Sn, and Hf.
  • n is one or more A compound having a layered triangular lattice structure represented by (RMbO 3 - ⁇ ) n (MaO) m , where R is an integer, m is an integer of 0 or more, ⁇ is a real number of 0 to 0.2, or a part of R of the compound A compound in which is substituted with an element having a positive divalent value or less can be used.
  • the resistor 20 will be described as LuFe 2 O 4 .
  • the memory element described above can be formed as follows.
  • a first metal layer is formed on the insulating substrate 10 by sputtering or the like.
  • fine particles of LuFe 2 O 4 are formed on the first metal layer by CVD (Chemical Vapor Deposition), sputtering, MBE (Molecular Beam Epitaxy), or aerosol deposition.
  • CVD Chemical Vapor Deposition
  • sputtering sputtering
  • MBE Molecular Beam Epitaxy
  • aerosol deposition a resistor layer is formed.
  • a second metal layer is formed on the resistor layer by sputtering or the like.
  • etching mask is formed on the upper surface of the second metal layer, and the second metal layer, the resistor layer, and the first metal layer are sequentially etched by etching or electron beam lithography to thereby form the first electrode. 21, a resistor 30 and a second electrode 22 are formed.
  • the resistor layer is preferably a single crystal of LuFe 2 O 4 , but may be polycrystalline.
  • the c-axis direction of LuFe 2 O 4 is made to coincide with the opposing direction of the first electrode 21 and the second electrode 22.
  • the c-axis direction of LuFe 2 O 4 is not necessarily completely coincident with the opposing direction of the first electrode 21 and the second electrode 22, and at least the c-axis direction of LuFe 2 O 4 is the first electrode. It does not have to be orthogonal to the facing direction of 21 and the second electrode 22.
  • the electric resistance of the resistor can be easily switched, so that a memory element with low power consumption can be obtained.
  • first electrode 21 and second electrode 22 for applying a predetermined voltage to the resistor, spaced apart in the c-axis direction of the compound, the first electrode 21 and the second electrode 22
  • the electric resistance of the resistor 30 can be effectively changed by the formed electric field, and the power consumption can be further reduced.
  • the first electrode 21, the second electrode 22, and the resistor 30 have the same width.
  • the width may be smaller than that of the electrode 21 and the resistor 30.
  • the second electrode 22 ′ may have a width dimension smaller than that of the resistor 30 ′, and the resistor 30 ′ may have a width dimension smaller than that of the first electrode 21.
  • the width dimension of the first electrode 21 "and the second electrode 22" may be smaller than the width dimension of the resistor 30 ".
  • first electrode 21 and the second electrode 22 are not only formed apart in the vertical direction, but, for example, as shown in FIG. 7, the first electrode 21 is separated by a predetermined dimension in the surface direction of the insulating substrate 40.
  • 51 and a second electrode 52 may be provided, and a resistor 60 made of a compound having a layered triangular lattice structure containing a rare earth element may be provided between the first electrode 51 and the second electrode 52.
  • a resistor layer is formed in advance on the insulating substrate 40 by using a fine particle form of LuFe 2 O 4 by a CVD method, a sputtering method, an MBE method, an aerosol deposition method, or the like.
  • the resistor 60 is formed into a predetermined cell shape by electron beam lithography or the like.
  • a metal layer is formed on the insulating substrate 40 by sputtering or the like to cover the resistor 60, and a first mask for etching for forming the first electrode 51 and the second electrode 52 is formed.
  • a metal layer is formed on the insulating substrate 40 by sputtering or the like to cover the resistor 60, and a first mask for etching for forming the first electrode 51 and the second electrode 52 is formed.
  • the first electrode 51, the resistor 60, and the second electrode 52 are arranged in the surface direction of the insulating substrate 40.
  • the first electrode 51 and the second electrode 52 may be formed before the resistor 60.
  • the c-axis direction of the compound constituting the resistor 60 Is the surface direction of the insulating substrate 40.
  • the c-axis direction of the compound constituting the resistor 60 can be the plane direction of the insulating substrate 10.
  • ScAlMgO 4 is used for the insulating substrate 40.
  • the direction of the electric field applied to the resistors 30 and 60 by the first electrodes 21 and 51 and the second electrodes 22 and 52 is either the vertical direction of the insulating substrate 10 or the surface direction of the insulating substrate 40.
  • the second electrode 82 is provided obliquely above the first electrode 81 provided on the upper surface of the insulating substrate 70 with the resistor 90 interposed therebetween. Also good.
  • a storage device can be configured using the memory element described above.
  • the number of memory elements m corresponding to the storage capacity is arranged in a matrix.
  • the first wiring 101 is connected to the first electrode of the memory element m, and the second wiring 102 is connected to the second electrode of the memory element m via the control transistor t.
  • the memory elements m arranged in the vertical direction in FIG. 9 share one first wiring 101, and the memory elements m arranged in the horizontal direction in FIG.
  • the second wiring 102 is shared.
  • the first wiring 101 is connected to the first driver circuit 103, the second wiring 102 is the second driver circuit 104, and the first wiring 101 and the second wiring 102 are connected by the first driver circuit 103 and the second driver circuit 104.
  • a predetermined electric field is applied to the memory element m.
  • the first driver circuit 103 and the second driver circuit 104 are controlled by control signals input from a main control unit (not shown).
  • a control signal line 105 is connected to each gate of the control transistor t.
  • the control signal line 105 is connected to the third driver circuit 106 and output from the third driver circuit 106 to the control signal line 105.
  • the control transistor t performs on / off switching control of the control transistor t.
  • control transistors t arranged in the horizontal direction share one control signal line 105.
  • the third driver circuit 106 is also controlled by a control signal input from a main control unit (not shown).
  • the first wiring 101 connected to the memory element m storing the predetermined data in the first driver circuit 103 is set to the first potential
  • the second driver The second wiring 102 connected to the memory element m that stores predetermined data in the circuit 104 is set to the second potential
  • the third transistor circuit 106 turns on the control transistor t connected to the memory element m that stores predetermined data. A signal is being input.
  • a predetermined electric field can be applied to the resistor of the memory element m by the first electrode having the first potential and the second electrode having the second potential, and the electric resistance of the resistor can be set to a predetermined value.
  • the electrical resistance is.
  • control transistors t arranged in the horizontal direction in FIG. 9 share one control signal line 105, not only the control transistor t connected to the memory element m that stores predetermined data, All the control transistors t arranged in the horizontal direction are in the on state.
  • the first driver circuit 103 and the second driver circuit 104 cause the first electrode and the second electrode of each memory element m to have the same potential in the memory elements m other than the memory element m that stores predetermined data. This prevents meaningless data from being written in the memory element m.
  • the value of the current for reading is detected by the first driver circuit 103 or the second driver circuit 104, and the resistance value of the memory element m is detected by comparing this current value with a predetermined threshold value. Reading data.
  • the first electrode and the second electrode are shared, and the first electrode and the second electrode are used for detecting the electrical resistance of the resistor.
  • the structure of the memory element m can be prevented from becoming complicated, and the memory element m can be formed very easily.
  • a low power consumption memory device can be provided.

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Abstract

Disclosed is a memory element having low-power consumption.  Also disclosed are a method for manufacturing the memory element and a memory device comprising the memory element. The memory element comprises a resistor that causes a change in electric resistance upon the application of voltage and a voltage applying electrode for applying a predetermined voltage to the resistor.  The memory device comprises the memory element.  The resistor is formed of a compound having a layered triangle lattice structure containing a rare earth element.  In particular, the resistor is formed of a compound having a layered triangle lattice structure represented by (RMbO3-δ)n(MaO)m wherein R represents at least one element selected from In, Sc, Y, Dy, Ho, Er, Tm, Yb, Lu, Ti, Ca, Sr, Ce, Sn, and Hf; Ma and Mb, which may be same or different, represent at least one element selected from Ti, Mn, Fe, Co, Cu, Ga, Zn, Al, Mg, and Cd; n is an integer of 1 or more; m is an integer of 0 or more; and δ is a real number of 0 to 0.2.  Alternatively, the resistor may be formed of a compound that is the same compound as described above except that a part of R in the compound has been replaced with a positive divalent or lower element.

Description

メモリ素子及びその製造方法、並びにメモリ素子を備えた記憶装置MEMORY ELEMENT, MANUFACTURING METHOD THEREOF, AND STORAGE DEVICE PROVIDED WITH MEMORY ELEMENT
　本発明は、メモリ素子及びその製造方法、並びにメモリ素子を備えた記憶装置に関する。 The present invention relates to a memory element, a manufacturing method thereof, and a storage device including the memory element.
　従来、電子計算機では、いわゆるＤＲＡＭ(Dynamic Random Access Memory)と呼ばれている記憶装置が一般的に用いられている。 Conventionally, a storage device called a DRAM (Dynamic Random Access Memory) is generally used in an electronic computer.
　このＤＲＡＭは、半導体基板に形成したコンデンサとトランジスタで構成しており、トランジスタによってコンデンサに蓄積する電荷量を制御することにより、「０」または「１」の１ビット分のデータを記憶している。 This DRAM is composed of a capacitor and a transistor formed on a semiconductor substrate, and stores data of one bit of “0” or “1” by controlling the amount of charge accumulated in the capacitor by the transistor. .
　ＤＲＡＭでは、コンデンサに蓄積した電荷が経時的に減少するために、一定時間ごとにコンデンサに対して再充電を行って、記憶しているデータを保持するリフレッシュ処理が必要となっている。 In the DRAM, since the charge accumulated in the capacitor decreases with time, a refresh process is necessary in which the capacitor is recharged at regular intervals and the stored data is retained.
　また、最近では、ＤＲＡＭのようにリフレッシュ処理を行うことなくデータを長期間記憶可能とした、いわゆるＭＲＡＭ(Magnetroresistive Random Access Memory)も用いられるようになっている。 Recently, a so-called MRAM (Magnetroresistive Random Access Memory) that can store data for a long period of time without performing a refresh process like a DRAM has been used.
　ＭＲＡＭでは、自由な方向に磁化可能とした自由磁化層と、一定の方向に磁化された固定磁化層とを積層させて、強磁性トンネル接合素子を形成しており、この強磁性トンネル接合素子で「０」または「１」の１ビット分のデータを記憶している。 In an MRAM, a ferromagnetic tunnel junction element is formed by laminating a free magnetic layer that can be magnetized in a free direction and a fixed magnetic layer that is magnetized in a fixed direction. One bit of data “0” or “1” is stored.
　すなわち、強磁性トンネル接合素子では、自由磁化層の磁化の方向と固定磁化層の磁化の方向とが平行状態となっている場合と、反平行状態となっている場合とで電気抵抗の大きさが異なっており、この異なる電気抵抗の状態を利用して１ビット分のデータを記憶している（例えば、特許文献１参照。）。 That is, in the ferromagnetic tunnel junction device, the magnitude of the electric resistance is different depending on whether the magnetization direction of the free magnetic layer and the magnetization direction of the fixed magnetic layer are parallel or antiparallel. Are different from each other, and data of 1 bit is stored using the state of the different electric resistance (see, for example, Patent Document 1).
　したがって、ＭＲＡＭでは、自由磁化層を所定の方向に向けて磁化することによりデータを書き込むことができる。
特開平１１－０９７７６６号公報 Therefore, in the MRAM, data can be written by magnetizing the free magnetic layer in a predetermined direction.
Japanese Patent Laid-Open No. 11-097766
　しかしながら、ＭＲＡＭでは、自由磁化層を所定の方向に向けて磁化するために、アンペールの法則に基づいて所定の電流を流しており、しかも、自由磁化層に所定の閾値以上の磁場を作用させる必要があるため、比較的大きな電流を流す必要があって、消費電力が大きいという問題があった。 However, in the MRAM, in order to magnetize the free magnetic layer in a predetermined direction, a predetermined current is passed based on Ampere's law, and a magnetic field of a predetermined threshold value or more must be applied to the free magnetic layer. Therefore, there is a problem that a relatively large current needs to flow and power consumption is large.
　また、ＤＲＡＭの場合でも、リフレッシュ処理にともなって電力が消費されるため、消費電力をより小さくすることが困難となっていた。 Further, even in the case of DRAM, since power is consumed with the refresh process, it has been difficult to reduce power consumption.
　本発明者らは、希土類元素を含有した層状三角格子構造を有する化合物の研究を行う中で、この化合物の誘電特性を利用することにより消費電力の小さいメモリ素子を提供できることに思い至り、本発明を成したものである。 The inventors of the present invention have studied the compound having a layered triangular lattice structure containing a rare earth element, and have come to realize that a memory element with low power consumption can be provided by utilizing the dielectric properties of the compound. It is made.
　本発明のメモリ素子では、電圧を印加することにより電気抵抗が変化する抵抗体と、この抵抗体に所定の電圧を印加するための電圧印加用の電極とを有するメモリ素子であって、前記抵抗体を希土類元素を含有した層状三角格子構造を有する化合物で構成することとした。 The memory element of the present invention is a memory element having a resistor whose electrical resistance changes when a voltage is applied and a voltage application electrode for applying a predetermined voltage to the resistor. The body was composed of a compound having a layered triangular lattice structure containing rare earth elements.
　さらに、本発明のメモリ素子では以下の点にも特徴を有するものである。すなわち、
（１）前記化合物が、Ｒを、In,Sc,Y,Dy,Ho,Er,Tm,Yb,Lu,Ti,Ca,Sr,Ce,Sn,Hfから選ばれる少なくとも１種類の元素、Ma及びMbを、Ti,Mn,Fe,Co,Cu,Ga,Zn,Al,Mg,Cdから重複を許して選ばれる少なくとも１種類の元素、ｎを１以上の整数、ｍを０以上の整数、δを０以上0.2以下の実数として、(RMbO3-δ)n(MaO)mとして表される化合物、またはその化合物のＲの一部を正二価以下の元素により置換した化合物であること。
（２）電圧印加用の電極は２つ１組として抵抗体を挟んで対向させて設けるとともに、電圧印加用の電極を抵抗体の電気抵抗を検出するための電圧検出用の電極と兼用していること。
（３）電圧印加用の電極は抵抗体を構成している化合物のｃ軸方向に離隔させて設けたこと。 Furthermore, the memory element of the present invention is also characterized by the following points. That is,
(1) In the compound, R is at least one element selected from In, Sc, Y, Dy, Ho, Er, Tm, Yb, Lu, Ti, Ca, Sr, Ce, Sn, and Hf, Ma, and Mb is at least one element selected from Ti, Mn, Fe, Co, Cu, Ga, Zn, Al, Mg, and Cd, n is an integer of 1 or more, m is an integer of 0 or more, δ Is a compound represented by (RMbO 3-δ ) n (MaO) m , where R is a real number of 0 or more and 0.2 or less, or a compound in which a part of R of the compound is substituted with an element less than or equal to positive divalent.
(2) The voltage application electrodes are provided as a pair so as to face each other across the resistor, and the voltage application electrode is also used as a voltage detection electrode for detecting the electrical resistance of the resistor. Being.
(3) The voltage application electrodes are provided separated in the c-axis direction of the compound constituting the resistor.
　また、本発明のメモリ素子の製造方法では、電圧を印加することにより電気抵抗が変化する抵抗体と、抵抗体に所定の電圧を印加するための電圧印加用の電極とを有するメモリ素子の製造方法であって、前記抵抗体を希土類元素を含有した層状三角格子構造を有する化合物で形成する工程を有することとした。 Further, in the method for manufacturing a memory element according to the present invention, a memory element having a resistor whose electrical resistance is changed by applying a voltage and an electrode for applying a voltage for applying a predetermined voltage to the resistor is manufactured. The method includes the step of forming the resistor with a compound having a layered triangular lattice structure containing a rare earth element.
　また、本発明の記憶装置では、電圧を印加することにより電気抵抗が変化する抵抗体と、抵抗体に所定の電圧を印加するための電圧印加用の電極とをそれぞれ有する複数のメモリ素子を備えた記憶装置であって、前記抵抗体を希土類元素を含有した層状三角格子構造を有する化合物で構成することとした。 In addition, the memory device of the present invention includes a plurality of memory elements each including a resistor whose electrical resistance changes when a voltage is applied and a voltage application electrode for applying a predetermined voltage to the resistor. In the memory device, the resistor is composed of a compound having a layered triangular lattice structure containing a rare earth element.
　本発明によれば、抵抗体の異なる抵抗値を利用して所定のデータを記憶するメモリ素子及びその製造方法、並びにメモリ素子を備えた記憶装置において、抵抗体を希土類元素を含有した層状三角格子構造を有する化合物で構成することにより、抵抗体に所定の電圧を印加することにより電気抵抗を変化させて、データを記憶させることができる。 According to the present invention, a memory element that stores predetermined data using different resistance values of a resistor, a manufacturing method thereof, and a memory device including the memory element, the layered triangular lattice containing the rare earth element as the resistor By comprising a compound having a structure, data can be stored by changing the electrical resistance by applying a predetermined voltage to the resistor.
　しかも、この抵抗体を用いて形成したメモリ素子では、リフレッシュ処理が不要となることにより消費電力の低減を図ることができ、さらに、抵抗体が微細化することができることによって、小型化による消費電力の低減を図ることもできる。 In addition, the memory element formed using this resistor can reduce power consumption by eliminating the need for a refresh process, and can further reduce the power consumption due to miniaturization of the resistor. Can also be reduced.
図１は層状三角格子構造を有する化合物の平面視における各元素の配置の概略説明図である。FIG. 1 is a schematic explanatory diagram of the arrangement of each element in a plan view of a compound having a layered triangular lattice structure. 図２は層状三角格子構造を有する化合物の側面視における各元素の配置の概略説明図である。FIG. 2 is a schematic explanatory diagram of the arrangement of each element in a side view of a compound having a layered triangular lattice structure. 図３は本発明の実施形態にかかるメモリ素子の概略模式図である。FIG. 3 is a schematic diagram of a memory element according to the embodiment of the present invention. 図４は他の実施形態のメモリ素子の概略模式図である。FIG. 4 is a schematic diagram of a memory device according to another embodiment. 図５は他の実施形態のメモリ素子の概略模式図である。FIG. 5 is a schematic diagram of a memory device according to another embodiment. 図６は他の実施形態のメモリ素子の概略模式図である。FIG. 6 is a schematic diagram of a memory element according to another embodiment. 図７は他の実施形態のメモリ素子の概略模式図である。FIG. 7 is a schematic diagram of a memory device according to another embodiment. 図８は他の実施形態のメモリ素子の概略模式図である。FIG. 8 is a schematic diagram of a memory device according to another embodiment. 図９は本発明の実施形態にかかる記憶装置の概略模式図である。FIG. 9 is a schematic diagram of a storage device according to an embodiment of the present invention.
　10,40,70　絶縁基板
　21,21",51,81　第１電極
　22,22',22",52,82　第２電極
　30,30',30",60,90　抵抗体 10,40,70 Insulating substrate 21,21 ", 51,81 First electrode 22,22 ', 22", 52,82 Second electrode 30,30', 30 ", 60,90 Resistor
　本発明のメモリ素子及びその製造方法、並びにメモリ素子を備えた記憶装置では、電圧を印加することにより電気抵抗が変化する抵抗体を用いてメモリ素子を構成しているものである。 In the memory element of the present invention, the manufacturing method thereof, and the memory device including the memory element, the memory element is configured by using a resistor whose electric resistance is changed by applying a voltage.
　特に、抵抗体は、希土類元素を含有した層状三角格子構造を有する化合物で構成したものである。 In particular, the resistor is composed of a compound having a layered triangular lattice structure containing a rare earth element.
　具体的には、Ｒを、In,Sc,Y,Dy,Ho,Er,Tm,Yb,Lu,Ti,Ca,Sr,Ce,Sn,Hfから選ばれる少なくとも１種類の元素、Ma及びMbを、Ti,Mn,Fe,Co,Cu,Ga,Zn,Al,Mg,Cdから重複を許して選ばれる少なくとも１種類の元素、ｎを１以上の整数、ｍを０以上の整数、δを０以上0.2以下の実数として、(RMbO3-δ)n(MaO)mとして表される化合物、またはその化合物のＲの一部を正二価以下の元素により置換した化合物である。 Specifically, R is at least one element selected from In, Sc, Y, Dy, Ho, Er, Tm, Yb, Lu, Ti, Ca, Sr, Ce, Sn, and Hf, Ma and Mb. , Ti, Mn, Fe, Co, Cu, Ga, Zn, Al, Mg, Cd, at least one element selected with duplication allowed, n is an integer of 1 or more, m is an integer of 0 or more, and δ is 0 A compound represented by (RMbO 3 -δ ) n (MaO) m as a real number of 0.2 or more or a compound in which a part of R of the compound is substituted with an element of less than or equal to bivalence.
　以下において、ＲをLuとし、Ma及びMbをFeとしたLuFe2O4を代表例として、層状三角格子構造を有する化合物を説明する。 Hereinafter, a compound having a layered triangular lattice structure will be described with LuFe 2 O 4 in which R is Lu and Ma and Mb are Fe as representative examples.
　LuFe2O4は、以下の手順により生成できる。
（１）酸化ルテチウム(Lu2O3)と酸化鉄(III)(Fe2O3)とを１：２の割合で混合するとともに、ボールミルで約１時間混合し、混合物を生成する。
（２）前記混合物を所定形状に成形して、酸素雰囲気下で、24時間、800℃に加熱して仮焼成体を生成する。
（３）ＦＺ(Floating Zone)法によって前記仮焼成体を本焼成することにより、単結晶のLuFe2O4とする。このとき、一酸化炭素と二酸化炭素の混合ガスであるCO－CO2混合ガスの雰囲気下で結晶成長させている。 LuFe 2 O 4 can be produced by the following procedure.
(1) Lutetium oxide (Lu 2 O 3 ) and iron (III) oxide (Fe 2 O 3 ) are mixed at a ratio of 1: 2 and mixed with a ball mill for about 1 hour to form a mixture.
(2) The mixture is formed into a predetermined shape and heated to 800 ° C. for 24 hours in an oxygen atmosphere to form a pre-fired body.
(3) The temporary fired body is fired by the FZ (Floating Zone) method to obtain single crystal LuFe 2 O 4 . At this time, the crystal is grown in an atmosphere of a CO—CO 2 mixed gas that is a mixed gas of carbon monoxide and carbon dioxide.
　なお、単結晶を生成する本焼成では、CO－CO2混合ガスの代わりにCO2－H2混合ガスを用いてもよく、還元雰囲気で酸素分圧を制御しながら焼成することにより酸素の量を調整している。 In the main firing for producing a single crystal, a CO 2 —H 2 mixed gas may be used instead of the CO—CO 2 mixed gas, and the amount of oxygen is obtained by firing while controlling the oxygen partial pressure in a reducing atmosphere. Is adjusted.
　単結晶のLuFe2O4の結晶構造について、図１及び図２を用いて説明する。なお、説明の便宜上、LuFe2O4の結晶構造は、結晶中のFeイオンにおいてFe3+とFe2+の規則構造が出現していない、いわゆる電荷秩序化前の状態としている。 The crystal structure of single crystal LuFe 2 O 4 will be described with reference to FIGS. For convenience of explanation, the crystal structure of LuFe 2 O 4 is in a state before so-called charge ordering, in which the ordered structure of Fe 3+ and Fe 2+ does not appear in Fe ions in the crystal.
　図１は、平面視における各元素の配置の概略説明図であり、元素Ａの三角格子と、元素Ｂの三角格子と、元素Ｃの三角格子の位置関係を示している。以下において、元素Ａの三角格子における格子点の位置を「Ａ位置」、元素Ｂの三角格子における格子点の位置を「Ｂ位置」、元素Ｃの三角格子における格子点の位置を「Ｃ位置」と呼ぶこととする。 FIG. 1 is a schematic explanatory diagram of the arrangement of each element in a plan view, and shows the positional relationship of a triangular lattice of element A, a triangular lattice of element B, and a triangular lattice of element C. In the following, the position of the lattice point in the triangular lattice of element A is “A position”, the position of the lattice point in the triangular lattice of element B is “B position”, and the position of the lattice point in the triangular lattice of element C is “C position”. I will call it.
　図２は、側面視における各元素の配置の概略説明図であり、最上層から下方に向けて以下の順番で所定の位置に各元素が位置している。
　　Lu－Ｂ位置
　　O －Ｃ位置
　　Fe－Ｃ位置
　　O －Ｂ位置
　　O －Ｃ位置
　　Fe－Ｂ位置
　　O －Ｂ位置
　　Lu－Ｃ位置
　　O －Ａ位置
　　Fe－Ａ位置○
　　O －Ｃ位置○
　　O －Ａ位置○
　　Fe－Ｃ位置○
　　O －Ｃ位置
　　Lu－Ａ位置
　　O －Ｂ位置
　　Fe－Ｂ位置
　　O －Ａ位置
　　O －Ｂ位置
　　Fe－Ａ位置
　　O －Ａ位置
　　Lu－Ｂ位置 FIG. 2 is a schematic explanatory diagram of the arrangement of each element in a side view, and each element is located at a predetermined position in the following order from the uppermost layer downward.
Lu-B position O-C position Fe-C position O-B position O-C position Fe-B position O-B position Lu-C position O-A position Fe-A position ○
O-C position ○
O-A position ○
Fe-C position ○
O-C position Lu-A position O-B position Fe-B position O-A position O-B position Fe-A position O-A position Lu-B position
　このうち、○印を付した４層で構成される部分をＷ層(W-Layer)と呼んでおり、このＷ層を有していることがLuFe2O4の特徴点となっている。 Among these, a portion composed of four layers marked with a circle is called a W layer (W-Layer), and having this W layer is a characteristic point of LuFe 2 O 4 .
　また、LuFe2O4以外の層状三角格子構造を有する化合物でも同様にＷ層が形成されていることが知られている。 Further, it is known that a W layer is also formed in a compound having a layered triangular lattice structure other than LuFe 2 O 4 .
　Ｗ層は三角格子の積層構造となっており、LuFe2O4において同数のFe2+とFe3+とを存在させることにより、電荷のフラストレーションを生じさせている。 The W layer has a triangular lattice laminated structure, and the presence of the same number of Fe 2+ and Fe 3+ in LuFe 2 O 4 causes frustration of charges.
　これにより、LuFe2O4では、Ｗ層中においてFe3+の多い領域が正電荷の役割を持ち、一方、Fe2+の多い領域が負電荷の役割を持つこととなって、電気双極子（電気分極）が現れることとなっている。 As a result, in LuFe 2 O 4 , the region rich in Fe 3+ has a role of positive charge in the W layer, while the region rich in Fe 2+ has a role of negative charge. (Electrical polarization) appears.
　しかも、LuFe2O4では、外部から電場を作用させることにより電気双極子の状態を制御でき、この電気双極子の状態に応じてLuFe2O4が異なる電気抵抗を有することとなっている。 Moreover, in LuFe 2 O 4 , the state of the electric dipole can be controlled by applying an electric field from the outside, and LuFe 2 O 4 has different electric resistances depending on the state of the electric dipole.
　このように、希土類元素を含有した層状三角格子構造を有する化合物はＷ層を有するとともに、外部から加えた電場によってＷ層中の電荷秩序構造を制御して異なる電気抵抗の状態を生じさせることができることから、メモリ素子を構成できる。 As described above, a compound having a layered triangular lattice structure containing a rare earth element has a W layer and can control the charge order structure in the W layer by an electric field applied from the outside to generate different states of electrical resistance. Therefore, a memory element can be configured.
　すなわち、本発明のメモリ素子は、図３に示すように、所定の絶縁基板10上に第１電極21と、抵抗体30と、第２電極22とを下から順次積層させて形成しており、第１電極21と第２電極22を所定の電位として抵抗体30に電場を作用させることにより抵抗体30の電気抵抗を変更可能としている。 That is, as shown in FIG. 3, the memory element of the present invention is formed by sequentially laminating a first electrode 21, a resistor 30, and a second electrode 22 on a predetermined insulating substrate 10 from below. The electric resistance of the resistor 30 can be changed by applying an electric field to the resistor 30 with the first electrode 21 and the second electrode 22 set to a predetermined potential.
　第１電極21と第２電極22には、図示しない電圧印加装置を接続して、第１電極21と第２電極22の間の抵抗体30に所定の電場を作用させることとしている。 A voltage application device (not shown) is connected to the first electrode 21 and the second electrode 22 so that a predetermined electric field acts on the resistor 30 between the first electrode 21 and the second electrode 22.
　すなわち、電圧印加装置では、第１電極21の方を第２電極22よりも高電位とするか、第２電極22の方を第１電極21よりも高電位とするかによって抵抗体30に作用させる電場の向きを調整し、抵抗体30を電気抵抗の異なる２つの状態に変更可能としている。ただし、抵抗体30の電気抵抗を変更するためには、所定の閾値以上の電場を抵抗体30に作用させる必要がある。 That is, in the voltage application device, the first electrode 21 acts on the resistor 30 depending on whether the first electrode 21 has a higher potential than the second electrode 22 or the second electrode 22 has a higher potential than the first electrode 21. The direction of the electric field to be adjusted is adjusted so that the resistor 30 can be changed to two states having different electric resistances. However, in order to change the electrical resistance of the resistor 30, it is necessary to apply an electric field of a predetermined threshold value or more to the resistor 30.
　第１電極21及び第２電極22は、AuやCuなどの導電性の高い金属を用いて構成している。 The first electrode 21 and the second electrode 22 are made of a highly conductive metal such as Au or Cu.
　抵抗体20は、本実施形態ではLuFe2O4としている。なお、抵抗体20はLuFe2O4に限定するものではなく、Ｒを、In,Sc,Y,Dy,Ho,Er,Tm,Yb,Lu,Ti,Ca,Sr,Ce,Sn,Hfから選ばれる少なくとも１種類の元素、Ma及びMbを、Ti,Mn,Fe,Co,Cu,Ga,Zn,Al,Mg,Cdから重複を許して選ばれる少なくとも１種類の元素、ｎを１以上の整数、ｍを０以上の整数、δを０以上0.2以下の実数として、(RMbO3-δ)n(MaO)mとして表される層状三角格子構造を有する化合物、またはその化合物のＲの一部を正二価以下の元素により置換した化合物を用いることができる。以下においては、抵抗体20はLuFe2O4として説明する。 The resistor 20 is LuFe 2 O 4 in this embodiment. The resistor 20 is not limited to LuFe 2 O 4 , and R is selected from In, Sc, Y, Dy, Ho, Er, Tm, Yb, Lu, Ti, Ca, Sr, Ce, Sn, and Hf. At least one element selected, Ma and Mb, at least one element selected from Ti, Mn, Fe, Co, Cu, Ga, Zn, Al, Mg, and Cd with duplication allowed, n is one or more A compound having a layered triangular lattice structure represented by (RMbO 3 -δ ) n (MaO) m , where R is an integer, m is an integer of 0 or more, δ is a real number of 0 to 0.2, or a part of R of the compound A compound in which is substituted with an element having a positive divalent value or less can be used. Hereinafter, the resistor 20 will be described as LuFe 2 O 4 .
　上述したメモリ素子は、次のようにして形成することができる。 The memory element described above can be formed as follows.
　まず、絶縁基板10上にスパッタ法などによって第１金属層を形成する。 First, a first metal layer is formed on the insulating substrate 10 by sputtering or the like.
　次いで、この第１金属層上に微粒子状としたLuFe2O4を用いて、ＣＶＤ(Chemical Vapor Deposition)法、スパッタ法、ＭＢＥ(Molecular Beam Epitaxy)法、あるいはエアロゾルデポジション法などによって形成して抵抗体層を形成する。 Next, fine particles of LuFe 2 O 4 are formed on the first metal layer by CVD (Chemical Vapor Deposition), sputtering, MBE (Molecular Beam Epitaxy), or aerosol deposition. A resistor layer is formed.
　次いで、この抵抗体層上にスパッタ法などによって第２金属層を形成する。 Next, a second metal layer is formed on the resistor layer by sputtering or the like.
　その後、この第２金属層の上面にエッチング用のマスクを形成して、エッチングあるいは電子線リソグラフィーにより第２金属層と、抵抗体層と、第１金属層を順次エッチングすることにより、第１電極21、抵抗体30、第２電極22を形成している。なお、抵抗体層は、LuFe2O4の単結晶である方が望ましいが、多結晶であってもよい。 Thereafter, an etching mask is formed on the upper surface of the second metal layer, and the second metal layer, the resistor layer, and the first metal layer are sequentially etched by etching or electron beam lithography to thereby form the first electrode. 21, a resistor 30 and a second electrode 22 are formed. The resistor layer is preferably a single crystal of LuFe 2 O 4 , but may be polycrystalline.
　抵抗体層を形成する場合には、LuFe2O4のｃ軸方向を、第１電極21と第２電極22の対向方向に一致させている。なお、LuFe2O4のｃ軸方向は、第１電極21と第２電極22の対向方向に必ずしも完全に一致させておく必要はなく、少なくともLuFe2O4のｃ軸方向が、第１電極21と第２電極22の対向方向と直交していなければよい。 When the resistor layer is formed, the c-axis direction of LuFe 2 O 4 is made to coincide with the opposing direction of the first electrode 21 and the second electrode 22. Note that the c-axis direction of LuFe 2 O 4 is not necessarily completely coincident with the opposing direction of the first electrode 21 and the second electrode 22, and at least the c-axis direction of LuFe 2 O 4 is the first electrode. It does not have to be orthogonal to the facing direction of 21 and the second electrode 22.
　このように、抵抗体に希土類元素を含有した層状三角格子構造を有する化合物を用いることにより、抵抗体の電気抵抗を容易に切り替えることができるので、消費電力の小さいメモリ素子とすることができる。 Thus, by using a compound having a layered triangular lattice structure containing a rare earth element as a resistor, the electric resistance of the resistor can be easily switched, so that a memory element with low power consumption can be obtained.
　特に、抵抗体に所定の電圧を印加する２つ１組の第１電極21と第２電極22を、化合物のｃ軸方向に離隔させて設けることにより、第１電極21と第２電極22で形成した電場によって抵抗体30の電気抵抗を効果的に変えることができ、さらなる低消費電力化を図ることができる。 In particular, by providing a pair of first electrode 21 and second electrode 22 for applying a predetermined voltage to the resistor, spaced apart in the c-axis direction of the compound, the first electrode 21 and the second electrode 22 The electric resistance of the resistor 30 can be effectively changed by the formed electric field, and the power consumption can be further reduced.
　図１に示したメモリ素子では、第１電極21と第２電極22、及び抵抗体30の幅寸法を同寸法としているが、例えば、図４に示すように、第２電極22'を第１電極21及び抵抗体30よりも小さい幅寸法としてもよい。 In the memory element shown in FIG. 1, the first electrode 21, the second electrode 22, and the resistor 30 have the same width. For example, as shown in FIG. The width may be smaller than that of the electrode 21 and the resistor 30.
　さらには、図５に示すように、第２電極22'を抵抗体30'よりも小さい幅寸法とするとともに、抵抗体30'を第１電極21よりも小さい幅寸法としてもよい。 Furthermore, as shown in FIG. 5, the second electrode 22 ′ may have a width dimension smaller than that of the resistor 30 ′, and the resistor 30 ′ may have a width dimension smaller than that of the first electrode 21.
　あるいは、図６に示すように、第１電極21"と第２電極22"の幅寸法を、抵抗体30"の幅寸法よりも小さくしてもよい。 Alternatively, as shown in FIG. 6, the width dimension of the first electrode 21 "and the second electrode 22" may be smaller than the width dimension of the resistor 30 ".
　また、第１電極21と第２電極22は上下方向に離隔させて形成する場合だけでなく、例えば、図７に示すように、絶縁基板40の面方向に所定寸法だけ離隔させて第１電極51と第２電極52を設け、第１電極51と第２電極52の間に希土類元素を含有した層状三角格子構造を有する化合物からなる抵抗体60を設けてもよい。 In addition, the first electrode 21 and the second electrode 22 are not only formed apart in the vertical direction, but, for example, as shown in FIG. 7, the first electrode 21 is separated by a predetermined dimension in the surface direction of the insulating substrate 40. 51 and a second electrode 52 may be provided, and a resistor 60 made of a compound having a layered triangular lattice structure containing a rare earth element may be provided between the first electrode 51 and the second electrode 52.
　この場合、絶縁基板40上には、微粒子状としたLuFe2O4を用いて、ＣＶＤ法、スパッタ法、ＭＢＥ法、あるいはエアロゾルデポジション法などによって抵抗体層をあらかじめ形成し、この抵抗体層を電子線リソグラフィーなどによって所定のセル形状として抵抗体60を形成している。 In this case, a resistor layer is formed in advance on the insulating substrate 40 by using a fine particle form of LuFe 2 O 4 by a CVD method, a sputtering method, an MBE method, an aerosol deposition method, or the like. The resistor 60 is formed into a predetermined cell shape by electron beam lithography or the like.
　その後、絶縁基板40上には、スパッタ法などによって金属層を形成して抵抗体60を被覆し、第１電極51及び第２電極52を形成するためのエッチング用の第１マスクを形成して金属層をエッチングすることにより、絶縁基板40の面方向に第１電極51と、抵抗体60と、第２電極52を配設している。なお、抵抗体60を第１電極51と第２電極52よりも先に形成するのではなく、第１電極51と第２電極52を抵抗体60よりも先に形成してもよい。 Thereafter, a metal layer is formed on the insulating substrate 40 by sputtering or the like to cover the resistor 60, and a first mask for etching for forming the first electrode 51 and the second electrode 52 is formed. By etching the metal layer, the first electrode 51, the resistor 60, and the second electrode 52 are arranged in the surface direction of the insulating substrate 40. Instead of forming the resistor 60 before the first electrode 51 and the second electrode 52, the first electrode 51 and the second electrode 52 may be formed before the resistor 60.
　ここで、図７に示すように絶縁基板40の面方向に第１電極51と、抵抗体60と、第２電極52を配設する場合には、抵抗体60を構成する化合物のｃ軸方向を絶縁基板40の面方向としている。 Here, when the first electrode 51, the resistor 60, and the second electrode 52 are disposed in the plane direction of the insulating substrate 40 as shown in FIG. 7, the c-axis direction of the compound constituting the resistor 60 Is the surface direction of the insulating substrate 40.
　すなわち、表面の結晶面を調整した絶縁基板40を用いて抵抗体60を形成することにより、抵抗体60を構成する化合物のｃ軸方向を絶縁基板10の面方向とすることができる。本実施形態では、絶縁基板40にはScAlMgO4を用いている。 That is, by forming the resistor 60 using the insulating substrate 40 whose surface crystal plane is adjusted, the c-axis direction of the compound constituting the resistor 60 can be the plane direction of the insulating substrate 10. In this embodiment, ScAlMgO 4 is used for the insulating substrate 40.
　上述した実施形態では、第１電極21,51と第２電極22,52によって抵抗体30,60に作用させる電場の方向が、絶縁基板10の垂直方向と、絶縁基板40の面方向とのいずれかとなっているが、場合によっては、図８に示すように、絶縁基板70の上面に設けた第１電極81に対して、抵抗体90を挟んで第２電極82を斜め上方位置に設けてもよい。 In the above-described embodiment, the direction of the electric field applied to the resistors 30 and 60 by the first electrodes 21 and 51 and the second electrodes 22 and 52 is either the vertical direction of the insulating substrate 10 or the surface direction of the insulating substrate 40. However, in some cases, as shown in FIG. 8, the second electrode 82 is provided obliquely above the first electrode 81 provided on the upper surface of the insulating substrate 70 with the resistor 90 interposed therebetween. Also good.
　上述したメモリ素子を用いて記憶装置を構成することができる。記憶装置では、図９に示すように、記憶容量に応じた数のメモリ素子ｍを行列状に配設している。 A storage device can be configured using the memory element described above. In the storage device, as shown in FIG. 9, the number of memory elements m corresponding to the storage capacity is arranged in a matrix.
　メモリ素子ｍの第１電極には第１配線101を接続し、メモリ素子ｍの第２電極には、制御用トランジスタｔを介して第２配線102を接続している。 The first wiring 101 is connected to the first electrode of the memory element m, and the second wiring 102 is connected to the second electrode of the memory element m via the control transistor t.
　本実施形態の記憶装置では、図９中において縦方向に並んだメモリ素子ｍは１本の第１配線101を共用しており、図９中において横方向に並んだメモリ素子ｍは１本の第２配線102を共用している。 In the memory device of this embodiment, the memory elements m arranged in the vertical direction in FIG. 9 share one first wiring 101, and the memory elements m arranged in the horizontal direction in FIG. The second wiring 102 is shared.
　第１配線101は第１ドライバ回路103に接続し、第２配線102は第２ドライバ回路104にして、第１ドライバ回路103と第２ドライバ回路104によって、第１配線101及び第２配線102を介してメモリ素子ｍに所定の電場を作用させるようにしている。 The first wiring 101 is connected to the first driver circuit 103, the second wiring 102 is the second driver circuit 104, and the first wiring 101 and the second wiring 102 are connected by the first driver circuit 103 and the second driver circuit 104. A predetermined electric field is applied to the memory element m.
　第１ドライバ回路103と第２ドライバ回路104は、それぞれ図示しない主制御部から入力された制御信号によって制御している。 The first driver circuit 103 and the second driver circuit 104 are controlled by control signals input from a main control unit (not shown).
　制御用トランジスタｔのゲートには、それぞれ制御信号線105を接続しており、この制御信号線105は第３ドライバ回路106に接続して、第３ドライバ回路106から制御信号線105に出力された制御信号によって制御用トランジスタｔのオン・オフの切替制御を行っている。 A control signal line 105 is connected to each gate of the control transistor t. The control signal line 105 is connected to the third driver circuit 106 and output from the third driver circuit 106 to the control signal line 105. The control transistor t performs on / off switching control of the control transistor t.
　図９中において横方向に並んだ制御用トランジスタｔは１本の制御信号線105を共用している。第３ドライバ回路106も図示しない主制御部から入力された制御信号によって制御している。 In FIG. 9, the control transistors t arranged in the horizontal direction share one control signal line 105. The third driver circuit 106 is also controlled by a control signal input from a main control unit (not shown).
　このように構成した記憶装置において所定のデータを記憶する場合には、第１ドライバ回路103で所定のデータを記憶するメモリ素子ｍに接続した第１配線101を第１の電位とし、第２ドライバ回路104で所定のデータを記憶するメモリ素子ｍに接続した第２配線102を第２の電位として、第３ドライバ回路106で所定のデータを記憶するメモリ素子ｍに接続した制御用トランジスタｔにオン信号を入力している。 When storing predetermined data in the storage device configured as described above, the first wiring 101 connected to the memory element m storing the predetermined data in the first driver circuit 103 is set to the first potential, and the second driver The second wiring 102 connected to the memory element m that stores predetermined data in the circuit 104 is set to the second potential, and the third transistor circuit 106 turns on the control transistor t connected to the memory element m that stores predetermined data. A signal is being input.
　したがって、第１の電位となった第１電極と、第２の電位となった第２電極によって、メモリ素子ｍの抵抗体に所定の電場を作用させることができ、抵抗体の電気抵抗を所定の電気抵抗としている。 Therefore, a predetermined electric field can be applied to the resistor of the memory element m by the first electrode having the first potential and the second electrode having the second potential, and the electric resistance of the resistor can be set to a predetermined value. The electrical resistance is.
　なお、図９中において横方向に並んだ制御用トランジスタｔは１本の制御信号線105を共用しているため、所定のデータを記憶するメモリ素子ｍに接続した制御用トランジスタｔだけでなく、横方向に並んだ全ての制御用トランジスタｔがオン状態となっている。 In addition, since the control transistors t arranged in the horizontal direction in FIG. 9 share one control signal line 105, not only the control transistor t connected to the memory element m that stores predetermined data, All the control transistors t arranged in the horizontal direction are in the on state.
　このとき、所定のデータを記憶するメモリ素子ｍ以外のメモリ素子ｍには、第１ドライバ回路103と第２ドライバ回路104によって、それぞれのメモリ素子ｍの第１電極と第２電極を同電位とすることにより、メモリ素子ｍに無意味なデータが書き込まれることを防止している。 At this time, the first driver circuit 103 and the second driver circuit 104 cause the first electrode and the second electrode of each memory element m to have the same potential in the memory elements m other than the memory element m that stores predetermined data. This prevents meaningless data from being written in the memory element m.
　一方、所定のメモリ素子ｍからデータを読み出す場合には、第３ドライバ回路106でデータを読み出すメモリ素子ｍに接続した制御用トランジスタｔにオン信号を入力し、第１ドライバ回路103と第２ドライバ回路104とによって第１配線101及び第２配線102を介してデータを読み出すメモリ素子ｍに所定の読み出し用の電流を流している。 On the other hand, when data is read from the predetermined memory element m, an ON signal is input to the control transistor t connected to the memory element m from which the third driver circuit 106 reads data, and the first driver circuit 103 and the second driver A predetermined read current is supplied to the memory element m from which data is read by the circuit 104 via the first wiring 101 and the second wiring 102.
　そして、この読み出し用の電流の値を第１ドライバ回路103または第２ドライバ回路104で検出し、この電流の値と所定の閾値との比較を行って、メモリ素子ｍの抵抗状態を検出してデータを読み出している。 Then, the value of the current for reading is detected by the first driver circuit 103 or the second driver circuit 104, and the resistance value of the memory element m is detected by comparing this current value with a predetermined threshold value. Reading data.
　なお、メモリ素子ｍからデータを読み出す際には、メモリ素子ｍにおける抵抗体において抵抗状態が変化する電場よりも小さい電場でが作用する状態として、データの読み出しにともなってメモリ素子ｍで記憶されているデータが書き換えられないようにしている。 When data is read from the memory element m, it is stored in the memory element m as the data is read as a state where an electric field smaller than the electric field whose resistance state changes in the resistor in the memory element m acts. Data is not overwritten.
　このように、メモリ素子ｍでは、データを書き込む場合と、データを読み出す場合とで第１電極及び第２電極を共用し、第１電極と第２電極を抵抗体の電気抵抗を検出するための電圧検出用の電極としても用いることにより、メモリ素子ｍの構造が複雑化することを防止でき、極めて容易にメモリ素子ｍを形成することができる。 As described above, in the memory element m, when writing data and when reading data, the first electrode and the second electrode are shared, and the first electrode and the second electrode are used for detecting the electrical resistance of the resistor. By using it as an electrode for voltage detection, the structure of the memory element m can be prevented from becoming complicated, and the memory element m can be formed very easily.
　本発明によれば、低消費電力のメモリ装置を提供できる。 According to the present invention, a low power consumption memory device can be provided.

Claims (6)

  1. 　電圧を印加することにより電気抵抗が変化する抵抗体と、
    　前記抵抗体に所定の電圧を印加するための電圧印加用の電極と
    を有するメモリ素子であって、
    　前記抵抗体を希土類元素を含有した層状三角格子構造を有する化合物で構成したメモリ素子。     A resistor whose electrical resistance changes by applying a voltage;
    A memory element having a voltage application electrode for applying a predetermined voltage to the resistor,
    A memory element in which the resistor is composed of a compound having a layered triangular lattice structure containing a rare earth element.
  2. 　前記抵抗体が、
    　Ｒを、In,Sc,Y,Dy,Ho,Er,Tm,Yb,Lu,Ti,Ca,Sr,Ce,Sn,Hfから選ばれる少なくとも１種類の元素、
    　Ma及びMbを、Ti,Mn,Fe,Co,Cu,Ga,Zn,Al,Mg,Cdから重複を許して選ばれる少なくとも１種類の元素、
    　ｎを１以上の整数、
    　ｍを０以上の整数、
    　δを０以上0.2以下の実数
    として、(RMbO3-δ)n(MaO)mとして表される層状三角格子構造を有する化合物、またはその化合物のＲの一部を正二価以下の元素により置換した化合物である請求項１に記載のメモリ素子。     The resistor is
    R is at least one element selected from In, Sc, Y, Dy, Ho, Er, Tm, Yb, Lu, Ti, Ca, Sr, Ce, Sn, and Hf,
    Ma and Mb, at least one element selected from Ti, Mn, Fe, Co, Cu, Ga, Zn, Al, Mg, and Cd with duplication allowed,
    n is an integer of 1 or more,
    m is an integer greater than or equal to 0,
    A compound having a layered triangular lattice structure represented as (RMbO 3 -δ ) n (MaO) m , where δ is a real number of 0 or more and 0.2 or less, or a part of R of the compound was substituted with an element less than positive divalent The memory element according to claim 1, wherein the memory element is a compound.
  3. 　前記電圧印加用の電極は２つ１組として前記抵抗体を挟んで対向させて設けるとともに、前記電圧印加用の電極を前記抵抗体の電気抵抗を検出するための電圧検出用の電極と兼用している請求項１または請求項２に記載のメモリ素子。 The voltage application electrodes are provided as a pair so as to face each other with the resistor interposed therebetween, and the voltage application electrode is also used as a voltage detection electrode for detecting the electrical resistance of the resistor. The memory element according to claim 1 or 2.
  4. 　前記電圧印加用の電極は、前記抵抗体を構成している前記化合物のｃ軸方向に離隔させて設けている請求項３に記載のメモリ素子。 4. The memory element according to claim 3, wherein the voltage application electrodes are provided apart from each other in the c-axis direction of the compound constituting the resistor.
  5. 　電圧を印加することにより電気抵抗が変化する抵抗体と、
    　前記抵抗体に所定の電圧を印加するための電圧印加用の電極と
    を有するメモリ素子の製造方法であって、
    　前記抵抗体を希土類元素を含有した層状三角格子構造を有する化合物で形成する工程を有するメモリ素子の製造方法。     A resistor whose electrical resistance changes by applying a voltage;
    A method of manufacturing a memory element having a voltage application electrode for applying a predetermined voltage to the resistor,
    A method for manufacturing a memory element, comprising the step of forming the resistor with a compound having a layered triangular lattice structure containing a rare earth element.
  6. 　電圧を印加することにより電気抵抗が変化する抵抗体と、
    　前記抵抗体に所定の電圧を印加するための電圧印加用の電極と
    をそれぞれ有する複数のメモリ素子を備えた記憶装置であって、
    　前記抵抗体を希土類元素を含有した層状三角格子構造を有する化合物で構成した記憶装置。     A resistor whose electrical resistance changes by applying a voltage;
    A storage device comprising a plurality of memory elements each having a voltage application electrode for applying a predetermined voltage to the resistor,
    A memory device in which the resistor is composed of a compound having a layered triangular lattice structure containing a rare earth element.
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