WO2010035344A1

WO2010035344A1 - Information processing device, power supply control method, and power supply control program

Info

Publication number: WO2010035344A1
Application number: PCT/JP2008/067666
Authority: WO
Inventors: 智和土屋
Original assignee: 富士通株式会社
Priority date: 2008-09-29
Filing date: 2008-09-29
Publication date: 2010-04-01

Abstract

An information processing device comprises one or a plurality of storage units the number of which is changeable, an arithmetical unit for performing information processing with the one or plurality of storage units, a plurality of power supply units for supplying power to the one or plurality of storage units, means for detecting the number of the one or plurality of storage units, and means for determining the number of power supply units to be actually operated out of the plurality of power supply units according to the detected number of the one or plurality of storage units.

Description

Information processing apparatus, power supply control method, and power supply control program

The present invention relates to an information processing apparatus, a power control method, and a power control program. In particular, the present invention relates to an information processing apparatus that uses one or a plurality of storage devices, a power control method for controlling a power supply device that supplies power to the storage devices, and a program for causing a computer to execute the method.

In recent years, servers, personal computers, home appliances, and the like have been required to reduce power consumption and heat generation due to power loss. For example, an information processing apparatus such as a server having the following configuration is known. That is, the information processing apparatus is equipped with a storage device such as a plurality of DIMMs (dual inline memory module: dual inline memory module, hereinafter the same). Further, the information processing apparatus is equipped with a power supply device such as a plurality of DC-DC converters for supplying a power supply current to the storage device. Here, assuming that the maximum number of DIMMs is mounted, a plurality of the power supply devices are installed in parallel.

In the information processing apparatus having such a configuration, the following problems may occur when the actual number of installed DIMMs is small. That is, it is conceivable that as many power supply devices as can supply power more than the number of DIMMs currently installed in the information processing apparatus need operate. In such a case, the amount of power supplied per power supply device is smaller than when power is supplied by a smaller number of power supply devices. When the supply amount of power per power supply device is extremely reduced, the operation efficiency of the power supply device is lowered. That is, when the actual number of installed DIMMs is small, useless power may be consumed by the power supply device.

FIG. 1 is a diagram for explaining this point. FIG. 1 shows the operating efficiency (Efficiency) of the power supply device with respect to the current value (Iout) supplied by one power supply device. In FIG. 1, it can be seen that the operation efficiency is low in the region Z1 where the supplied current value is relatively small, and the operation efficiency is high in the region Z2 where the supplied current value is relatively large.

There is known a method for detecting the total current of the outputs of a plurality of power supply devices provided in parallel as described above and controlling the number of power supply devices to be operated according to the total current amount related to the detection.
Japanese Patent Laid-Open No. 11-127573

In an information processing apparatus having one or a plurality of storage devices whose number can be changed and a plurality of power supply devices that supply power to the storage devices, the operation efficiency of the power supply devices is effectively improved with a simple configuration. The purpose is to let you.

Means for detecting the number of one or more storage devices in an information processing device having one or more storage devices whose number can be changed and a plurality of power supply devices for supplying power to the storage devices Is provided. The information processing apparatus further includes means for controlling the number of power supply devices to be actually operated among the plurality of power supply devices in accordance with the detected number of one or more storage devices.

The disclosed information processing device controls the number of power supply devices that are actually operated among the plurality of power supply devices in accordance with the detected number of one or more storage devices. Therefore, the operation efficiency of the power supply device can be effectively improved with a simple configuration.

It is a figure for demonstrating the operating efficiency of a power supply device. FIG. 3 is a block diagram (part 1) for explaining the configuration and operation of the first embodiment. FIG. 3 is a block diagram (No. 2) for explaining the configuration and operation of the first embodiment. It is a block diagram for demonstrating the structural example of the system board in FIG. 2A, 2B. It is a block diagram for demonstrating the structural example of the control board in FIG. 2A, 2B. 3 is a flowchart for explaining an operation of the first embodiment. FIG. 6 is a diagram (part 1) for explaining the operation of the first embodiment; FIG. 6 is a second diagram for explaining the operation of the first embodiment; 6 is a block diagram for explaining the configuration and operation of Embodiment 2. FIG. FIG. 8 is a circuit diagram illustrating a circuit configuration example of a power supply control circuit in FIG. 7. It is a figure for demonstrating the terminal for present signals provided in DIMM in FIG. It is a figure for demonstrating the structural example of the present signal generation circuit in FIG.

Explanation of symbols

100 Control board (computer)
200 System board 210, 210-1 to 210-4 Memory controller 220, 220-1 to 220-16 DIMM (storage device)
230 North Bridge 241-244 CPU (arithmetic unit)
280 Present signal generation circuit 281 to 286 Short circuit detection circuit 300 GPIO
410, 420 Power supply device 500 Power supply control circuit enable signal enable signal Present 1-6 present signal TX1, TX2 Present signal terminal (DIMM)
TY1 to TY6 Present signal terminals (present signal generation circuit)

In the disclosed information processing apparatus, the number of power supply apparatuses actually used is changed according to the actual number of storage devices such as DIMMs. As a result, the power supply device can be operated in a highly efficient state. By using this method, it is possible to operate the power supply apparatus in a highly efficient state using a control means that is relatively inexpensive and has a low failure rate.

That is, in the disclosed information processing apparatus, in order to control the number of operating power supply apparatuses, the number and types of storage devices actually mounted on the information processing apparatus are grasped. Then, a number of power supply devices suitable for supplying necessary power to the actually mounted storage device are operated.

Hereinafter, Example 1 will be described with reference to the drawings.

FIG. 2A is a block diagram illustrating a schematic configuration of the information processing apparatus according to the first embodiment.

The information processing apparatus is, for example, a server that provides various services in response to requests from client computers. In the following description of the first embodiment, the information processing apparatus according to the first embodiment will be described as a server. However, it goes without saying that the first embodiment can be realized by an information processing apparatus other than the server.

As shown in FIG. 2A, the server includes a control board 100, a system board 200, a GPIO (General Purpose I / O, hereinafter the same) 300, and two

power supply units

410, 420.

The system board 200 is a functional unit for actually providing the service provided by the server. As shown in FIG. 2A, the system board 200 includes a memory controller 210 and can mount one or a plurality of DIMMs 220.

FIG. 3 is a block diagram showing a detailed configuration example of the system board 200. As shown in FIG. 3, the system board 200 includes four CPUs 241 to 244, a north bridge 230, and four memory controllers 210-1 to 210-4. The system board 200 can include one or more DIMMs 220-1 to 220-16. 2A and 2B, the four memory controllers 210-1 to 210-4 are collectively referred to as a memory controller 210. In the following description, the four memory controllers 210-1 to 210-4 are collectively referred to as a memory controller 210. 2A and 2B, the 16 DIMMs 220-1 to 220-16 are collectively referred to as DIMM 220. In the following description, DIMMs 220-1 to 220-16 are collectively referred to as DIMM 220. Here, in FIG. 3, a total of 16 DIMMs 220-1 to 220-16 are shown as being included in the system board 200. However, in actuality, the server can be operated with only one or a plurality of DIMMs among the 16 DIMMs 220-1 to 220-16 mounted on the system board 200.

The system board 200 having such a configuration actually provides various services to be provided by the server when the CPUs 241 to 244 execute necessary information processing using the mounted DIMM 220 as appropriate.

Firmware is mounted on the control board 100, and the number of DIMMs 220 actually mounted on the system board 200 is detected by the function of the firmware. Further, the control board 100 grasps the type of the DIMM 220 actually mounted by the function of the firmware. More specifically, the control board 100 reads SPD (Serial Presence Detect, the same applies hereinafter) information of each DIMM 220 actually mounted. In the first embodiment, the control board 100 can read the SPD information using the I2C (inter-integrated circuit, the same applies hereinafter) via the memory controller 210. The control board 100 grasps the specification content of the DIMM 220 by reading the SPD information of the DIMM 220 in this way. Specific examples of the contents of the SPD information include, for example, the type, configuration, capacity, access speed, access method, and the like of the DIMM 200.

FIG. 4 is a block diagram showing a schematic configuration of the control board 100. As shown in FIG. 4, the control board 100 includes a CPU 110, a memory 120 on which the firmware and the like are mounted, and an I / O 130. Here, the I / O 130 is an interface IC, and the control board 100 communicates with the system board 200 or the GPIO 300 via the I / O 130 using I2C. Further, as described above, the control board 100 can grasp the number of DIMMs 220 mounted based on the SPD information of the DIMM 200 by executing the firmware mounted in the memory 120 as described above.

The GPIO 300 is an I / O port for receiving an instruction by an I2C signal from the control board 100 and transmitting an enable signal (that is, an enable signal, the same applies hereinafter) to the

power supply devices

410 and 420 according to the contents of the instruction.

The

power supply devices

410 and 420 are power supplies that supply power to the DIMM 220 mounted on the system board 200, and can be, for example, DC-DC converters. Each

power supply device

410 and 420 is operated only while the enable signal received from the control board 100 via the GPIO 300 is at a high level, and supplies power to the DIMM 220 during that time.

2A shows a state where a relatively large number of DIMMs 220 are mounted on the system board 200 of the server, and FIG. 2B shows a state where a relatively small number of DIMMs 220 are mounted on the system board 200. The following operation is performed by the firmware function of the control board 100 described later with reference to FIG. That is, when a relatively large number of DIMMs 220 are mounted as shown in FIG. 2A, the state is automatically detected, and high level enable signals are transmitted to both of the two

power supply devices

410 and 420, respectively. As a result, the two

power supply devices

410 and 420 operate, and power is supplied from the two

power supply devices

410 and 420 to the relatively large number of DIMMs 220. On the other hand, when a relatively small number of DIMMs 220 as shown in FIG. 2B are mounted, the state is automatically detected, and only one power supply 410 out of the two

power supplies

410 and 420 is used. A high level enable signal is transmitted. As a result, only the one power supply device 410 operates, and power is supplied from the single power supply device 410 to the relatively few DIMMs 220. As a result, when the number of DIMMs 220 that require power supply is large, a relatively large number of power supply devices are operated to supply power. Similarly, when the number of DIMMs 220 requiring power supply is small, only a relatively small number of power supply devices are operated to supply power. As a result, when the supply amount of power is small, it is possible to prevent the amount of power supplied per power supply device from being excessively reduced, and as described above with reference to FIG. 1, the operation efficiency of each power supply device can be improved. it can.

That is, the firmware mounted in the memory 120 of the control board 100 of the server according to the first embodiment having the above configuration is executed by the CPU 110, and the following operation is performed. Hereinafter, an operation performed by the CPU 110 when the firmware is executed will be described with reference to FIG.

5, the following information is stored in advance in the memory 120 of the control board 100 as information that can be referred to when the CPU 110 executes the firmware. That is, first table information indicating the number of the two

power supply devices

410, 420 to be actually operated is stored in accordance with the total power consumption value of the DIMM 220 actually mounted on the system board 200. FIG. 6A shows an example of the first table information. The example of FIG. 6A is an example of a case where the number of

power supply devices

410 and 420 is not limited to two, 410, and 420 as in the first embodiment, and the case of three or more power supply devices is also assumed. . That is, in the case of FIG. 6A, the high level that the control board 100 transmits via the GPIO 300 in each case where the total power consumption of the DIMM 220 actually mounted on the system board 200 is P1, P2, P2,. The number of enable signals n1, n2, n3,. Here, each of the transmitted enable signals is given to a corresponding power supply device. Therefore, the number of high-level enable signals to be transmitted indicates the number of power supply devices that are actually operated. In FIG. 6A, P1 <P2 <P3 <... and n1 <n2 <n3 <.... That is, the contents of the first table information are determined such that the greater the total power consumption of DIMMs actually mounted on the system board 200, the greater the number of power supply devices that supply power to the DIMMs.

Returning to the description of FIG. 5, in step S2, the memory 120 of the control board 100 further stores the following information in advance as information that can be referred to by the CPU 110 executing the firmware. That is, information indicating the power consumption per DIMM for each type of DIMM 220 mounted on the system board 200 is stored in advance in the memory 120 as the second table information. FIG. 6B shows an example of the second table information. In FIG. 6B, with respect to type-1, type-2,... As types of DIMMs 220 actually mounted on the system board 200, respective power consumptions of the corresponding types of DIMMs 220, p1, p2,. Is stored.

Returning to the description of FIG. 5, in step S <b> 3, the firmware acquires the SPD information of the DIMM 220 actually mounted on the system board 200 via the memory controller 210. Then, the firmware grasps the total number of DIMMs 220 actually mounted on the system board 200 from the SPD information. Here, the SPD information is individually stored in each DIMM 220 for each of the DIMMs 220. Therefore, the number of DIMMs 220 actually mounted on the system board 200 can be grasped by counting the number of SPD information obtained from each of the DIMMs 220 actually mounted on the system board 200. The firmware further obtains information indicating the type of the corresponding DIMM 220 included in the SPD information of each DIMM 220 actually mounted on the system board 200. The firmware obtains the power consumption value per corresponding DIMM 2201 by referring to the second table information described above with reference to FIG. 6B.

In step S4, the firmware calculates the total power consumption of the DIMM 220 actually mounted on the system board 200. Here, as an example, it is assumed that the types of DIMMs 220 actually mounted on the system board 200 are all common, for example, type-1. In this case, p1 is obtained as the power consumption value for each of all the DIMMs 220 actually mounted on the system board 200 by the second table information in FIG. 6B. In this case, the number of DIMMs 220 actually mounted on the system board 200 obtained in step S3 as described above may be multiplied by the common power consumption p1. As a result, the total power consumption value of all the DIMMs 220 actually mounted on the system board 200 is obtained.

Next, as an example different from the above example, a case where different types of DIMMs are mixed in the DIMM 220 actually mounted on the system board 200 is assumed. In this case, by summing up the number of DIMMs for each type of DIMM and multiplying by the power consumption of the DIMM of that type, the total power consumption of the DIMM for each type can be obtained. Next, the power consumption of each type of DIMM thus obtained is summed over all types. As a result, the total power consumption value of all the DIMMs 220 actually mounted on the system board 200 is obtained.

Next, in step S5, the first table information in FIG. 6A is referred to. The number of high-level enable signals required for the total power consumption value of all DIMMs 220 actually mounted on the system board 200 obtained in step S4 as described above can be obtained. . The firmware of the control board 100 transmits the required number of high-level enable signals to the power supply device via the GPIO 300. As a result, the same number of power supply devices are operated by each of the transmitted number of high-level enable signals, and power is supplied to all the DIMMs 220 by the power supply device.

As described above, in the first embodiment, the firmware of the control board 100 determines the number of installed DIMMs 220 and the type of the installed DIMM 220. More specifically, the firmware of the control board 100 grasps the type of the DIMM 220 from the SPD information of the DIMM 220. The firmware refers to the second table information, and obtains the power consumption value per DIMM corresponding to the type of the DIMM 220. As a result, the firmware can grasp the power consumption of the DIMM 220. Then, the firmware calculates the power consumption of all the DIMMs 220 actually mounted on the system board 200 from the information on the number of mounted DIMMs 220 and the power consumption of each mounted DIMM obtained as described above. The firmware supplies a corresponding number of high-level enable signals according to the first table information in order to operate a number of

power supply apparatuses

410 and 420 suitable for supplying power consumption of all the DIMMs 220. Send to device. In the case of the first embodiment, the total number of

power supply devices

410 and 420 is two. Therefore, the firmware determines one or two

power supply devices

410 and 420 suitable for supplying the power consumption of all the DIMMs 220. When one is determined as the number of

power supply devices

410 and 420 to be operated here, as shown in FIG. 2B, the firmware transmits only an enable signal for operating the power supply device 410 at a high level. That is, in this case, the firmware does not set the enable signal for operating the power supply device 420 to the high level. As a result, in this case, only the power supply device 410 is operated. On the other hand, when two

power supply devices

410 and 420 to be operated are determined, the firmware sets an enable signal for operating the power supply device 410 to a high level as shown in FIG. 2A. In this case, the firmware also sets the enable signal for operating the power supply device 420 to a high level. As a result, in this case, both

power supply devices

410 and 420 are operated.

As described above, according to the first embodiment, the power consumption of all DIMMs actually mounted on the system board 200 can be obtained by the firmware mounted on the control board 100. When the power consumption of all the DIMMs is relatively small, only one power supply device 410 is operated out of the two

power supply devices

410 and 420 as shown in FIG. 2B. In this case, only the one power supply device 410 supplies power to all DIMMs actually mounted on the system board 200. On the other hand, when the power consumption of all DIMMs actually mounted on the system board 200 is relatively large, the following operation is performed as shown in FIG. 2A. That is, in this case, both of the two

power supply devices

410 and 420 are operated. As a result, the two

power supply devices

410 and 420 supply power to all DIMMs actually mounted on the system board 200. As a result, an appropriate number of power supply devices corresponding to the power consumption of all DIMMs actually mounted on the system board 200 are operated. As a result, as described above, the individual operation efficiency of the

power supply devices

410 and 420 can be effectively improved.

In the first embodiment, in order to obtain SPD information from the DIMM 220 actually mounted on the system board 200, it is necessary to supply power to the DIMM 220. Therefore, the firmware of the control board 100 performs the following operations, for example. That is, when the server is started, the enable signals for the two

power supply devices

410 and 420 are set to the high level, respectively, and the two

power supply devices

410 and 420 are once operated. In this state, when the two

power supply devices

410 and 420 are operated and power is supplied to the DIMM 220 actually mounted on the system board 200, the firmware obtains the SPD information from the DIMM 220 via the memory controller 210. . The firmware calculates the power consumption of all DIMMs 220 actually mounted on the system board 200 based on the SPD information as described above. The firmware determines the number of power supply devices to be operated based on the calculated power consumption of all DIMMs. When the number of power supply devices related to the determination is 1, the firmware sets the enable signal for operating the power supply device 420 to a low level and stops the operation of the power supply device 420. As a result, only one power supply device 410 continues to operate. On the other hand, when the number of the power supply devices according to the above determination is 2, the enable signal for operating the power supply device 420 is continuously set to the high level as it is, and the operations of both of the two

power supply devices

410 and 420 are continued. .

Next, Example 2 will be described with reference to FIGS.

The information processing apparatus according to the second embodiment is, for example, a server that provides various services in response to requests from a client computer, like the information processing apparatus according to the first embodiment. Hereinafter, also in the description of the second embodiment, the information processing apparatus according to the second embodiment will be described as a server. However, it is needless to say that the second embodiment can be realized by an information processing apparatus other than the server.

The server includes a control board 100, a system board 200, a GPIO (General Purpose I / O, hereinafter the same) 300, a power supply control circuit 500, and

power supply apparatuses

410 and 420 as shown in FIG.

As in the case of the first embodiment, the system board 200 is a functional unit for actually providing a service provided by the server in the server. As shown in FIG. 7, the system board 200 can mount one or more DIMMs 220.

FIG. 3 is a block diagram showing a detailed configuration of the system board 200. The configuration of the system board 200 is the same as that of the system board 200 in the server of the first embodiment described above, and redundant description is omitted. However, as will be described later, in the case of the second embodiment, unlike the case of the first embodiment, the system board 200 is provided with a presence signal generation circuit 280. Further, as in the first embodiment, in the system board 200, the CPUs 241 to 244 execute necessary information processing by appropriately using the mounted DIMM 220, and actually provide the service to be provided by the server.

The control board 100 is equipped with firmware, and the firmware performs the following operations. That is, when the server is started, in order to supply power to the DIMM 220 mounted on the system board 200, the enable signal for the

power supply devices

410 and 420 is set to the high level via the GPIO 300 and the power supply control circuit 500.

FIG. 4 is a block diagram showing a schematic configuration of the control board 100. The configuration of the control board 100 is the same as that of the control board 100 in the server of the first embodiment described above, and redundant description is omitted. However, in the case of the second embodiment, the firmware installed in the memory 120 may be different from the firmware installed on the control board 100 of the server of the first embodiment. That is, in the case of the second embodiment, the firmware includes the number of

power supply devices

410 and 420 for calculating and operating the power consumption of the DIMM actually mounted on the system board 200 as described above in the description of the first embodiment. The function to decide is unnecessary. In the case of the second embodiment, as will be described later, a power supply control circuit 500 and the like are provided and perform necessary functions.

The GPIO 300 receives an instruction from the control board 100 using an I2C signal, and transmits an enable signal (that is, an enable signal, the same applies hereinafter) to the

power supply apparatuses

410 and 420 via the power supply control circuit 500 in accordance with the contents of the instruction. / O port. The power supply control circuit 500 will be described later.

The

power supply devices

410 and 420 supply power to the DIMM 220 mounted on the system board 200, and each can be a DC-DC converter, for example, as in the first embodiment. Each

power supply device

410 or 420 is operated only while receiving a high level enable signal A or B from the control board 100 via the GPIO 300 and the power supply control circuit 500, and supplies power to the DIMM 220 during that time.

Hereinafter, operations of the

power supply devices

410 and 420 in the server according to the second embodiment having the above-described configuration will be described with reference to the drawings. As in the case of the first embodiment, the server according to the second embodiment can mount a total of 16 DIMMs 220-1 to 220-16 on the system board 200 as shown in FIG. However, in the description of the second embodiment, for convenience of explanation, as shown in FIG. 7, it is assumed that one or more and six or less DIMMs 220 can be mounted on the system board 200. The six DIMMs 220 are installed in the corresponding six slots of the system board 200. When only one DIMM 220 is installed on the system board, the first DIMM is always installed in the first slot. Shall. Similarly, when only two DIMMs 220 are mounted on the system board, the first and second DIMMs are always mounted in the first and second slots, respectively. Similarly, when only n (where n is any one of 3 to 6) DIMMs 220 are mounted on the system board, the 1st to nth DIMMs are always installed in the 1st to nth slots, respectively. That is, for example, when only one DIMM 220 is mounted on the system board 200, the sixth DIMM is not mounted in the sixth slot.

First, the configuration of the power supply control circuit 500 when it is possible to mount one or more and six or less DIMMs 220 on the system board 200 as described above will be described with reference to FIG.

The power supply control circuit 500 has six present signal input terminals 1 to 6 for present signals Present 1 to 6 and a terminal ENABLE that receives an enable signal ENABLE transmitted from the GPIO 300. The power supply control circuit 500 has a terminal A that outputs an enable signal A to the power supply device 410 and a terminal B that outputs an enable signal B to the power supply device 420. The power supply control circuit 500 has OR logic elements OR1, OR2 and AND logic elements AND1, AND2, AND3.

In the power supply control circuit 500, the present signal input terminals 1 to 3 are respectively connected to three input terminals of an OR logic element OR1 and an AND logic element AND1. The present signal input terminals 4 to 6 are respectively connected to three input terminals of the OR logic element OR2. The output of the OR logic element OR1 is connected to one input terminal of the AND logic element AND2, and the terminal ENABLE is connected to the other input terminal of the AND logic element AND2. The output of the AND logic element AND1 is connected to the first input terminal of the AND logic element AND3, and the output of the OR logic element OR2 is connected to the second input terminal of the AND logic element AND3. The terminal ENABLE is connected to the third input terminal of the AND logic element AND3.

In the server according to the second embodiment, when the server is activated, a high-level enable signal is transmitted from the control board 100 to the power supply control circuit 500 via the GPIO 300. Further, the present signal of the DIMM 220, Presents 1 to 6 are supplied from the system board 200 to the power supply control circuit 500. The present signal, Present 1 to 6 corresponds to each of the above six DIMMs 220. Among the six present signals, Presents 1 to 6, the level of the signal corresponding to what is actually mounted on the system board 200 among the six DIMMs 220 becomes high. For example, when only one first DIMM among the six DIMMs 220 is actually mounted on the system board 200, only the present signal, Present 1, becomes high level. During that time, the present signals, Presents 2-6 are all at a low level. On the other hand, for example, when a total of three first to third DIMMs are actually mounted on the system board 200, each of the present signals and Presents 1 to 3 is at a high level. Meanwhile, each of present signals and presents 4 to 6 are at a low level. When the first to sixth DIMMs, that is, all the DIMMs are actually mounted on the system board 200, the present signal and all of Presents 1 to 6 become high level. The present signals, Present 1 to 6 are generated by the present signal generation circuit 280 as described below.

In order to generate present signals, Presents 1 to 6, as shown in FIG. 9, a pair of present signal terminals TX1 and TX2 are provided in advance in each of the six DIMMs 220. The present signal terminals TX1 and TX2 are short-circuited, for example, as shown in FIG. As described above, the system board 200 on which the six DIMMs 220 are mounted is provided with a total of six slots (not shown) corresponding to the six DIMMs 220. Each of the slots is also provided with a pair of present signal terminals corresponding to the present signal terminals TX1 and TX2 of the DIMM 220.

The system board 200 is provided with the present signal generation circuit 280 having a configuration as shown in FIG. The present signal generation circuit 280 includes six short-circuit detection circuits 281 to 286. Each of the short-circuit detection circuits 281 to 286 transmits a high-level present signal when a short-circuit state between input terminals is detected, and transmits a low-level present signal when an open state between input terminals is detected. .

The present signal generation circuit 280 has a total of six pairs of present signal terminals TY1 to TY6 corresponding to the present signal terminals TX1 and TX2 of the six DIMMs 220, respectively. Each of the six pairs of present signal terminals TY1 to TY6 is connected to a pair of present signal terminals corresponding to the present signal terminals TX1 and TX2 of the corresponding DIMM 220 in the system board 200. As a result, when the DIMM 220 is inserted into the slot of the system board 200, the present signal terminals TX1 and TX2 of the DIMM 220 are electrically connected to the corresponding pair of terminals among the six pairs of present signal terminals TY1 to TY6. Connected to. The six pairs of present signal terminals TY1 to TY6 of the present signal generation circuit 280 are connected to the input terminals of the corresponding six short-circuit detection circuits 281 to 286, respectively. The six short circuit detection circuits 281 to 286 output the present signals and presents 1 to 6 from the output terminals Present 1 to 6 of the present signal generation circuit 280, respectively. Therefore, when the DIMM 220 is installed in the slot of the system board 200, the present signal generation circuit 280 causes the input terminal of the corresponding short circuit detection circuit to be in a short circuit state and outputs a high level. As a result, the present signal corresponding to the DIMM 220 related to the mounting becomes a high level. On the other hand, for each of the slots on the system board 200 where the DIMM 220 is not mounted, the present signal generation circuit 280 releases the corresponding short-circuit detection circuit input terminal and outputs a low level. As a result, the present signal corresponding to the slot in which the DIMM 220 is not mounted becomes a low level.

The operation of the present signal generation circuit 280 having the above configuration will be described with a specific example. For example, it is assumed that the first DIMM 220 is installed in the first slot among the six slots of the system board. In this case, the present signal terminals TX1 and TX2 of the DIMM 220 are electrically connected to the corresponding pair of present signal terminals TY1. As described above with reference to FIG. 9, the present signal terminals TX1 and TX2 provided in the DIMM 220 are short-circuited. Therefore, in this case, in the present signal generation circuit 280, the corresponding pair of present signal terminals TY1 is short-circuited. In the present signal generation circuit 280, the short circuit detection circuit 281 corresponding to the first DIMM 220 detects a short circuit of the present signal terminal TY1 and outputs a high level. As a result, the level of the present signal, Present 1, becomes high.

Similarly, when the second DIMM 220 is installed in the second slot of the system board 200, the present signal generation circuit 280 enters a state where the corresponding pair of present signal terminals TY2 are short-circuited. In the present signal generation circuit 280, the short circuit detection circuit 282 corresponding to the second DIMM 220 detects a short circuit of the present signal terminal TY2 and outputs a high level. As a result, the level of the present signal, Present 2, becomes high. Similarly, when DIMMs 220 between n (n is one of 3 to 6) are installed in the n-th slot of the system board 200, the present signal generation circuit 280 makes a pair of corresponding present signal terminals TYn. Is short-circuited. In the present signal generation circuit 280, the short circuit detection circuit 28n corresponding to the nth DIMM 220 detects a short circuit of the present signal terminal TYn and outputs a high level. As a result, the level of the present signal, Present n becomes high.

Next, the operation of the power supply control circuit 500 shown in FIG. 8 will be described. Here, as an example, it is assumed that at least one of the three first to third DIMMs among the six DIMMs 220 is installed in the first to third slots of the system board 200. In this case, as described above, at least one of the present signals and presents 1 to 3 corresponding to the present signal becomes high level. As a result, the output of the OR logic element OR1 of the power supply control circuit 500 becomes high level. Also, here, it is assumed that the server is activated, and as a result, the high level enable signal ENABLE is transmitted from the control board 100 via the GPIO 300 as described above. As a result, the terminal ENABLE becomes high level. As a result, both inputs of the AND logic element AND2 become high level, and the output of the AND logic element AND2 becomes high level. As a result, the enable signal A becomes high level. As a result, the power supply device 410 is operated by the enable signal A. As a result, the power supply apparatus 410 supplies power to at least one DIMM 220 among the first to third DIMMs mounted on the system board 200.

On the other hand, since none of the fourth to sixth DIMMs 220 is installed in the fourth to sixth slots, the corresponding present signals, Present 4 to 6 are all at the low level. As a result, the output of the OR logic element OR2 becomes low level. As a result, the second input of the AND logic element AND3 becomes low, and the output B of the AND logic element AND3 becomes low level. As a result, the enable signal B becomes low level, and the power supply apparatus 420 is not operated. Therefore, if at least one of the first to third DIMMs is installed in at least one of the corresponding first to third slots, and no DIMM is installed in the other slots, It becomes as follows. That is, only the power supply device 410 is operated, and the power supply device 420 is not operated. As a result, power is supplied to at least one of the first to third DIMMs by only one power supply device 410. When the number of DIMMs mounted on the system board 200 is 1 or more and 3 or less in this way, only one power supply device 410 is operated, and power is supplied to the mounted DIMM 220 by the power supply device 410. The

Next, all of the first to third DIMMs are installed in the corresponding slots of the first to third system boards 200, and at least one of the fourth to sixth DIMMs is mounted on the system board 200. Assume that the slot is installed in the corresponding slot among the fourth to sixth slots. In this case, as described above, the present signals, Presents 1 to 3 are all at a high level, and at least one of the present signals and Presents 4 to 6 is at a high level. In that case, the output of the OR logic element OR1 of the power supply control circuit 500 becomes high level. Further, it is assumed that the server is activated as described above, and as a result, the high level enable signal ENABLE is transmitted from the control board 100 via the GPIO 300 as described above. As a result, the terminal ENABLE goes high. As a result, both inputs of the AND logic element AND2 become high level, and the output of the AND logic element AND2 becomes high level. As a result, the enable signal A becomes high level, and the power supply device 410 is operated.

Further, in this case, as described above, at least one of the 4th to 6th DIMMs is mounted in the corresponding slot in the 4th to 6th slots of the system board 200. In this case, as described above, at least one of the present signals and presents 4 to 6 falls to a high level. In that case, the output of the OR logic element OR2 of the power supply control circuit 500 becomes high level. Here, as described above, the high level enable signal ENABLE is transmitted from the control board 100 via the GPIO 300, and the terminal ENABLE is high. Since the present signals, Present 1 to 3 are all at the high level as described above, the output of the AND logic element AND1 is at the high level. As a result, all the first to third inputs of the AND logic element AND3 become high level, and the output of the AND logic element AND2 becomes high level. As a result, the enable signal B also goes high, and the power supply device 420 is also operated. In this way, when all the first to third DIMMs and at least one of the fourth to sixth DIMMs are installed in the corresponding slots of the system board 200, the following occurs. That is, both the enable signals A and B are at a high level, and as a result, both of the corresponding two

power supply devices

410 and 420 are operated. Therefore, when four or more DIMMs in total such as all of the first to third DIMMs and at least one of the fourth to sixth DIMMs are mounted on the system board 200 as follows, Become. That is, the two

power supply devices

410 and 420 are operated, and power is supplied to the DIMM 220 by the two

power supply devices

410 and 420.

As described above, according to the second embodiment, when the number of DIMMs mounted on the system board 200 is 1 or more and 3 or less, only one power supply device 410 is operated, and the power supply device 410 supplies power to the mounted DIMMs. Is supplied. On the other hand, when the number of DIMMs mounted on the system board 200 is 4 or more and 6 or less, the two

power supply devices

410 and 420 are operated, and power is supplied to the mounted DIMMs by the

power supply devices

410 and 420. . That is, when the number of DIMMs that supply power is small, power is supplied by a small number of power supply devices, and when the number of DIMMs that supply power is large, power is supplied by a large number of power supply devices. As a result, as described above with reference to FIG. 1, it is possible to effectively improve the operation efficiency of each power supply apparatus.

In the description of each of the first and second embodiments, the case where the number of power supply devices is two has been described. However, the present invention is not limited to such a case. That is, it goes without saying that each embodiment can be applied even when power is supplied to one or a plurality of DIMMs using three or more power supply devices. In that case, the number of the three or more power supply devices that are actually operated may be increased when the number of DIMMs actually mounted or the total power consumption is large, and may be controlled when the number is small.

Claims

One or a plurality of storage devices, wherein the number of the one or more storage devices is changeable, and
A computing device that performs information processing using the one or more storage devices;
A plurality of power supply devices for supplying power to the one or more storage devices;
Means for detecting the number of the one or more storage devices;
Means for determining the number of power supply devices to be actually operated among the plurality of power supply devices according to the detected number of one or more storage devices.
Information about the storage device is stored in advance in each of the one or more storage devices,
The means for detecting the number of the one or more storage devices reads from the one or more storage devices information related to the storage device stored in advance in each of the one or more storage devices;
The information processing apparatus according to claim 1, further comprising: a unit that determines the number of the one or more storage devices based on the read information about each storage device.
And a means for determining the power consumption of each of the one or more storage devices based on the read information about each storage device.
The means for controlling the number of power supply devices actually operated is based on the determined number of the one or more storage devices and the power consumption of each of the determined one or more storage devices. The information processing device according to claim 2, wherein the number of power supply devices to be operated is determined.
The means for detecting the number of the one or more storage devices includes means for detecting whether or not the storage device is attached to the information processing device for each of the one or more storage devices,
The means for determining the number of power supply devices to be actually operated has means for determining the number of power supply devices to be actually operated based on whether or not each detected storage device is attached to the information processing device. The information processing apparatus according to claim 1.
One or a plurality of storage devices, wherein the number of the one or more storage devices is changeable, and
A computing device that performs information processing using the one or more storage devices;
In an information processing apparatus having a plurality of power supply devices that supply power to the one or a plurality of storage devices, a power control method for controlling operations of the plurality of power supply devices,
Detecting the number of the one or more storage devices;
Determining the number of power supply devices to be actually operated among the plurality of power supply devices according to the detected number of one or more storage devices.
Information about the storage device is stored in advance in each of the one or more storage devices,
In the step of detecting the number of the one or more storage devices, a step of reading information on the storage device stored in advance in each of the one or more storage devices from the one or more storage devices;
The power supply control method according to claim 5, further comprising: determining the number of the one or more storage devices based on the read information about each storage device.
And determining power consumption of each of the one or more storage devices based on the read information about each storage device.
In the step of determining the number of power supply devices to be actually operated, based on the determined number of one or more storage devices and the power consumption of each of the determined one or more storage devices, The power supply control method according to claim 6, wherein the number of power supply devices to be operated is determined.
One or a plurality of storage devices, wherein the number of the one or more storage devices is changeable, and
A computing device that performs information processing using the one or more storage devices;
And a plurality of power supply devices that supply power to the one or more storage devices. A computer for controlling operations of the plurality of power supply devices detects the number of the one or more storage devices. Means,
A power supply control program for functioning as means for determining the number of power supply devices to be actually operated among the plurality of power supply devices according to the detected number of one or more storage devices.
Information about the storage device is stored in advance in each of the one or more storage devices,
The means for detecting the number of the one or more storage devices reads from the one or more storage devices information related to the storage device stored in advance in each of the one or more storage devices;
The power supply control program according to claim 8, further comprising: a unit that determines the number of the one or more storage devices based on the read information regarding each storage device.
Furthermore, a power supply control program for causing the computer to function as means for determining the power required for each of the one or a plurality of storage devices based on the read information about each storage device,
The means for determining the number of power supply devices to be actually operated is based on the determined number of one or more storage devices and the power consumption of each of the determined one or more storage devices. The power supply control program according to claim 9, further comprising a unit that determines the number of power supply devices to be operated.