WO2010034995A1 - Method and apparatus for forming an interconnection through a substrate - Google Patents

Method and apparatus for forming an interconnection through a substrate Download PDF

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Publication number
WO2010034995A1
WO2010034995A1 PCT/GB2009/002277 GB2009002277W WO2010034995A1 WO 2010034995 A1 WO2010034995 A1 WO 2010034995A1 GB 2009002277 W GB2009002277 W GB 2009002277W WO 2010034995 A1 WO2010034995 A1 WO 2010034995A1
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WIPO (PCT)
Prior art keywords
arrangement
substrate
connecting material
solder
die
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PCT/GB2009/002277
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French (fr)
Inventor
Jiebin Gu
William Thomas Pike
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Imperial Innovations Limited
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Publication of WO2010034995A1 publication Critical patent/WO2010034995A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13009Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/9202Forming additional connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Definitions

  • This invention relates to a method and apparatus for forming an interconnection through a substrate. It is particularly suitable, but by no means limited, for use in wafer level packaging, for example to form a through- wafer interconnection in micro-electro-mechanical systems.
  • TWI through-silicon via
  • MEMS micro-electro-mechanical systems
  • ICs integrated circuits
  • TWI/TSV The fabrication of known TWI/TSV involves at least some of the following techniques: via fabrication, isolation, deposition of diffusion barrier and adhesion layers, metallization, via filling, wafer thinning, dicing, alignment and bonding.
  • the metallization of the sidewall of the via involves physical vapour deposition (PVD) or chemical vapour deposition (CVD).
  • PVD physical vapour deposition
  • CVD chemical vapour deposition
  • electroplating is used to fill the vias. As electroplating is a damascene process, it can take hours to fully fill a via hole.
  • tight control of all of the chemical additives during the electroplating process is critical and costly [1-8].
  • Other TWI/TSV techniques specify the use of specific, non-standard silicon wafers, such as low resistivity, high resistivity, or even glass wafers [9-11].
  • two main TWI/TSV techniques have been developed, as follows:
  • TWV through- wafer via
  • DRIE deep reactive-ion etching
  • CVD chemical vapour deposition
  • electroplating followed by patterning and etching [1, 2, 3].
  • the second technique is named "Silex Via" and was developed by Silex Microsystems Ltd.
  • the technique behind Silex Via is the use of low resistivity through-wafer silicon pillars that are fabricated by DRIE to serve as a conductive medium [12].
  • the trenches between the pillars and the main wafer body are then filled with dielectric materials for electrical isolation, followed by thin etching, metal deposition and patterning.
  • a method of forming an interconnection through a substrate comprising the steps of: forming a first via through the substrate; providing a second via in communication with the first via; introducing connecting material into at least the second via; causing the connecting material to flow, in liquid form, from the second via to the first via under the effect of a pressure differential; and solidifying the connecting material in the first via, thereby forming an interconnection through the substrate.
  • connection should be interpreted broadly, to encompass an electrical interconnection through the substrate, or a thermal interconnection, or an interconnection for mechanical joining purposes.
  • substrate as used herein should be interpreted broadly, to encompass any wafer or die material capable of being used with the process described herein.
  • via as used herein should be interpreted broadly, to encompass a through- hole through the wafer or other substrate material.
  • connecting material should be interpreted as any material suitable for providing a interconnection through the substrate material used.
  • the connecting material may be conductive (e.g. a conductive solder) or non-conductive.
  • the second via has a diameter less than that of the first via. This difference in via diameters enables the surface tension force of the liquid connecting material (e.g. molten solder) to be exploited, to
  • This technique may be used to form a TWI in the first via without the need for prior deposition of metal on the internal wall of the via (as is the case with TWV) - thereby avoiding geometrical constraint problems - and without using interconnecting silicon (as is the case with Silex Via).
  • the second via may also be formed through the substrate.
  • the second via may be formed through a base die.
  • the substrate and the base die are preferably positioned such that the first and second vias are axially aligned. This allows the forming of fewer vias in the substrate, and multiple first vias to be arranged in a reduced pitch array (i.e. more closely positioned relative to one another).
  • a support die may be provided beneath the base die to hold connecting material in the second via prior to flowing.
  • the support die may comprise a vent hole to prevent air pressure dropping in the second via hole during the melting of the reflow.
  • the first via may be through-plated with a material wettable by the connecting material when in liquid form.
  • a material wettable by the connecting material when in liquid form.
  • This technique may be used to form a TWI in the first via, and also allows the first via to have a diameter less than that of the second via. This reduces the volume of connecting material required.
  • the method further comprises providing a path from the second via to the first via, along which liquid connecting material may flow.
  • the said path is formed between the substrate and a base die.
  • the method may further comprise providing one or more spacers 5 between the substrate and the base die.
  • the said path may incorporate a channel within the base die.
  • the method may further comprise providing one or more metal pads along the0 said path, the metal pads being situated on the substrate, the base die, or opposingly on both the substrate and the base die.
  • Such pads may be wetted by the liquid connecting material, and therefore aid in defining the flow path for the liquid between the first and second vias. Due to the wetting of the pads, this may also facilitate forming an electrical interconnection and/or an5 increased physical bonding effect between the connecting material and the substrate and/or base die - particularly when a solder connecting material is used in conjunction with a silicon substrate, since silicon is not ordinarily wetted by molten solder.
  • the method may further comprise forming an isolating layer (e.g. an electrically-isolating oxide layer, or some other dielectric layer) on the surface of the substrate, after the formation of the first via, and prior to the introduction of the connecting material. This provides isolation (e.g. electrical isolation) between the connecting material and the substrate.
  • an isolating layer e.g. an electrically-isolating oxide layer, or some other dielectric layer
  • the method may further comprise forming an isolating layer on the surface of the base die, prior to the introduction of the connecting material.
  • the step of introducing connecting material comprises introducing connecting material into both the first and second vias.
  • Connecting material may also be introduced into a said channel, if one is present.
  • the second via may be formed within a base die.
  • the second via may be substantially within the plane of the base die.
  • the second via may be one of a plurality of such vias in communication with the first via. In this manner, a relatively large quantity of connecting material may be supplied from the plurality of second vias to the first via.
  • a metal pad may be provided on a surface of the said substrate around the outlet of the first via. This metal pad may be wetted by the connecting material (when molten) in order to provide additional electrical, physical and thermal interconnection.
  • the method may comprise causing the connecting material to flow to such an extent that, when solidified, it protrudes out of the first via. If this is performed in a plurality of locations on the substrate, substantially simultaneously, an array of protrusions of connecting material may be formed.
  • This technique is attractive for use with surface mounting technology (SMT), as an array of such protrusions may be used to form the balls of a ball grid array (BGA) in a single operation, without the need to attach additional balls to form the BGA.
  • SMT surface mounting technology
  • the connecting material is introduced as solid material, and the step of causing the joining material to flow comprises melting the connecting material.
  • the connecting material is solder.
  • Particularly preferably is introduced in the form of solder balls.
  • the solder may alternatively be introduced by any suitable deposition method, such as solderjet (RTM), electroplating, wave soldering, etc.
  • the solder may be an alloy of tin/lead, or tin/silver, or may be a lead-free solder, as those skilled in the art will appreciate.
  • the substrate may be silicon-based, and may be a wafer.
  • the method may include aligning the substrate and a base die using a means of alignment. For example, pins or supports may be inserted through alignment holes in the substrate and base die, or the substrate and base die may be located within a frame. Alternative alignment techniques will be readily apparent to those skilled in the art of device fabrication.
  • an arrangement comprising: a substrate having a first via therethrough; a base die; and a second via in either the substrate or the base die, the second via being in communication with the first via, such that liquid connecting material may flow from the second via to the first via under the effect of a pressure differential.
  • connecting material has yet to be flowed into the first via, then there may be as-received connecting material in at least the second via, and possibly in the first via, and also in the said channel, if one is present.
  • Solidified connecting material may protrude out of the first via. This may be reproduced in a plurality of locations on the substrate so as to form an array of protrusions of connecting material, for example for use as a ball grid array.
  • Figure IA is a three-dimensional illustration of a first embodiment of a so-called "solder pump", with solder balls placed in the target and feed vias within a cap silicon die, ready for reflow;
  • Figure IB is a cross-section schematic of the embodiment of Figure IA (note that the device has been rotated through 180° about a vertical axis when going from Figure IA to Figure IB), illustrating the use of opposing upper and lower metal pads on either side of the path along which molten solder will flow once melted;
  • Figure 2 illustrates a second embodiment of a solder pump, having opposing metal pads and isolating layers of silicon dioxide on the silicon substrates;
  • Figure 2A illustrates a variation of the embodiment of Figure 2 wherein the metal pads only surround the target via;
  • Figures 2B illustrates a variation of the embodiment of Figure 2 wherein a U- shaped flow configuration is employed together with multiple feed vias that are each narrower than the target via;
  • Figure 2C illustrates the solder, once re-solidified, of the solder pump of Figure 2B;
  • Figure 3 illustrates a third embodiment of a solder pump, having an upper metal pad and an isolating layer of silicon dioxide on the upper silicon substrate, and a channel formed in the lower substrate;
  • Figure 4 illustrates a fourth embodiment of a solder pump having a lower metal pad and isolating layers of silicon dioxide on the silicon substrates;
  • Figure 5 illustrates a fifth embodiment of a solder pump in which the feed via is within the base die
  • Figure 6A illustrates a sixth embodiment of a solder pump in which the target via is formed in the upper silicon substrate (which has an isolating layer of silicon dioxide) and the feed via is formed in the lower silicon substrate, and where the substrates are mounted upon a support die, and the vias are aligned axially and vertically;
  • Figure 6B illustrates the solder, once re-solidified, of the solder pump of Figure
  • Figure 6C illustrates a variation of the embodiment of Figure 6A wherein a vent hole is present in the support die
  • Figure 6D illustrates a variation of the embodiment of Figure 6A wherein the feed via has a sloped or tapered wall profile
  • Figure 6E illustrates a variation of the embodiment of Figure 6A wherein the feed via has a stepped wall profile (as shown, the lower die could be one die or formed by two dies);
  • Figure 6F illustrates a variation of the embodiment of Figure 6A wherein two feed vias are present in the lower die, the two feed vias being connected by a connection die;
  • Figures 6G, 6H and 61 illustrate the molten solder flow mechanism of the solder pump of Figure 6F;
  • Figure 6J illustrates the solder, once re-solidified, of the solder pump of Figure
  • Figure 7A illustrates a seventh embodiment of a solder pump having an arrangement similar to the embodiment of Figure 2 wherein the target via is through-plated and is narrower than the feed via;
  • Figure 7B illustrates the solder, once re-solidified, of the solder pump of Figure
  • Figure 8 A illustrates an eighth embodiment of a solder pump having a axial vertical arrangement of the target and feed vias wherein the target via is narrower than the feed via;
  • Figure 8B illustrates the solder, once re-solidified, of the solder pump of Figure
  • Figure 9 illustrates a general method of fabricating silicon substrates for the solder pump embodiments of Figures 1 to 4;
  • FIG. 10 illustrates the solder flow mechanism of the embodiment of Figures
  • Figure 11 illustrates the solder flow mechanism of the embodiment of Figures 7A and 7B;
  • Figure 12 illustrates various parameters for modelling the operation of a solder pump
  • Figure 13 illustrates a simulation of solder flow and the shape of molten solder before, during and after reflow of the solder material
  • Figure 14 illustrates a simulation of a failure of the solder pump due to insufficient load on the upper substrate
  • Figure 15 illustrates the forces acting on the upper substrate during reflow
  • Figures 16A-N show scanning electron microscope micrographs of solder pump prototypes after the solder has solidified;
  • Figure 17 shows the capillary pressure in molten solder within a via, for different via diameters;
  • Figure 18 shows two applications of TWI/TSV produced by the solder pump system, namely 3D stacked-dies and wafer-level packaging.
  • solder pump By way of an initial introduction, the present embodiments are variants of what we have termed a "solder pump".
  • Our solder pump concept causes molten solder to flow into a "target" via in a substrate, and this may be used to form an interconnection through the target via.
  • the interconnection so formed may be an electrical interconnection, or a thermal interconnection, or for mechanical joining purposes.
  • Solid solder for example in the form of solder balls, is introduced in a "feed" via, which is preferably formed in the same substrate as the target via.
  • the feed via is in communication with the target via by way of a path.
  • solid solder is introduced in the target via as well as the feed via.
  • the solder is then melted, upon which it then flows, under the effect of a pressure differential, from the feed via and into the target via, so as to fill the target via.
  • the pressure differential may be one which arises automatically, through capillary and surface tension effects, as a result of the feed via being of a smaller diameter than the target via.
  • the pressure differential may arise due to differing surface energies of the molten solder in the target and feed vias.
  • the differing surface energies are as a result of the target via being additionally through-plated and hence wettable by the molten solder. With the through-plating, the target via may be a smaller diameter than the feed via.
  • solder is then solidified.
  • the solidified solder in the target via provides an interconnection through the substrate.
  • the substrate may be a silicon wafer, and thus the present embodiments provide a way of forming through-wafer interconnections.
  • the invention is more broadly applicable than to just molten solder and silicon wafers.
  • other connecting materials and other substrate materials may also be used.
  • FIG. IA and IB a cross-section schematic of a first embodiment of a solder pump structure 10 is illustrated.
  • the structure comprises two substrates, in this case a cap silicon die 11 and a base silicon die 12.
  • a pair of through- wafer holes or vias 13 and 14 have been formed through the cap silicon die 11, for example by deep reactive-ion etching (DRIE).
  • the vias 13, 14 have different diameters.
  • the diameter of the so-called "target" via 14 (which may be considered a 'first' via) is greater than that of the so-called "feed” via 13 (which may be considered a 'second' via).
  • Solder balls 15 are placed within at least the feed via 13, and preferably within both the target and feed vias, as illustrated.
  • the solder balls 15 may be formed from a standard solder composition of a tin/silver or tin/lead alloy, or any other suitable material, such as lead-free solder compositions.
  • Underlay 19 provides a degree of separation between the cap die 11 and the base die 12, so as to form a flow path 18 from the feed via 13 to the target via 14.
  • Upper metal pads 16 are positioned on the cap silicon die 11 , and an opposing lower metal pad 17 is positioned on the base silicon die 12, on either side of the path 18. These pads are wettable by molten solder, and thus serve to define the flow path 18 from the feed via 13 to the target via 14. Once molten, solder is able to flow during along the path 18, from the feed via 13 to the target via 14. This is of benefit since silicon and silicon dioxide are not wetted by molten solder, and so the flow of molten solder would not be so predictable without the metal pads. Due to the wetting of the pads, this may also facilitate forming an electrical interconnection and/or an increased physical bonding effect between the solder and the cap die 11 and/or base die 12, and may additionally provide hermetic sealing.
  • the dies 11, 12 may be isolated from the connecting material by forming an isolating coating on the surfaces of the dies. As illustrated in Figures 2 to 8, this may be achieved by forming a silicon dioxide layer on the surface of at least one of the silicon dies by oxidation.
  • the isolation layer can also be formed by depositing any suitable dielectric material, such as silicon dioxide or silicon nitride.
  • the upper metal pad 16 may surround only the target via 14, and not the feed via 13. This promotes the eventual reflow of the molten solder balls from the feed via to the target via.
  • the feed vias 13 are narrower than the target via 14 (as per Figures IA, IB, 2, 2A, 2B, 2C and 4).
  • the placing of solder balls in the target via 14 may be omitted, as the feed vias 13 provide sufficient molten solder under reflow to fill the target via 14 and produce the desired electrical and/or physical bonding effect, as illustrated in Figure 2C.
  • solder-pump structure is shown in Figures 3 to 8.
  • the metal pad 16 is positioned on the cap silicon die 11, without there being an opposing lower metal pad.
  • the flow path 18 comprises an additional channel 31 in the base silicon die 12. Solid solder balls 15 are placed within this channel 31, as well as in the feed via 13 and the target via 14.
  • the metal pad 17 is placed on the base silicon die 12, and there is no opposing upper metal pad.
  • the flow path 18 is bordered on one side by a metal pad and on another side by a silicon die (which may or may not be formed with an isolating layer). This is possible since a single pad is sufficient to provide a wettable surface and thereby define the flow path 18.
  • the use of a single metal pad also allows the cap silicon die 11 and the base silicon die 12 to be separated more easily after the solder has flowed and solidified. This is because the solder, once solid, only bonds to the side of the path 18 that comprises a metal pad. Additionally, the fabrication process is simpler when metal deposition is only required on one of the substrate dies.
  • the feed via 13 may be angled (rather than being perpendicularly through the die 11) such that an increased volume of solder balls may be positioned within the feed via prior to reflow.
  • the feed via 13 may be positioned entirely within the base silicon die 12, allowing a simpler construction of the solder pump system with fewer vias required in the cap silicon die 11.
  • the feed via 13 may be positioned horizontally, such that it is not exposed to the surrounding atmosphere.
  • Figure 6 A shows an embodiment where the target via 14 is formed in the cap silicon die 11 and the feed via 13 is formed in the base silicon die 12.
  • the dies are positioned such that the target and feed vias are aligned axially and vertically.
  • Underlay 19 may optionally be employed in order to provide a degree of separation between the cap and base dies.
  • Metal pads 16 are positioned on the cap silicon die 11 surrounding the target via 14.
  • Solder balls 15 are positioned within at least the feed via 13, and preferably both the target and feed vias, as illustrated.
  • An additional silicon die 73 is positioned below the base silicon die 12 in order to retain the solder balls 15 in the feed via 13. Once molten, solder is able to flow from the feed via 13 to the target via 14 until it reaches the configuration shown in Figure 6B.
  • a solder bump capping 94 may protrude from the outer surfaces of the cap silicon die 11.
  • the cap silicon die 11 and the base silicon die 12 may be separated more easily after the solder has flowed and solidified. This is because, in this arrangement, there are no metal pads (equivalent to feature 17 of Figures IA, IB, 2 and 3) that cause the solidified solder to physically bond the cap silicon die 11 to the base silicon die 12.
  • FIG. 6C An alternative arrangement is shown in Figure 6C.
  • an additional silicon die 73 positioned below the base silicon die 12, is provided with a through hole 74 as shown.
  • the hole is axially and vertically aligned with the target and feed vias, and is suitably dimensioned such that solder balls 15 are supported in the feed via 13 during initial placement. Gas can thereby vent into the feed via 13 from through hole 74 during the reflow, and so prevent a low pressure developing in the feed via 13 underneath the molten solder as the molten solder is pumped up.
  • Figures 6D and 6E show yet further embodiments where the target via 14 and the feed via 13 are aligned axially and vertically.
  • FIG. 6D comprises sloped or tapered sidewalls in the feed via 13, and the embodiment of Figure 6E has a stepped configuration of the feed via 13.
  • the slope ( Figure 6D) or stepped configuration ( Figure 16E) is arranged such that the diameter of the feed via 13 increases in a direction towards the target via 14. This causes a pressure differential to act on the solder, when molten, in the direction of the target via 14, resulting in the final
  • the feed via 13 is dimensioned such that the solder balls 15 required for the solder pump effect need only be placed within the feed via prior to reflow.
  • the base die 12 to be prepared and solder balls placed within the feed via(s) 13 independently of the cap die 11. Therefore, the geometric structure of the cap die 11 does not influence solder ball placement.
  • the cap die 11 may be a target device on a printed circuit board. The device, therefore, may be excluded from involvement in the solder ball placement. This simplifies printed circuit board manufacture and preparation, and reduces the exposure to manufacturing processes that the devices must withstand.
  • a feed via 13 having a stepped sidewall may be formed using a base die 12 and an additional die 20, the interface between the two providing a step in the diameter of the feed via 13.
  • this can result in the base die 12 and the additional die 20 being reduced in thickness (in comparison to an alternative in which the step is formed in a single die, for example by appropriate drilling of axially aligned holes of different diameters).
  • the tapered or sloped sidewall of the feed via 13 of the embodiment of Figure 6D is preferably fabricated from a single base die 12.
  • Providing an accurate taper or slope may require deep DRIE (for example up to lOOO ⁇ m).
  • the angle of the taper or slope may be about 1°.
  • FIG. 6F this illustrates yet another variation on the vertical arrangement.
  • two feed vias 13 A, 13B are provided in the base die 12, the first feed via 13 A being in axial and vertical alignment with the target via 14 in the cap die 11, and the second feed via 13B being situated alongside the first.
  • a connection die 75 provides a linking passage or trench 76 to allow molten solder to flow from the second feed via 13B to the first feed via 13 A.
  • the diameter of the second feed via 13B is less than that of the first feed via 13 A, which in turn has a diameter less than that of the target via 14.
  • solder is able to flow from the second feed via 13B, through the linking passage or trench 76 and the first feed via 13 A, to the target via 14, as shown in Figures 6G to 61, until it reaches the configuration shown in Figure 6 J.
  • a solder bump capping 94 may protrude from the outer surfaces of the cap silicon die 11.
  • the pressure differential between the feed and target vias may also arise due to differing surface energies of the molten solder in the target and feed vias.
  • This differing surface energy results from the target via being through-plated and hence wettable by the molten solder.
  • the feed via is not plated, and hence is not wettable by the molten solder. This technique is employed in the embodiments of Figures 7A-B and 8A-B.
  • the silicon dies are arranged in a manner similar to the embodiment of Figure 2, except that the target via 14 is through- plated 71 and has a smaller diameter than the feed via 13.
  • the overall volume of the vias is reduced.
  • the flow path 18 is defined by the upper metal pads 16 and lower metal pads 17 as in the embodiment of Figure 2.
  • solder balls 15 need only be positioned in the feed via 13 prior to reflow, as a consequence of the decreased overall volume of the vias.
  • the target via 14 provides a bonding effect between the cap silicon die 11 and the base silicon die 12 by virtue of the lower metal pads 17 and the optional upper metal pads 16.
  • Figure 8A shows a further embodiment where, similarly to the embodiment of Figure 6A, the target via 14 is formed in the cap silicon die 11 and the feed via 13 is formed in the base silicon die 12.
  • the dies are positioned such that the target and feed vias are vertically and axially aligned.
  • Metal pads 16 are positioned on the cap die 11 around the target via 14.
  • Target via 14 is through- plated (71) and of a smaller diameter than the feed via 13. This allows the overall size of the vias to be reduced which, in-turn, would allow multiple target vias to be arranged in a reduced pitch array (i.e. more closely positioned relative to one another).
  • Underlay (not shown) may be employed to provide a degree of separation between the cap silicon die 11 and the base silicon die 12.
  • solder balls 15 need only be positioned in the feed via 13 prior to reflow.
  • the narrower target via 14 retains the solder balls 15 in the feed via 13 prior to reflow (and hence no additional die 73 is required).
  • solder is able to flow from the feed via 13 to the target via 14 until it reaches the configuration shown in Figure 8B.
  • a solder bump capping 94 may protrude from the surfaces of the cap silicon die 11.
  • the base silicon die 12 and the cap silicon die 11 may then be separated. This is due to there being no metal pads on the base silicon die that would provide a physical bonding effect with the solidified solder.
  • optional metal pads 72 may be positioned on the exterior surface of the cap die 11, around the outlet of the target via 14, as shown in Figures 6 to 8. This may enhance the electrical interconnection, increase physical bonding, and also provide hermetic sealing.
  • Figure 9 illustrates a general method of fabricating the silicon dies (silicon substrates) for a two-substrate solder pump system (e.g. as shown in Figures 1 to 4).
  • the steps will individually be familiar to those skilled in the art and so will only be described at a high level here, to illustrate their order of execution during the fabrication process, rather than to provide precise details. It will be apparent to those skilled in the art that these steps may easily be adapted in order to fabricate silicon dies for use with any of the embodiments of the solder-pump system disclosed herein.
  • step 51 pieces of silicon wafer of suitable dimensions for the cap silicon die 11 are obtained, and target via 14 (a first via of a first radius) and feed via 13 (a second via of a smaller second radius) are created in step 52, for example by deep reactive-ion etching.
  • target via 14 a first via of a first radius
  • feed via 13 a second via of a smaller second radius
  • step 53 a silicon dioxide or other oxide layer
  • This may be done, for example, by exposing the silicon dies to oxygen, and heating as appropriate, or by depositing the silicon dioxide or other layer (e.g. silicon nitride) directly onto the silicon dies. This produces a cap silicon die having an isolating layer, as shown in the embodiments of Figures 2, 3 and 4.
  • step 55 the deposition process is performed in step 55, after an optional step 54 in which an additional silicon wafer die 50 is formed with vias of appropriate dimensions in order to provide a template for the metal pad deposition process.
  • This optional step 54 may be performed since the alternative well-known method of covering the metal to be retained with photo-resist prior to exposing to ultra-violet light, and then etching, would be very cumbersome for the small dimensions of metal pad desired.
  • step 56 the additional silicon wafer die 50 is removed, resulting in a cap silicon die 11 comprising metal pads 16 as per the embodiments of Figures IA-B, 2 and 3.
  • step 57 a layer of photoresist is added over the metal.
  • step 58 the photoresist is removed in positions where a metal pad is not ultimately required (according to the location of the vias 13, 14 in the cap silicon die 11).
  • step 59 the remaining photoresist is removed, rendering a base silicon die comprising a metal pad 17 of appropriate dimensions for the embodiments of Figures 1 A-B, 2 and 4.
  • the base silicon die 12 includes an additional flow channel 31 which may be created by adding photoresist over the base silicon die at step 61, and then removing the photoresist with ultraviolet light at step 62.
  • the channel is created at step 63 by a deep etching process.
  • the photoresist is removed at step 64 resulting in the base silicon die 12 of the embodiment of Figure 3.
  • solder pump system of Figures IA and IB which may be constructed in much the same manner, but without forming a coating of silicon dioxide (or another isolating coating) on the dies.
  • the various wafers are cut to the required thicknesses and, typically, DRIE would be performed to create the through holes that form the feed and target vias (13, 14), and also the vent hole 74 if applicable. Then, isolation with SiO 2 or the like takes place, as previously discussed, followed by metallisation of the metal pads.
  • Alignment of the cap silicon die 11 and the base silicon die 12 may be important for the solder-pump to perform efficiently.
  • One way of achieving this would be to form alignment holes at corresponding positions on the cap silicon die 11, base silicon die 12 and, if present, the support die 73 during
  • the gap between dies is approximately 50 ⁇ m which may be created by positioning underlay as discussed above, or placing thin metal foil spacers between the dies.
  • the ref ⁇ ow of solder balls 15 in the solder pump may be divided into two steps: (i) spreading and combination; and (ii) solder pumping from the feed via 13 to the target via 14.
  • Step (i) of the mechanism is triggered by reilow, where molten solder (following heating of the solder balls 15 to promote their coalescence) initially spreads (in a manner also known as 'wicking') along the metal pads 16 and 17. Eventually the molten solder from the feed via 13 and the target via 14 combines to form a contiguous volume of molten solder in the flow path 18 between the wettable metal pads, as shown in Figure 10. In step (U) 5 the solder is pumped from the feed via 13 to the target via 14.
  • Both silicon (as in the case of the cap silicon die of the embodiment of Figures IA and IB) and silicon dioxide (as in the case of the isolating coating of the embodiments of Figures 2 to 4) are non- wettable by solder, and so hemispherical surfaces 101 are formed both in the feed via 13 and the target via 14 during the pumping process, as shown in Figure 10.
  • the capillary pressure (in Pascals) generated with a spherical cap can be derived by
  • the driving pressure difference is given by
  • This pressure difference drives the solder from the feed via 14 to the target via 13, as indicated by the arrows 81 in Figure 10.
  • the transfer of solder ceases when the solder in the feed via 13 forms a cap whose pressure equals the pressure in the cap of the target via 14, i.e. when the two cap radii are substantially equal.
  • the solder in the target via provides an interconnection (e.g. TWI).
  • the hemispherical cap may protrude from the target via 14 and the surface of the cap die 11, as shown in Figures 16B to 16D.
  • the protruding hemispherical cap may be used as a ball of a BGA (if an array of similar target vias is provided in the die 11).
  • the final solder geometry is governed by surface-energy minimisation.
  • the final geometry of the solder is comprised of four volumes: (a) a solder cap 91 in the feed via 13; (b) a plate 92 within the flow path 18 (between the metal pads 16, 17); (c) a cylinder 93 inside the target via 13 (which serves as the conductive medium for TWI); and (d) a solder bump capping 94 on the target via 14 protruding from the outer surface 95 of the cap die 11.
  • the solder bump capping 94 on the target via 14 may be suitable for surface mounting.
  • Figure 17 illustrates the capillary pressure in molten solder within a via, for different via diameters.
  • the above solder pump effect could be achieved by any means capable of providing a pressure differential, such that the pressure in the feed via 13 is greater than the pressure in the target via 14.
  • a gas supply may be arranged to act upon the feed via, or a vacuum supply may be connected to the target via.
  • step (i) during reflow, the molten solder flows from the feed via 13 along metal pads 16 and 17.
  • step (ii) the solder is pumped from the feed via 13 to the target via 14.
  • the differing surface energies of the molten solder in the target and feed vias is as a result of the solder spreading to and wetting the through-plating 71 in the target via 14.
  • This wetting effect forms a concave meniscus 111 (which has a negative pressure) on the top of the molten solder in the target via 14.
  • the positive pressure of the molten solder in the feed via 13 (which is surrounded by unwettable silicon or an isolating compound such as silicon dioxide) therefore pumps molten solder from the feed via 13 to the target via 14 as indicated by arrows 81 in Figure 11.
  • the molten solder may fill the target via 14 to an extent that a hemispherical cap may protrude from the target via 14.
  • This cap may be suitable for use as a ball of a BGA (if an array of similar target vias is provided in the cap silicon die 11).
  • Figure 12 shows the geometric parameters of the solder pump structure of the embodiment of Figures IA-B and 2.
  • the pumping step during reflow of the molten solder balls was simulated by computer, for different conditions, to obtain the final shape of the solder, and the results are presented graphically in Figures 13 A to 13D.
  • the solder flows from the feed via 13 to the target via 14 and finally forms the shape shown in Figure 13D (corresponding to real-world examples shown in Figures 16A to 16D) when pressure equilibrium is reached in the molten solder.
  • the final shape of the solder comprises a bump 91 in the feed via 13; a plate 92 within the flow path 18 (between the metal pads 16, 17); a cylinder 93 inside the target via 13 (which serves as the conductive medium for TWI); and a solder bump capping 94 on the target via 14 protruding from the outer surface 95 of the cap die 11.
  • the solder bump capping 94 on the target via 14 may be suitable for surface mounting.
  • a first issue is the optimization of the stand-off height H gap .
  • the solder consumed in the flow path 18 between the metal pads 16 and 17 is preferably minimised; however, the stand-off height H gap also affects the flow rate of the molten solder.
  • a second issue is that of volume constraint.
  • the solder used is in the form of balls 15, and the total volume of the solder is therefore calculated as a multiple of the volume of a single solder ball.
  • multiple feed vias 12 may be required in order to provide a sufficient quantity of solder.
  • the number of feed vias required can be approximately calculated using the following formula:
  • R via and r sb are the radii of the target via 14 and a solder ball 15 respectively, andH w ⁇ r is the thickness of the cap silicon die 11.
  • a third issue is the lifting of the cap silicon die 11.
  • the surface tension and the pressure within the molten solder yield a lifting force on the upper die 11. This lifting force can result in the failure of the solder pump (as shown in Figure 14) due to lifting of the die 11, which results in the flow path 18 becoming too wide.
  • the molten solder when flowing from the feed via 13, favours filling the wider flow channel 140 rather than being forced up the target via 14.
  • a sufficient load weight, or some kind of clamping force, is therefore needed to counteract the lifting of the cap die 11, to prevent the failure of the solder pump in this manner.
  • the bond number B 0 is calculated to determine whether the effect of gravity should be considered.
  • ⁇ and P are the surface tension and density of the molten solder respectively.
  • L is the characteristic length scale of the solder pump structure, which in the embodiments described herein is the radius of the feed via 14, and is of the order of 100 ⁇ m, the scale unit of the structure.
  • B 0 » 30 the gravity effect is negligible as the surface tension force is 30 times larger.
  • Figure 15 illustrates the forces acting on the upper metal pad 16. Pressure 110 generated by the molten solder provides an upward force on the cap die 11.
  • Load weight 112 which is the total weight of the cap die 11 and an extra load, provides an opposing downward force on the base die 12.
  • Surface tension 114 of the molten solder provides forces acting on both the cap die 11 and the base die 12. In terms of the force balance condition, it can be shown that the minimum load weight to prevent the lifting of the cap die is:
  • W load (4)
  • W load is the load weight
  • S pad and L pad are the area and length of the perimeter of the lower metal pad 17, respectively.
  • any suitable clamping arrangement may be used to constrain the maximum separation of the cap silicon die 11 and the base silicon die 12, and hence avoid the failure mechanism as described in relation to Figure 10.
  • solder balls of 300 ⁇ m diameter were used to obtain the results shown (the diameter of the TWI obtained may be decreased by using solder balls of a smaller diameter such as 100 ⁇ m diameter and adjusting the diameters of the vias accordingly).
  • the diameter of the target via 13 was 25% larger than the diameter of the solder balls 15, whereas the feed via 14 was only about 4% larger. Both the feed via 13 and the target via 14 were loaded with two solder balls.
  • the die assembly was placed on a hotplate in a gastight reflow chamber together with microscope slides slightly sprayed with resin flux (Electrolube brand). After an initial 15 minute nitrogen purge, the hotplate was ramped to 25O 0 C at 25°C/min for reflow, and then returned to room temperature.
  • Figure 16A shows a scanning electron microscope (SEM) image of the solder formed inside the solder pump with the cap die 11 removed. It can be seen that the shape of the solder is very similar to the simulated result of Figure 13D.
  • insufficiency in the volume of solder is solved by using multiple feed vias 13, all of which are in communication with a single target via 14.
  • Figure 16C shows a solder bump forming the cap on target via 14 with the cap silicon die 11 and base silicon die 12 in position.
  • the solder bump 94 may be used for surface mounting in a BGA manner as discussed earlier.
  • Figures 16E to 161 for which the embodiment of Figure 2 A was used, it can be seen that in Figures 16E and 16F, two feed vias 13 feed each target via 14.
  • Figure 16E eight out of nine solder pumps were successful, demonstrating the reproducibility of the solder pump technique.
  • Figure 16F shows a close-up of a solder pump after reflow.
  • Figure 16G shows a cross- section through a low-resistance solder pump via. After reflow, the target via 14 is filled (cylinder 93 as per Figure 16A) completely void-free.
  • Figures 16H and 161 show further successful results from the perspective of a cap die 11 and a base die 12 respectively.
  • the metal pads should be of sufficient thickness (for example 500 nm) to prevent them from dissolving during reflow, in order to provide combined mechanical and electrical connection in the resulting structure after reflow.
  • the resulting filled target via may be suitable for creating solder balls on, for example, a BGA device.
  • Figures 16J to 16N successful results for the embodiment of Figure 6C are shown (the target and feed vias being axially and vertically aligned).
  • Figures 16 J and 16K show the solder bump capping 94 protruding from the top of a cap silicon die 11
  • Figures 16L and 16M show the capping 94 protruding from the bottom of the cap silicon die 11.
  • Figure 16N shows a cross-section of the resulting low-resistance vertical solder pump TWI interconnect.
  • solder pump structure A new solder pump structure and its potential application in solder-based TWI has been described. Several issues related to the structure and operation of the solder pump have been discussed in section 4.
  • TWI/TSV may provide interconnection on at least three levels - electrical, thermal and physical — and is suitable for use in semiconductor devices, such as
  • each wafer may have a different functionality and inter-wafer electrical interconnection is desired.
  • This may be on the micro scale such as accelerometers in, for example, airbag collision detection devices, or on the macro scale such as in printer heads.
  • TWI/TSV to produce micro-scale 3D solder formations on the surface of a silicon wafer. This could be applied, for example, to form solder pillars which could be used for thermal dispersion.
  • Figure 18 shows two further applications of TWI/TSV produced by the solder pump system described herein: 3D packaging in the form of stacked silicon dies 130; and two examples of wafer-level packaging.
  • wafer-level packaging both comprise a wafer 131 directly mounted on at least one silicon die 132.
  • Both applications may be surface mounted to an underlying PCB (not shown).
  • Today's electronics require Integrated Circuits (ICs) with multiple functionality and minimum footprint. PCB real-estate is at a premium where the size of the electronic device is a major design concern, such as in a mobile telephone or other portable electronic device.
  • ICs Integrated Circuits
  • the desire to stack silicon dies on top of each other, utilising the same PCB footprint, is known in the art; however, achieving this is a difficult process.
  • the solder pump system described herein enables, in one process, the stacking of silicon dies and/or silicon wafer level packaging to be combined with providing a ball grid array (BGA) or equivalent connectivity to the PCB on which the device is to be mounted. Therefore, the manufacturing steps of inter-connecting the dies/wafers and then creating a ball grid array for the surface mounting of the device may be merged into one. This saves time and tooling up of a specialist machine, when compared to the known methods of TWV and Silex Via.
  • BGA ball grid array
  • solder may be used successfully as a primary interconnecting material for all three levels of electrical interconnections - i.e. die level (semiconductor level), carrier level (package level), and main circuit board level (PCB level) - this solder-based TWI can be more readily adapted into current packaging technology.
  • the techniques described herein for utilising a pressure differential to electrically, thermally and/or mechanically connect two silicon substrates may be applied to any suitable substrates, and may be applied on a larger scale, as well as to the micro-scale of silicon wafers and dies.

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Abstract

A method of forming an interconnection through, a substrate (11), the method comprising the steps of : forming a first via (14) through the substrate; providing a second via (13) in communication with the first via; introducing connecting material (15) into at least the second via; causing the connecting material to flow, in liquid form, from the second via to the first via under the effect of a pressure differential (e.g. as a result of a capillary- effect); and solidifying the connecting material in the first via, thereby forming an interconnection through the substrate.

Description

METHOD AND APPARATUS FOR FORMING AN INTERCONNECTION THROUGH A SUBSTRATE
This invention relates to a method and apparatus for forming an interconnection through a substrate. It is particularly suitable, but by no means limited, for use in wafer level packaging, for example to form a through- wafer interconnection in micro-electro-mechanical systems.
Background to the Invention Through-wafer interconnection (TWI), also known as through-silicon via (TSV), is a critical and enabling technology for 3D vertical stacked-die and wafer level packaging for semiconductor devices such as, but not limited to, micro-electro-mechanical systems (MEMS) and integrated circuits (ICs). Compared to conventional planar feed-through technologies, TWI/TSV offers several advantages such as higher connection density, lower resistance and smaller parasitic components in RF circuits.
The fabrication of known TWI/TSV involves at least some of the following techniques: via fabrication, isolation, deposition of diffusion barrier and adhesion layers, metallization, via filling, wafer thinning, dicing, alignment and bonding. The metallization of the sidewall of the via involves physical vapour deposition (PVD) or chemical vapour deposition (CVD). These processes have a geometric constraint problem due to the high aspect ratio of the via. Moreover, electroplating is used to fill the vias. As electroplating is a damascene process, it can take hours to fully fill a via hole. Furthermore, tight control of all of the chemical additives during the electroplating process is critical and costly [1-8]. Other TWI/TSV techniques specify the use of specific, non-standard silicon wafers, such as low resistivity, high resistivity, or even glass wafers [9-11]. To date, two main TWI/TSV techniques have been developed, as follows:
The first technique was proposed by Hyongsok T. Soh and his colleagues at Stanford University in 1998, and is named "through- wafer via" (TWV). The main process involves through wafer etch by way of deep reactive-ion etching (DRIE), thermal oxidation, chemical vapour deposition (CVD) metallization and electroplating, followed by patterning and etching [1, 2, 3].
The second technique is named "Silex Via" and was developed by Silex Microsystems Ltd. The technique behind Silex Via is the use of low resistivity through-wafer silicon pillars that are fabricated by DRIE to serve as a conductive medium [12]. The trenches between the pillars and the main wafer body are then filled with dielectric materials for electrical isolation, followed by thin etching, metal deposition and patterning.
Both of these techniques have disadvantages. With TWV, the involved CVD metallization and electroplating has a geometric constraint problem. Deposition of metal on the internal wall of a through- wafer hole with a high aspect ratio is always a challenge. With Silex Via, using silicon as a conductive medium produces a relatively larger resistance than metals. Furthermore, to allow devices constructed using both the TWV and the Silex Via methods to be compatible with surface mounting technology (SMT), additional solder balls must be attached to the interconnection surfaces by reflowing, for example in order to form a ball grid array. Additionally, the use of specific non-standard silicon wafers is much more costly than using a standard silicon wafer. There is, therefore, a need for a simpler and more efficient way in which to form TWI/TSV.
Summary of the Invention According to a first aspect of the present invention there is provided a method as defined in Claim 1 of the appended claims. Thus there is provided a method of forming an interconnection through a substrate, the method comprising the steps of: forming a first via through the substrate; providing a second via in communication with the first via; introducing connecting material into at least the second via; causing the connecting material to flow, in liquid form, from the second via to the first via under the effect of a pressure differential; and solidifying the connecting material in the first via, thereby forming an interconnection through the substrate.
The term "interconnection" should be interpreted broadly, to encompass an electrical interconnection through the substrate, or a thermal interconnection, or an interconnection for mechanical joining purposes. The term "substrate" as used herein should be interpreted broadly, to encompass any wafer or die material capable of being used with the process described herein. The term "via" as used herein should be interpreted broadly, to encompass a through- hole through the wafer or other substrate material. The term "connecting material" should be interpreted as any material suitable for providing a interconnection through the substrate material used. The connecting material may be conductive (e.g. a conductive solder) or non-conductive.
By virtue of the connecting material being driven into the first via from the second via under the effect of the pressure differential, and then allowed to solidify in the first via, this enables the interconnection to be readily formed in the first via. Preferable yet optional features are defined in the dependent claims.
Thus, in certain embodiments, the second via has a diameter less than that of the first via. This difference in via diameters enables the surface tension force of the liquid connecting material (e.g. molten solder) to be exploited, to
"pump" the liquid connecting material from the second via into the first via.
This technique may be used to form a TWI in the first via without the need for prior deposition of metal on the internal wall of the via (as is the case with TWV) - thereby avoiding geometrical constraint problems - and without using interconnecting silicon (as is the case with Silex Via).
The second via may also be formed through the substrate.
Alternatively the second via may be formed through a base die. In such instances, the substrate and the base die are preferably positioned such that the first and second vias are axially aligned. This allows the forming of fewer vias in the substrate, and multiple first vias to be arranged in a reduced pitch array (i.e. more closely positioned relative to one another). A support die may be provided beneath the base die to hold connecting material in the second via prior to flowing. Furthermore, the support die may comprise a vent hole to prevent air pressure dropping in the second via hole during the melting of the reflow.
Optionally the first via may be through-plated with a material wettable by the connecting material when in liquid form. This enables a difference in the surface energies of the connecting material (e.g. molten solder) in the first and second vias to be exploited, to "pump" the liquid connecting material from the second via into the first via. This technique may be used to form a TWI in the first via, and also allows the first via to have a diameter less than that of the second via. This reduces the volume of connecting material required.
These techniques promise several advantages over current TWI methods: no 5 customized wafer is needed; the fabrication process is simpler; it is more compatible with surface mounting technology (SMT); it is compatible with current packaging processes which already use reflow techniques; and through the use of solder, the resulting interconnection can have a low electrical impedance. 0
Preferably the method further comprises providing a path from the second via to the first via, along which liquid connecting material may flow. In certain embodiments the said path is formed between the substrate and a base die. To achieve this, the method may further comprise providing one or more spacers 5 between the substrate and the base die.
The said path may incorporate a channel within the base die.
The method may further comprise providing one or more metal pads along the0 said path, the metal pads being situated on the substrate, the base die, or opposingly on both the substrate and the base die. Such pads may be wetted by the liquid connecting material, and therefore aid in defining the flow path for the liquid between the first and second vias. Due to the wetting of the pads, this may also facilitate forming an electrical interconnection and/or an5 increased physical bonding effect between the connecting material and the substrate and/or base die - particularly when a solder connecting material is used in conjunction with a silicon substrate, since silicon is not ordinarily wetted by molten solder.
Λ •aeoΛc-l. ιΛ The method may further comprise forming an isolating layer (e.g. an electrically-isolating oxide layer, or some other dielectric layer) on the surface of the substrate, after the formation of the first via, and prior to the introduction of the connecting material. This provides isolation (e.g. electrical isolation) between the connecting material and the substrate.
Similarly, the method may further comprise forming an isolating layer on the surface of the base die, prior to the introduction of the connecting material.
Preferably the step of introducing connecting material comprises introducing connecting material into both the first and second vias. Connecting material may also be introduced into a said channel, if one is present.
In alternative embodiments, the second via may be formed within a base die. The second via may be substantially within the plane of the base die.
With all the embodiments, the second via may be one of a plurality of such vias in communication with the first via. In this manner, a relatively large quantity of connecting material may be supplied from the plurality of second vias to the first via.
Moreover, with all the embodiments, a metal pad may be provided on a surface of the said substrate around the outlet of the first via. This metal pad may be wetted by the connecting material (when molten) in order to provide additional electrical, physical and thermal interconnection.
The method may comprise causing the connecting material to flow to such an extent that, when solidified, it protrudes out of the first via. If this is performed in a plurality of locations on the substrate, substantially simultaneously, an array of protrusions of connecting material may be formed. This technique is attractive for use with surface mounting technology (SMT), as an array of such protrusions may be used to form the balls of a ball grid array (BGA) in a single operation, without the need to attach additional balls to form the BGA.
Preferably the connecting material is introduced as solid material, and the step of causing the joining material to flow comprises melting the connecting material. This is particularly well suited to automated processing. Preferably the connecting material is solder. Particularly preferably is introduced in the form of solder balls. However, the solder may alternatively be introduced by any suitable deposition method, such as solderjet (RTM), electroplating, wave soldering, etc.
The solder may be an alloy of tin/lead, or tin/silver, or may be a lead-free solder, as those skilled in the art will appreciate.
The substrate may be silicon-based, and may be a wafer.
The method may include aligning the substrate and a base die using a means of alignment. For example, pins or supports may be inserted through alignment holes in the substrate and base die, or the substrate and base die may be located within a frame. Alternative alignment techniques will be readily apparent to those skilled in the art of device fabrication.
According to a second aspect of the present invention there is provided an arrangement comprising: a substrate having a first via therethrough; a base die; and a second via in either the substrate or the base die, the second via being in communication with the first via, such that liquid connecting material may flow from the second via to the first via under the effect of a pressure differential. Optional features correspond to the optional features summarised above, as set out in the dependent claims.
If the connecting material has yet to be flowed into the first via, then there may be as-received connecting material in at least the second via, and possibly in the first via, and also in the said channel, if one is present.
Alternatively, if the connecting material has been flowed, there will be solidified connecting material in the first via. Solidified connecting material may protrude out of the first via. This may be reproduced in a plurality of locations on the substrate so as to form an array of protrusions of connecting material, for example for use as a ball grid array.
Brief Description of the Drawings
Embodiments of the invention will now be described, by way of example only, and with reference to the drawings in which:
Figure IA is a three-dimensional illustration of a first embodiment of a so- called "solder pump", with solder balls placed in the target and feed vias within a cap silicon die, ready for reflow;
Figure IB is a cross-section schematic of the embodiment of Figure IA (note that the device has been rotated through 180° about a vertical axis when going from Figure IA to Figure IB), illustrating the use of opposing upper and lower metal pads on either side of the path along which molten solder will flow once melted;
Figure 2 illustrates a second embodiment of a solder pump, having opposing metal pads and isolating layers of silicon dioxide on the silicon substrates; Figure 2A illustrates a variation of the embodiment of Figure 2 wherein the metal pads only surround the target via; Figures 2B illustrates a variation of the embodiment of Figure 2 wherein a U- shaped flow configuration is employed together with multiple feed vias that are each narrower than the target via;
Figure 2C illustrates the solder, once re-solidified, of the solder pump of Figure 2B;
Figure 3 illustrates a third embodiment of a solder pump, having an upper metal pad and an isolating layer of silicon dioxide on the upper silicon substrate, and a channel formed in the lower substrate;
Figure 4 illustrates a fourth embodiment of a solder pump having a lower metal pad and isolating layers of silicon dioxide on the silicon substrates;
Figure 5 illustrates a fifth embodiment of a solder pump in which the feed via is within the base die;
Figure 6A illustrates a sixth embodiment of a solder pump in which the target via is formed in the upper silicon substrate (which has an isolating layer of silicon dioxide) and the feed via is formed in the lower silicon substrate, and where the substrates are mounted upon a support die, and the vias are aligned axially and vertically;
Figure 6B illustrates the solder, once re-solidified, of the solder pump of Figure
6A; Figure 6C illustrates a variation of the embodiment of Figure 6A wherein a vent hole is present in the support die;
Figure 6D illustrates a variation of the embodiment of Figure 6A wherein the feed via has a sloped or tapered wall profile;
Figure 6E illustrates a variation of the embodiment of Figure 6A wherein the feed via has a stepped wall profile (as shown, the lower die could be one die or formed by two dies);
Figure 6F illustrates a variation of the embodiment of Figure 6A wherein two feed vias are present in the lower die, the two feed vias being connected by a connection die; Figures 6G, 6H and 61 illustrate the molten solder flow mechanism of the solder pump of Figure 6F;
Figure 6J illustrates the solder, once re-solidified, of the solder pump of Figure
6F; Figure 7A illustrates a seventh embodiment of a solder pump having an arrangement similar to the embodiment of Figure 2 wherein the target via is through-plated and is narrower than the feed via;
Figure 7B illustrates the solder, once re-solidified, of the solder pump of Figure
7A; Figure 8 A illustrates an eighth embodiment of a solder pump having a axial vertical arrangement of the target and feed vias wherein the target via is narrower than the feed via;
Figure 8B illustrates the solder, once re-solidified, of the solder pump of Figure
8A; Figure 9 illustrates a general method of fabricating silicon substrates for the solder pump embodiments of Figures 1 to 4;
Figure 10 illustrates the solder flow mechanism of the embodiment of Figures
IA and IB;
Figure 11 illustrates the solder flow mechanism of the embodiment of Figures 7A and 7B;
Figure 12 illustrates various parameters for modelling the operation of a solder pump;
Figure 13 illustrates a simulation of solder flow and the shape of molten solder before, during and after reflow of the solder material; Figure 14 illustrates a simulation of a failure of the solder pump due to insufficient load on the upper substrate;
Figure 15 illustrates the forces acting on the upper substrate during reflow;
Figures 16A-N show scanning electron microscope micrographs of solder pump prototypes after the solder has solidified; Figure 17 shows the capillary pressure in molten solder within a via, for different via diameters; and
Figure 18 shows two applications of TWI/TSV produced by the solder pump system, namely 3D stacked-dies and wafer-level packaging.
In the figures, like elements are indicated by like reference numerals throughout.
Detailed Description of Preferred Embodiments
The present embodiments represent the best ways known to the applicants of putting the invention into practice. However, they are not the only ways in which this can be achieved.
By way of an initial introduction, the present embodiments are variants of what we have termed a "solder pump". Our solder pump concept causes molten solder to flow into a "target" via in a substrate, and this may be used to form an interconnection through the target via. The interconnection so formed may be an electrical interconnection, or a thermal interconnection, or for mechanical joining purposes.
Briefly, the operation of our solder pump concept is as follows. Solid solder, for example in the form of solder balls, is introduced in a "feed" via, which is preferably formed in the same substrate as the target via. The feed via is in communication with the target via by way of a path. In our preferred embodiments, solid solder is introduced in the target via as well as the feed via. The solder is then melted, upon which it then flows, under the effect of a pressure differential, from the feed via and into the target via, so as to fill the target via. In some embodiments, the pressure differential may be one which arises automatically, through capillary and surface tension effects, as a result of the feed via being of a smaller diameter than the target via. In other embodiments, the pressure differential may arise due to differing surface energies of the molten solder in the target and feed vias. The differing surface energies are as a result of the target via being additionally through-plated and hence wettable by the molten solder. With the through-plating, the target via may be a smaller diameter than the feed via.
Other ways of setting up a pressure differential are also possible, such as by arranging a gas supply to act upon the feed via, or by connecting a vacuum supply to the target via.
Once solder flow has taken place, the solder is then solidified. The solidified solder in the target via provides an interconnection through the substrate. The substrate may be a silicon wafer, and thus the present embodiments provide a way of forming through-wafer interconnections. However, the invention is more broadly applicable than to just molten solder and silicon wafers. As those skilled in the art will appreciate from the description which follows, other connecting materials and other substrate materials may also be used.
1. Configuration of the solder pump structure prior to solder reflow
In Figures IA and IB, a cross-section schematic of a first embodiment of a solder pump structure 10 is illustrated. The structure comprises two substrates, in this case a cap silicon die 11 and a base silicon die 12. A pair of through- wafer holes or vias 13 and 14 have been formed through the cap silicon die 11, for example by deep reactive-ion etching (DRIE). The vias 13, 14 have different diameters. The diameter of the so-called "target" via 14 (which may be considered a 'first' via) is greater than that of the so-called "feed" via 13 (which may be considered a 'second' via). Solder balls 15 are placed within at least the feed via 13, and preferably within both the target and feed vias, as illustrated. The solder balls 15 may be formed from a standard solder composition of a tin/silver or tin/lead alloy, or any other suitable material, such as lead-free solder compositions.
Underlay 19 provides a degree of separation between the cap die 11 and the base die 12, so as to form a flow path 18 from the feed via 13 to the target via 14.
Upper metal pads 16 are positioned on the cap silicon die 11 , and an opposing lower metal pad 17 is positioned on the base silicon die 12, on either side of the path 18. These pads are wettable by molten solder, and thus serve to define the flow path 18 from the feed via 13 to the target via 14. Once molten, solder is able to flow during along the path 18, from the feed via 13 to the target via 14. This is of benefit since silicon and silicon dioxide are not wetted by molten solder, and so the flow of molten solder would not be so predictable without the metal pads. Due to the wetting of the pads, this may also facilitate forming an electrical interconnection and/or an increased physical bonding effect between the solder and the cap die 11 and/or base die 12, and may additionally provide hermetic sealing.
If electrical or thermal insulation is required between the dies 11, 12 and the connecting material (e.g. solder), then the dies 11, 12 may be isolated from the connecting material by forming an isolating coating on the surfaces of the dies. As illustrated in Figures 2 to 8, this may be achieved by forming a silicon dioxide layer on the surface of at least one of the silicon dies by oxidation. The isolation layer can also be formed by depositing any suitable dielectric material, such as silicon dioxide or silicon nitride. Alternatively, as shown in Figure 2A5 the upper metal pad 16 may surround only the target via 14, and not the feed via 13. This promotes the eventual reflow of the molten solder balls from the feed via to the target via.
In some instances it may be sufficient to place solder balls only in the feed via 13 - or in a plurality of feed vias, if more than one is employed, as illustrated in Figures 2B and 2C - and not in the target via 14. As illustrated in Figure 2B, the feed vias 13 are narrower than the target via 14 (as per Figures IA, IB, 2, 2A, 2B, 2C and 4). With such a configuration, having a plurality of feed vias serving a single target via, the placing of solder balls in the target via 14 may be omitted, as the feed vias 13 provide sufficient molten solder under reflow to fill the target via 14 and produce the desired electrical and/or physical bonding effect, as illustrated in Figure 2C.
Further embodiments of the solder-pump structure are shown in Figures 3 to 8. In the embodiment of Figure 3, the metal pad 16 is positioned on the cap silicon die 11, without there being an opposing lower metal pad. Also, in this embodiment, the flow path 18 comprises an additional channel 31 in the base silicon die 12. Solid solder balls 15 are placed within this channel 31, as well as in the feed via 13 and the target via 14.
In Figure 4, the metal pad 17 is placed on the base silicon die 12, and there is no opposing upper metal pad. Thus, in both the embodiments of Figure 3 and Figure 4, the flow path 18 is bordered on one side by a metal pad and on another side by a silicon die (which may or may not be formed with an isolating layer). This is possible since a single pad is sufficient to provide a wettable surface and thereby define the flow path 18. In the embodiment of Figure 3, the use of a single metal pad also allows the cap silicon die 11 and the base silicon die 12 to be separated more easily after the solder has flowed and solidified. This is because the solder, once solid, only bonds to the side of the path 18 that comprises a metal pad. Additionally, the fabrication process is simpler when metal deposition is only required on one of the substrate dies.
In alternative variants, the feed via 13 may be angled (rather than being perpendicularly through the die 11) such that an increased volume of solder balls may be positioned within the feed via prior to reflow.
Alternatively, as shown in Figure 5, the feed via 13 may be positioned entirely within the base silicon die 12, allowing a simpler construction of the solder pump system with fewer vias required in the cap silicon die 11. In this case, the feed via 13 may be positioned horizontally, such that it is not exposed to the surrounding atmosphere.
Figure 6 A shows an embodiment where the target via 14 is formed in the cap silicon die 11 and the feed via 13 is formed in the base silicon die 12. The dies are positioned such that the target and feed vias are aligned axially and vertically. Underlay 19 may optionally be employed in order to provide a degree of separation between the cap and base dies. Metal pads 16 are positioned on the cap silicon die 11 surrounding the target via 14. Solder balls 15 are positioned within at least the feed via 13, and preferably both the target and feed vias, as illustrated. An additional silicon die 73 is positioned below the base silicon die 12 in order to retain the solder balls 15 in the feed via 13. Once molten, solder is able to flow from the feed via 13 to the target via 14 until it reaches the configuration shown in Figure 6B. A solder bump capping 94 may protrude from the outer surfaces of the cap silicon die 11. In a similar manner to the embodiment of Figure 3, the cap silicon die 11 and the base silicon die 12 may be separated more easily after the solder has flowed and solidified. This is because, in this arrangement, there are no metal pads (equivalent to feature 17 of Figures IA, IB, 2 and 3) that cause the solidified solder to physically bond the cap silicon die 11 to the base silicon die 12.
An alternative arrangement is shown in Figure 6C. Here, an additional silicon die 73, positioned below the base silicon die 12, is provided with a through hole 74 as shown. The hole is axially and vertically aligned with the target and feed vias, and is suitably dimensioned such that solder balls 15 are supported in the feed via 13 during initial placement. Gas can thereby vent into the feed via 13 from through hole 74 during the reflow, and so prevent a low pressure developing in the feed via 13 underneath the molten solder as the molten solder is pumped up.
Both the embodiments of Figures 6A and 6C result in the final TWI configuration shown in Figure 6B.
Figures 6D and 6E show yet further embodiments where the target via 14 and the feed via 13 are aligned axially and vertically. The embodiment of Figure
6D comprises sloped or tapered sidewalls in the feed via 13, and the embodiment of Figure 6E has a stepped configuration of the feed via 13. As can be seen, the slope (Figure 6D) or stepped configuration (Figure 16E) is arranged such that the diameter of the feed via 13 increases in a direction towards the target via 14. This causes a pressure differential to act on the solder, when molten, in the direction of the target via 14, resulting in the final
TWI configuration of Figure 6B. In the embodiments of Figures 6D and 6E3 the feed via 13 is dimensioned such that the solder balls 15 required for the solder pump effect need only be placed within the feed via prior to reflow. This allows the base die 12 to be prepared and solder balls placed within the feed via(s) 13 independently of the cap die 11. Therefore, the geometric structure of the cap die 11 does not influence solder ball placement. Typically, the cap die 11 (to which the solder reflows) may be a target device on a printed circuit board. The device, therefore, may be excluded from involvement in the solder ball placement. This simplifies printed circuit board manufacture and preparation, and reduces the exposure to manufacturing processes that the devices must withstand.
As can be seen from Figure 6E, a feed via 13 having a stepped sidewall may be formed using a base die 12 and an additional die 20, the interface between the two providing a step in the diameter of the feed via 13. Depending on topology, this can result in the base die 12 and the additional die 20 being reduced in thickness (in comparison to an alternative in which the step is formed in a single die, for example by appropriate drilling of axially aligned holes of different diameters).
In comparison, the tapered or sloped sidewall of the feed via 13 of the embodiment of Figure 6D is preferably fabricated from a single base die 12. Providing an accurate taper or slope may require deep DRIE (for example up to lOOOμm). The angle of the taper or slope may be about 1°.
Turning to the embodiment of Figure 6F, this illustrates yet another variation on the vertical arrangement. Here, two feed vias 13 A, 13B are provided in the base die 12, the first feed via 13 A being in axial and vertical alignment with the target via 14 in the cap die 11, and the second feed via 13B being situated alongside the first. A connection die 75 provides a linking passage or trench 76 to allow molten solder to flow from the second feed via 13B to the first feed via 13 A. The diameter of the second feed via 13B is less than that of the first feed via 13 A, which in turn has a diameter less than that of the target via 14.
Thus, once molten, solder is able to flow from the second feed via 13B, through the linking passage or trench 76 and the first feed via 13 A, to the target via 14, as shown in Figures 6G to 61, until it reaches the configuration shown in Figure 6 J. As in Figure 6B, a solder bump capping 94 may protrude from the outer surfaces of the cap silicon die 11.
In the embodiments of Figures 1 to 6, the pressure differential between the feed and target vias arises through capillary and surface tension effects. This is a result of geometrical effects, with the feed via being of a smaller diameter than the target via.
As previously discussed, the pressure differential between the feed and target vias may also arise due to differing surface energies of the molten solder in the target and feed vias. This differing surface energy results from the target via being through-plated and hence wettable by the molten solder. The feed via is not plated, and hence is not wettable by the molten solder. This technique is employed in the embodiments of Figures 7A-B and 8A-B.
In the embodiment of Figure 7A5 the silicon dies are arranged in a manner similar to the embodiment of Figure 2, except that the target via 14 is through- plated 71 and has a smaller diameter than the feed via 13. In this embodiment, as the size of the target via 14 is smaller, the overall volume of the vias is reduced. The flow path 18 is defined by the upper metal pads 16 and lower metal pads 17 as in the embodiment of Figure 2. Additionally, solder balls 15 need only be positioned in the feed via 13 prior to reflow, as a consequence of the decreased overall volume of the vias. As can be seen from Figure 7B, once solidified, the target via 14 provides a bonding effect between the cap silicon die 11 and the base silicon die 12 by virtue of the lower metal pads 17 and the optional upper metal pads 16.
Figure 8A shows a further embodiment where, similarly to the embodiment of Figure 6A, the target via 14 is formed in the cap silicon die 11 and the feed via 13 is formed in the base silicon die 12. The dies are positioned such that the target and feed vias are vertically and axially aligned. Metal pads 16 are positioned on the cap die 11 around the target via 14. Target via 14 is through- plated (71) and of a smaller diameter than the feed via 13. This allows the overall size of the vias to be reduced which, in-turn, would allow multiple target vias to be arranged in a reduced pitch array (i.e. more closely positioned relative to one another). Underlay (not shown) may be employed to provide a degree of separation between the cap silicon die 11 and the base silicon die 12.
As in the embodiment of Figures 7A and 7B, solder balls 15 need only be positioned in the feed via 13 prior to reflow. The narrower target via 14 retains the solder balls 15 in the feed via 13 prior to reflow (and hence no additional die 73 is required). Once molten, solder is able to flow from the feed via 13 to the target via 14 until it reaches the configuration shown in Figure 8B. As illustrated, a solder bump capping 94 may protrude from the surfaces of the cap silicon die 11. As previously discussed, once the solder is solidified, the base silicon die 12 and the cap silicon die 11 may then be separated. This is due to there being no metal pads on the base silicon die that would provide a physical bonding effect with the solidified solder.
In all of the embodiments of Figures 1 to 8, optional metal pads 72 may be positioned on the exterior surface of the cap die 11, around the outlet of the target via 14, as shown in Figures 6 to 8. This may enhance the electrical interconnection, increase physical bonding, and also provide hermetic sealing.
Figure 9 illustrates a general method of fabricating the silicon dies (silicon substrates) for a two-substrate solder pump system (e.g. as shown in Figures 1 to 4). The steps will individually be familiar to those skilled in the art and so will only be described at a high level here, to illustrate their order of execution during the fabrication process, rather than to provide precise details. It will be apparent to those skilled in the art that these steps may easily be adapted in order to fabricate silicon dies for use with any of the embodiments of the solder-pump system disclosed herein.
In step 51 (as numbered in Figure 9), pieces of silicon wafer of suitable dimensions for the cap silicon die 11 are obtained, and target via 14 (a first via of a first radius) and feed via 13 (a second via of a smaller second radius) are created in step 52, for example by deep reactive-ion etching. If a silicon dioxide or other oxide layer is desired, then such a layer may be formed in step 53. This may be done, for example, by exposing the silicon dies to oxygen, and heating as appropriate, or by depositing the silicon dioxide or other layer (e.g. silicon nitride) directly onto the silicon dies. This produces a cap silicon die having an isolating layer, as shown in the embodiments of Figures 2, 3 and 4.
If a metal pad is to be deposited on either of the silicon dies, the deposition process is performed in step 55, after an optional step 54 in which an additional silicon wafer die 50 is formed with vias of appropriate dimensions in order to provide a template for the metal pad deposition process. (This optional step 54 may be performed since the alternative well-known method of covering the metal to be retained with photo-resist prior to exposing to ultra-violet light, and then etching, would be very cumbersome for the small dimensions of metal pad desired.) In step 56, the additional silicon wafer die 50 is removed, resulting in a cap silicon die 11 comprising metal pads 16 as per the embodiments of Figures IA-B, 2 and 3.
To form the base silicon die 12, certain steps are performed as per the cap silicon die 11. To avoid repetition, these will not be described again here. After the deposition of metal in step 55, in step 57 a layer of photoresist is added over the metal. In step 58 the photoresist is removed in positions where a metal pad is not ultimately required (according to the location of the vias 13, 14 in the cap silicon die 11). After etching in step 59, the remaining photoresist is removed, rendering a base silicon die comprising a metal pad 17 of appropriate dimensions for the embodiments of Figures 1 A-B, 2 and 4.
In the embodiment of Figure 3, the base silicon die 12 includes an additional flow channel 31 which may be created by adding photoresist over the base silicon die at step 61, and then removing the photoresist with ultraviolet light at step 62. The channel is created at step 63 by a deep etching process. The photoresist is removed at step 64 resulting in the base silicon die 12 of the embodiment of Figure 3.
This general method also applies to the solder pump system of Figures IA and IB, which may be constructed in much the same manner, but without forming a coating of silicon dioxide (or another isolating coating) on the dies.
For the vertical embodiments of Figures 6 A, 6C5 6D and 6E, the various wafers are cut to the required thicknesses and, typically, DRIE would be performed to create the through holes that form the feed and target vias (13, 14), and also the vent hole 74 if applicable. Then, isolation with SiO2 or the like takes place, as previously discussed, followed by metallisation of the metal pads.
Alignment of the cap silicon die 11 and the base silicon die 12 may be important for the solder-pump to perform efficiently. One way of achieving this would be to form alignment holes at corresponding positions on the cap silicon die 11, base silicon die 12 and, if present, the support die 73 during
DRIE. Supports or pins may then be inserted through these alignment holes and attached to a base, such that the alignment holes provide accurate alignment of the dies. The gap between dies is approximately 50μm which may be created by positioning underlay as discussed above, or placing thin metal foil spacers between the dies.
A person skilled in the art will readily understand that other suitable means of alignment may be employed, such as a frame in which the dies may be located.
2. Mechanism of the solder pump
The operation of our solder pump concept will now be described with reference to the embodiment shown in Figures IB and 10. It is possible that the theory discussed below may not be absolutely accurate or complete. In any event, regardless of the theory, our experimental observations provide clear evidence that this technique works.
The refϊow of solder balls 15 in the solder pump may be divided into two steps: (i) spreading and combination; and (ii) solder pumping from the feed via 13 to the target via 14.
Step (i) of the mechanism is triggered by reilow, where molten solder (following heating of the solder balls 15 to promote their coalescence) initially spreads (in a manner also known as 'wicking') along the metal pads 16 and 17. Eventually the molten solder from the feed via 13 and the target via 14 combines to form a contiguous volume of molten solder in the flow path 18 between the wettable metal pads, as shown in Figure 10. In step (U)5 the solder is pumped from the feed via 13 to the target via 14. Both silicon (as in the case of the cap silicon die of the embodiment of Figures IA and IB) and silicon dioxide (as in the case of the isolating coating of the embodiments of Figures 2 to 4) are non- wettable by solder, and so hemispherical surfaces 101 are formed both in the feed via 13 and the target via 14 during the pumping process, as shown in Figure 10.
By the force balance condition, the capillary pressure (in Pascals) generated with a spherical cap can be derived by
P- * r (D where γ is the surface tension of molten solder, and r is the radius of the hemispherical cap, which is also the radius of the via for an unwettable sidewall. Because the radius of the feed via 13 is smaller than that of the target via 14, the pressure generated in the feed via is larger than that in the target via.
The driving pressure difference is given by
Figure imgf000024_0001
where Δr = rfeed - r^ is small compared to the solder ball radius.
This pressure difference drives the solder from the feed via 14 to the target via 13, as indicated by the arrows 81 in Figure 10. The transfer of solder ceases when the solder in the feed via 13 forms a cap whose pressure equals the pressure in the cap of the target via 14, i.e. when the two cap radii are substantially equal. At this hydrostatic equilibrium point, the solder in the target via provides an interconnection (e.g. TWI). The hemispherical cap may protrude from the target via 14 and the surface of the cap die 11, as shown in Figures 16B to 16D. The protruding hemispherical cap may be used as a ball of a BGA (if an array of similar target vias is provided in the die 11). Therefore the final solder geometry is governed by surface-energy minimisation. At the completion of the flow, the final geometry of the solder is comprised of four volumes: (a) a solder cap 91 in the feed via 13; (b) a plate 92 within the flow path 18 (between the metal pads 16, 17); (c) a cylinder 93 inside the target via 13 (which serves as the conductive medium for TWI); and (d) a solder bump capping 94 on the target via 14 protruding from the outer surface 95 of the cap die 11. The solder bump capping 94 on the target via 14 may be suitable for surface mounting.
Figure 17 illustrates the capillary pressure in molten solder within a via, for different via diameters.
Instead of using different via diameters, the above solder pump effect could be achieved by any means capable of providing a pressure differential, such that the pressure in the feed via 13 is greater than the pressure in the target via 14. For example, a gas supply may be arranged to act upon the feed via, or a vacuum supply may be connected to the target via.
With reference to the embodiment shown in Figures 7A and 7B, the operation of the solder pump will now be described when the pressure differential results from differing surface energy of the molten solder in the feed via 13 and target via 14. The reflow of solder balls 15 may be divided into two steps in a similar manner as discussed above. With reference to Figure 11, in step (i), during reflow, the molten solder flows from the feed via 13 along metal pads 16 and 17. In step (ii), the solder is pumped from the feed via 13 to the target via 14. The differing surface energies of the molten solder in the target and feed vias is as a result of the solder spreading to and wetting the through-plating 71 in the target via 14. This wetting effect forms a concave meniscus 111 (which has a negative pressure) on the top of the molten solder in the target via 14. The positive pressure of the molten solder in the feed via 13 (which is surrounded by unwettable silicon or an isolating compound such as silicon dioxide) therefore pumps molten solder from the feed via 13 to the target via 14 as indicated by arrows 81 in Figure 11. Eventually, the molten solder may fill the target via 14 to an extent that a hemispherical cap may protrude from the target via 14. This cap may be suitable for use as a ball of a BGA (if an array of similar target vias is provided in the cap silicon die 11).
3. Simulation
Figure 12 shows the geometric parameters of the solder pump structure of the embodiment of Figures IA-B and 2. The pumping step during reflow of the molten solder balls was simulated by computer, for different conditions, to obtain the final shape of the solder, and the results are presented graphically in Figures 13 A to 13D. As shown in these figures, during reflow the solder flows from the feed via 13 to the target via 14 and finally forms the shape shown in Figure 13D (corresponding to real-world examples shown in Figures 16A to 16D) when pressure equilibrium is reached in the molten solder. The final shape of the solder comprises a bump 91 in the feed via 13; a plate 92 within the flow path 18 (between the metal pads 16, 17); a cylinder 93 inside the target via 13 (which serves as the conductive medium for TWI); and a solder bump capping 94 on the target via 14 protruding from the outer surface 95 of the cap die 11. The solder bump capping 94 on the target via 14 may be suitable for surface mounting.
4. Considerations A number of issues were considered and have been optimised in order to provide acceptable performance of the solder pump.
Referring to Figure 12, a first issue is the optimization of the stand-off height Hgap . The solder consumed in the flow path 18 between the metal pads 16 and 17 is preferably minimised; however, the stand-off height Hgap also affects the flow rate of the molten solder. The bigger the flow path 18 between the metal pads 16 and 17, the easier it is for the solder to reflow. It is estimated that a stand-off height of between 10 μm and 50 μm is preferable.
A second issue is that of volume constraint. Initially, the solder used is in the form of balls 15, and the total volume of the solder is therefore calculated as a multiple of the volume of a single solder ball. Through calculation, it has been found that, depending on the diameter of the target via 14, multiple feed vias 12 may be required in order to provide a sufficient quantity of solder. By assuming that the space between the metal pads 16 and 17 and also the solder bump capping 94 on the target via 14 consume one solder ball together, the number of feed vias required can be approximately calculated using the following formula:
JV = (2)
Figure imgf000027_0001
where Rvia and rsb are the radii of the target via 14 and a solder ball 15 respectively, andHwφr is the thickness of the cap silicon die 11. A third issue is the lifting of the cap silicon die 11. During reflow, the surface tension and the pressure within the molten solder yield a lifting force on the upper die 11. This lifting force can result in the failure of the solder pump (as shown in Figure 14) due to lifting of the die 11, which results in the flow path 18 becoming too wide. The molten solder, when flowing from the feed via 13, favours filling the wider flow channel 140 rather than being forced up the target via 14. A sufficient load weight, or some kind of clamping force, is therefore needed to counteract the lifting of the cap die 11, to prevent the failure of the solder pump in this manner.
To theoretically analyze the lifting force, the bond number B0 is calculated to determine whether the effect of gravity should be considered.
PgL
where ^ and P are the surface tension and density of the molten solder respectively. L is the characteristic length scale of the solder pump structure, which in the embodiments described herein is the radius of the feed via 14, and is of the order of 100 μm, the scale unit of the structure. For the parameter values listed in Table 1, B0 » 30 . Thus, the gravity effect is negligible as the surface tension force is 30 times larger.
Figure imgf000028_0001
Table 1
Figure 15 illustrates the forces acting on the upper metal pad 16. Pressure 110 generated by the molten solder provides an upward force on the cap die 11.
Load weight 112, which is the total weight of the cap die 11 and an extra load, provides an opposing downward force on the base die 12. Surface tension 114 of the molten solder provides forces acting on both the cap die 11 and the base die 12. In terms of the force balance condition, it can be shown that the minimum load weight to prevent the lifting of the cap die is:
Wload = (4)
Figure imgf000029_0001
where Wload is the load weight, and Spad and Lpad are the area and length of the perimeter of the lower metal pad 17, respectively. From equation (4) above, the lifting force for the model of Figure 9 (A-D) is approximately 1.5 mN. This concurs with our computer simulation which gave a value of approximately 1.4 mN.
Rather than providing a load weight in accordance with the calculation obtained from equation (4) above, any suitable clamping arrangement may be used to constrain the maximum separation of the cap silicon die 11 and the base silicon die 12, and hence avoid the failure mechanism as described in relation to Figure 10.
5. Experimental results
Referring to Figures 16A to 16D5 solder balls of 300 μm diameter were used to obtain the results shown (the diameter of the TWI obtained may be decreased by using solder balls of a smaller diameter such as 100 μm diameter and adjusting the diameters of the vias accordingly). In these examples (using the embodiment of Figure IB) the diameter of the target via 13 was 25% larger than the diameter of the solder balls 15, whereas the feed via 14 was only about 4% larger. Both the feed via 13 and the target via 14 were loaded with two solder balls. The initial stand-off height Hgap between the two silicon dies 11,
12 was approximately 50 μm. The solder balls used were lead-free (ECO brand from Senju Metal Industry Co. Ltd) with a composition of Sn-3.0Ag- 0.5Cu. The maximum reflow temperature reached was nearly 25O0C (with the melting point of a solder ball being approximately 2200C). The die assembly was placed on a hotplate in a gastight reflow chamber together with microscope slides slightly sprayed with resin flux (Electrolube brand). After an initial 15 minute nitrogen purge, the hotplate was ramped to 25O0C at 25°C/min for reflow, and then returned to room temperature.
Figure 16A shows a scanning electron microscope (SEM) image of the solder formed inside the solder pump with the cap die 11 removed. It can be seen that the shape of the solder is very similar to the simulated result of Figure 13D. In the case of Figures 16B and 16D, and as addressed in section 4 above, insufficiency in the volume of solder is solved by using multiple feed vias 13, all of which are in communication with a single target via 14.
Figure 16C shows a solder bump forming the cap on target via 14 with the cap silicon die 11 and base silicon die 12 in position. The solder bump 94 may be used for surface mounting in a BGA manner as discussed earlier.
Referring to Figures 16E to 161 (for which the embodiment of Figure 2 A was used), it can be seen that in Figures 16E and 16F, two feed vias 13 feed each target via 14. In Figure 16E, eight out of nine solder pumps were successful, demonstrating the reproducibility of the solder pump technique. Figure 16F shows a close-up of a solder pump after reflow. Figure 16G shows a cross- section through a low-resistance solder pump via. After reflow, the target via 14 is filled (cylinder 93 as per Figure 16A) completely void-free. Figures 16H and 161 show further successful results from the perspective of a cap die 11 and a base die 12 respectively. With reference to Figure 161, the metal pads should be of sufficient thickness (for example 500 nm) to prevent them from dissolving during reflow, in order to provide combined mechanical and electrical connection in the resulting structure after reflow. However, even without a mechanical connection, the resulting filled target via may be suitable for creating solder balls on, for example, a BGA device.
In Figures 16J to 16N, successful results for the embodiment of Figure 6C are shown (the target and feed vias being axially and vertically aligned). Figures 16 J and 16K show the solder bump capping 94 protruding from the top of a cap silicon die 11, and Figures 16L and 16M show the capping 94 protruding from the bottom of the cap silicon die 11. Figure 16N shows a cross-section of the resulting low-resistance vertical solder pump TWI interconnect.
6. Conclusions
A new solder pump structure and its potential application in solder-based TWI has been described. Several issues related to the structure and operation of the solder pump have been discussed in section 4.
The embodiments of the solder pump system described herein provide several advantages over current TWI technologies:
(i) Lower resistance due to the high electrical conductivity of the solder and the large cross-sectional area of the through-wafer hole (the target via 13). The electrical impedance can be on the scale of mΩ; (ii) Simpler processing: compared with TWV, the geometric constraints of depositing metal in high-aspect ratio through-wafer holes is avoided as metal deposition is not necessarily required within the vias;
(iii) Enhanced compatibility with surface mounting technology (SMT): the solder bump capping on the target via is ready for surface mounting, while in current TWIs, additional solder balls must be added to make them SMT compatible; (iv) Offers the possibility of achieving bonding and interconnection in one reflow run, when solder is chosen as the bonding material.
7. Applications of the solder pump
TWI/TSV may provide interconnection on at least three levels - electrical, thermal and physical — and is suitable for use in semiconductor devices, such as
MEMS and IC devices, where each wafer may have a different functionality and inter-wafer electrical interconnection is desired. This may be on the micro scale such as accelerometers in, for example, airbag collision detection devices, or on the macro scale such as in printer heads. There is also the possibility of utilising TWI/TSV to produce micro-scale 3D solder formations on the surface of a silicon wafer. This could be applied, for example, to form solder pillars which could be used for thermal dispersion.
Figure 18 shows two further applications of TWI/TSV produced by the solder pump system described herein: 3D packaging in the form of stacked silicon dies 130; and two examples of wafer-level packaging. In the examples of wafer-level packaging, both comprise a wafer 131 directly mounted on at least one silicon die 132. One additionally comprises a cap wafer 133, and the other an additional silicon die 132. Both applications may be surface mounted to an underlying PCB (not shown). Today's electronics require Integrated Circuits (ICs) with multiple functionality and minimum footprint. PCB real-estate is at a premium where the size of the electronic device is a major design concern, such as in a mobile telephone or other portable electronic device. The desire to stack silicon dies on top of each other, utilising the same PCB footprint, is known in the art; however, achieving this is a difficult process. The solder pump system described herein enables, in one process, the stacking of silicon dies and/or silicon wafer level packaging to be combined with providing a ball grid array (BGA) or equivalent connectivity to the PCB on which the device is to be mounted. Therefore, the manufacturing steps of inter-connecting the dies/wafers and then creating a ball grid array for the surface mounting of the device may be merged into one. This saves time and tooling up of a specialist machine, when compared to the known methods of TWV and Silex Via.
Furthermore, since solder may be used successfully as a primary interconnecting material for all three levels of electrical interconnections - i.e. die level (semiconductor level), carrier level (package level), and main circuit board level (PCB level) - this solder-based TWI can be more readily adapted into current packaging technology.
The techniques described herein for utilising a pressure differential to electrically, thermally and/or mechanically connect two silicon substrates may be applied to any suitable substrates, and may be applied on a larger scale, as well as to the micro-scale of silicon wafers and dies.
References
[1] C. Patrick YUE5 Anthony MCCARTHY, Hangsup RYU, Thomas H. LEE,
S. Si-mon WONG5 and Calvin F. QUATE - Ultra-low resistance, through- wafer via (TWV) technology and its applications in three dimensional structures on silicon. Japanese Journal of Applied Physics PtI, Regular papers & short notes, 38(4):2393-2396, 19990430 1999.
[2] J. Neysmith. Modular, device-scale, direct-chip-attach packaging for microsystems. Components and Packaging Technologies, IEEE
Transactions on [see also Components, Packaging and Manufacturing
Technology, Part A: Packaging Technologies, IEEE Transactions on],
24(4):631-634, 2001.
[3] Joon Seong Ok. Advanced Packaging, IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on], 26(3):302-309, 2003.
[4] C. Hubert, R. Nelson, J. Reed, B. Lunceford, A. Somadder, K. Hu, and U. Ghoshal. Thermoelectric mems coolers, pages 117-122, 1999.
[5] J. H. Wu. A through-wafer interconnect in silicon for rfϊcs. Electron Devices, IEEE Transactions on, 51(11):1765-1771, 2004.
[6] Lin Chiung-Wen, Yang Hsueh-An, Chung Wang Wei, and FangWeileun. Implementation of three-dimensional soi-mems wafer-level packaging using through- wafer interconnections. Journal of Micromechanics and Microengineering, (17):1200-1205, 2007.
[7] M. Saadaoui. Local sealing of high aspect ratio vias for single step bottom- up copper electroplating of through wafer interconnects. Sensors, 2007 IEEE, pages 974-977, 2007.
[8] J. Jozwiak. Integrating through-wafer interconnects with active devices and circuits. Advanced Packaging, IEEE Transactions on [see also
Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on], 31(1):4-13, 2008.
[9] Lin Chiung-Wen. Implementation of sog devices with embedded through- wafer silicon vias using a glass reflow process for wafer-level 3d mems integration. In Hsu Chia-Pao, editor, Micro Electro Mechanical Systems,
2008. MEMS 2008. IEEE 21st International Conference on, pages 802-
805, 2008. ISBN 1084-6999. [10] L. L. W. Leung and K. J. Chen. Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates. Microwave Theory and Techniques, IEEE Transactions on, 53(8):2472-2480, 2005.
[11] J. Tian, J. Iannacci, S. Sosin, R. Gaddi, and M. Bartek. Rf-mems wafer- level packaging using through-wafer via technology. In Electronics Packaging Technology Conference, 2006. EPTC '06. 8th, pages 441-447, 2006.
[12] M. Rimskog. Through wafer via technology for mems and 3d integration. In Electronic Manufacturing Technology Symposium, 2007. IEMT '07. 32nd IEEE/CPMT International, pages 286-289, 2007. ISBN 1089-8190.

Claims

1. A method of forming an interconnection through a substrate, the method comprising the steps of: forming a first via through the substrate; providing a second via in communication with the first via; introducing connecting material into at least the second via; causing the connecting material to flow, in liquid form, from the second via to the first via under the effect of a pressure differential; and solidifying the connecting material in the first via, thereby forming an interconnection through the substrate.
2. A method as claimed in Claim 1, wherein the second via has a diameter less than that of the first via.
3. A method as claimed in Claim 1 or Claim 2, wherein the second via is also formed through the said substrate.
4. A method as claimed in Claim 1 or Claim 2, wherein the second via is formed through a base die.
5. A method as claimed in Claim 4, wherein the substrate and the base die are positioned such that the first and second vias are axially aligned.
6. A method as claimed in Claim 5, further comprising providing a support die beneath the base die to hold connecting material in the second via prior to flowing.
7. A method as claimed in Claim 6 wherein the support die comprises a vent hole.
8. A method as claimed in any of Claims 5, 6 or 7 wherein the second via is of varying diameter, the end of the second via nearest the first via being wider than the end of the second via furthest from the first via.
9. A method as claimed in Claim 8 wherein the second via comprises a sloped or tapered sidewall.
10. A method as claimed in Claim 8 wherein the second via comprises a stepped sidewall.
11. A method as claimed in Claim 10 wherein the base die is formed of two dies, the stepped sidewall being formed by the interface of the two dies.
12. A method as claimed in any of Claims 5 to 11, further comprising providing a third via in communication with the second via, the third via containing connecting material and being arranged to feed the second via during flow of the connecting material.
13. A method as claimed in Claim 12 wherein the third via is in communication with the second via by way of a trench in a connecting die.
14. A method as claimed in any preceding claim, wherein the first via is through-plated with a material wettable by the connecting material when in liquid form.
15. A method as claimed in any preceding claim, further comprising providing a path from the second via to the first via, along which liquid connecting material may flow.
16. A method as claimed in Claim 15 when dependent on Claim 3, wherein the said path is formed between the substrate and a base die.
17. A method as claimed in any preceding claim, further comprising providing one or more spacers between the substrate and the base die.
18. A method as claimed in Claim 16 or Claim 17, wherein the said path incorporates a channel within the base die.
19. A method as claimed in any of Claims 15, 16, 17 or 18, further comprising providing one or more metal pads along the said path, the metal pads being situated on the substrate, the base die, or opposingly on both the substrate and the base die.
20. A method as claimed in any preceding claim, further comprising forming an isolating layer on the surface of the substrate, after the formation of the first via, and prior to the introduction of the connecting material.
21. A method as claimed in any of Claims 16 to 20, further comprising forming an isolating layer on the surface of the base die, prior to the introduction of the connecting material.
22. A method as claimed in Claim 20 or Claim 21, wherein the isolating layer is an oxide layer.
23. A method as claimed in any preceding claim, wherein the step of introducing connecting material comprises introducing connecting material into both the first and second vias.
24. A method as claimed in any of Claims 18 to 23, wherein the step of introducing connecting material further comprises introducing connecting material into the said channel.
25. A method as claimed in Claim 1 or Claim 2, or any of Claims 20 to 24 when dependent on Claim 1 or Claim 2, wherein the second via is formed within a base die.
26. A method as claimed in Claim 25, wherein the second via is substantially within the plane of the base die.
27. A method as claimed in any preceding claim, wherein the second via is one of a plurality of such vias in communication with the first via.
28. A method as claimed in any preceding claim, further comprising causing the connecting material to flow to such an extent that, when solidified, it protrudes out of the first via.
29. A method as claimed in Claim 28, performed in a plurality of locations on the substrate, substantially simultaneously, so as to form an array of protrusions of connecting material.
30. A method as claimed in any preceding claim, further comprising providing a metal pad on a surface of the said substrate around the outlet of the first via.
31. A method as claimed in any preceding claim, wherein the connecting material is introduced as solid material, and the step of causing the joining material to flow comprises melting the connecting material.
32. A method as claimed in Claim 31, wherein the connecting material is solder.
33. A method as claimed in Claim 32, wherein the solder is introduced in the form of solder balls.
34. A method as claimed in Claim 32 or Claim 33, wherein the solder is an alloy of tin/lead, or tin/silver, or is a lead-free solder.
35. A method as claimed in any preceding claim, wherein the substrate is silicon-based.
36. A method as claimed in any preceding claim, wherein the substrate is a wafer.
37. A method as claimed in any preceding claim, further comprising aligning the substrate and a base die using a means of alignment.
38. An arrangement comprising: a substrate having a first via therethrough; a base die; and a second via in either the substrate or the base die, the second via being in communication with the first via, such that liquid connecting material may flow from the second via to the first via under the effect of a pressure differential.
39. An arrangement as claimed in Claim 38, wherein the second via has a diameter less than that of the first via.
40. An arrangement as claimed in Claim 38 or Claim 39, wherein the second via is also formed through the said substrate.
41. An arrangement as claimed in Claim 38 or Claim 39, wherein the second via is formed through the base die.
42. An arrangement as claimed in Claim 41, wherein the substrate and the base die are positioned such that the first and second vias are axially aligned.
43. An arrangement as claimed in Claim 42 further comprising a support die positioned beneath the base die.
44. An arrangement as claimed in Claim 43 wherein the support die comprises a vent hole.
45. An arrangement as claimed in any of Claims 42, 43 or 44 wherein the second via is of varying diameter, the end of the second via nearest the first via being wider than the end of the second via furthest from the first via.
46. An arrangement as claimed in Claim 45 wherein the second via comprises a sloped or tapered sidewall.
47. An arrangement as claimed in Claim 45 wherein the second via comprises a stepped sidewall.
48. An arrangement as claimed in Claim 47 wherein the base die is formed of two dies, the stepped sidewall being formed by the interface of the two dies.
49 An arrangement as claimed in any of Claims 42 to 48, further comprising a third via in communication with the second via, the third via being arranged to feed the second via during flow of the connecting material.
50 An arrangement as claimed in Claim 49 wherein the third via is in communication with the second via by way of a trench in a connecting die.
51. An arrangement as claimed in any of Claims 38 to 50, wherein the first via is through-plated with a material wettable by connecting material when in liquid form.
52. An arrangement as claimed in any of Claims 38 to 51, further comprising a path from the second via to the first via, along which liquid connecting material may flow.
53. An arrangement as claimed in Claim 52 when dependent on Claim 40, wherein the said path is formed between the substrate and the base die.
54. An arrangement as claimed in any of Claims 38 to 53, further comprising one or more spacers between the substrate and the base die.
55. An arrangement as claimed in Claim 53 or Claim 54, wherein the said path incorporates a channel within the base die.
56. An arrangement as claimed in any of Claims 52, 53, 54 or 55, further comprising one or more metal pads along the said path, the metal pads being situated on the substrate, the base die, or opposingly on both the substrate and the base die.
57. An arrangement as claimed in any of Claims 38 to 56, further comprising an isolating layer on the surface of the substrate.
58. An arrangement as claimed in any of Claims 53 to 57, further comprising an isolating layer on the surface of the base die.
59. An arrangement as claimed in Claim 57 or Claim 58, wherein the isolating layer is an oxide layer.
60. An arrangement as claimed in Claim 38 or Claim 39, or any of Claims 57 to 59 when dependent on Claim 38 or Claim 39, wherein the second via is formed within the base die.
61. An arrangement as claimed in Claim 60, wherein the second via is substantially within the plane of the base die.
62. An arrangement as claimed in any of Claims 38 to 61, wherein the second via is one of a plurality of such vias in communication with the first via.
63. An arrangement as claimed in any of claims 38 to 62, further comprising a metal pad on a surface of the said substrate around the outlet of the first via.
64. An arrangement as claimed in any of Claims 38 to 63, further comprising as-received connecting material in at least the second via.
65. An arrangement as claimed in Claim 64, further comprising as-received connecting material in the first via.
66. An arrangement as claimed in Claim 64 or Claim 65 when dependent on Claim 55, further comprising as-received connecting material in the said channel.
67. An arrangement as claimed in any of Claims 38 to 63, further comprising solidified connecting material in the first via.
68. An arrangement as claimed in Claim 67, wherein the solidified connecting material protrudes out of the first via.
69. An arrangement as claimed in Claim 68, reproduced in a plurality of locations on the substrate so as to form an array of protrusions of connecting material.
70. An arrangement as claimed in any of Claims 38 to 69, wherein the connecting material is solder.
71. An arrangement as claimed in Claim 70 when dependent on any of Claims 64, 65 or 66, wherein the as-received connecting material is in the form of solder balls.
72. An arrangement as claimed in Claim 70 or Claim 71, wherein the solder is an alloy of tin/lead, or tin/silver, or is a lead-free solder.
73. An arrangement as claimed in any of Claims 38 to 72, wherein the substrate is silicon-based.
74. An arrangement as claimed in any of Claims 38 to 73, wherein the substrate is a wafer.
75. An arrangement as claimed in any of Claims 38 to 74, further comprising means for aligning the substrate with the base die.
76. A method of forming an interconnection through a substrate substantially as herein described with reference to and as illustrated in any combination of the accompanying drawings.
77. An arrangement substantially as herein described with reference to and as illustrated in any combination of the accompanying drawings.
PCT/GB2009/002277 2008-09-23 2009-09-23 Method and apparatus for forming an interconnection through a substrate WO2010034995A1 (en)

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