WO2010033144A1 - Method and apparatus for surface treatment of semiconductor substrates using sequential chemical applications - Google Patents
Method and apparatus for surface treatment of semiconductor substrates using sequential chemical applications Download PDFInfo
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- WO2010033144A1 WO2010033144A1 PCT/US2009/004080 US2009004080W WO2010033144A1 WO 2010033144 A1 WO2010033144 A1 WO 2010033144A1 US 2009004080 W US2009004080 W US 2009004080W WO 2010033144 A1 WO2010033144 A1 WO 2010033144A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0402—Apparatus for fluid treatment
- H10P72/0406—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
- H10P72/0411—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
- H10P72/0414—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly spraying means, e.g. nozzles
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/20—Cleaning during device manufacture
- H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
- H10P70/273—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a delineation of conductive layers, e.g. by RIE
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0402—Apparatus for fluid treatment
- H10P72/0406—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
- H10P72/0411—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0402—Apparatus for fluid treatment
- H10P72/0418—Apparatus for fluid treatment for etching
- H10P72/0422—Apparatus for fluid treatment for etching for wet etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
- H10P72/0604—Process monitoring, e.g. flow or thickness monitoring
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
- H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
Definitions
- the present invention relates generally to semiconductor substrate processing, and more particularly, to systems and methods for treating a surface of a semiconductor substrate using sequential chemical applications.
- the fabrication operations define a plurality of features, such as gate structures, on semiconductor wafers (wafers or substrates) that span multi-levels.
- the substrate is exposed to various contaminants. Any material or chemical used in the fabrication operations to which the substrate is exposed is a potential source of contamination.
- Chemicals used in the various fabrication operations such as etching, deposition, etc., leave deposit, such as process gases, etching chemicals, deposition chemicals, etc., on and around features, such as gate structures, formed on the surface of the substrate, as particulates or polymer residue contaminants.
- the sizes of the particulate contaminants are in the order of the critical dimensions of the features being fabricated on the substrate. These contaminants lodge on the top, along the side walls and in between the features in hard-to-reach areas, such as in a trench surrounding the delicate features, and may likely cause damage to the features within the vicinity of the contaminant particles.
- a typical gate structure formed on a substrate may include a stack of layers made of different materials defining the gate structure.
- the gate structure may include a layer of gate oxide over which an electrode is fabricated using one or more layers of metal, such as tungsten, tungsten compounds, etc.
- the metal that may be used in fabricating the electrode may include tungsten, tungsten suicide, tungsten nitride, tantalum, polysilicon, silicon oxide, aluminum oxide, hafnium oxide, silicon oxynitride, tantalum nitride, etc.
- a layer of polysilicon is formed on top of the metal layer and a hardmask layer is fabricated over the top of the polysilicon layer.
- the hardmask layer is fabricated as a photoresist layer and is used to pattern the gate stack and preserve the underlying layers. During an etching operation, etching chemicals used in patterning the hardmask and the underlying layers leave polymer residue on top and along the sidewalls of the gate structure.
- Conventional polymer residue cleaning methods have relied on batch tools that expose the polymer residues to cleaning chemistries for a prolonged period of time. When a less aggressive cleaning chemistry is used, the exposure results in inefficient removal of polymer residues and other contaminants. On the other hand, when a more aggressive chemistry is used, the exposure using the batch tools leads to high material loss rates at the gate structure rendering the cleaning process undesirable. The material loss includes pullback of the hardmask layer and/or undercut of gate oxide and other layers of the gate structure formed on the substrate.
- Figure 1 illustrates a typical gate structure and Figure 2 illustrates an example of some of the negative effects experienced at various layers of the gate structure.
- Figure 1 illustrates a typical metal gate structure formed on a substrate 100 by various fabrication operations. An etching operation is used to form various layers of the gate structure thereby defining a gate stack.
- the gate structure includes a layer of gate oxide 115 formed on the substrate 100.
- the substrate 100 includes a source/drain region 105 over which the layer of gate oxide 115 (usually of high dielectric constant) is formed.
- a metal electrode is fabricated over the gate oxide 115 using one or more layers of metal. In the metal gate structure illustrated in Figure 1, the metal electrode is formed using a layer of metal 1 120 and a layer of metal 2 122.
- a polysilicon layer 125 is formed over the metal layer and a hardmask layer is formed over the polysilicon layer.
- the hardmask layer may further include one or more layers of hardmask. As depicted in Figure 1, the hardmask layer includes 3 layers of hardmask, mask 1 130, mask 2 132, and mask 3 134.
- the etched materials and the etching chemicals used in the etching operation to define the stack deposit metallic or polymer contaminants on the top and sidewalls of the gate structure. Typical contaminants include polymer residues 140 and metal containing polymer residues 142.
- FIG. 2 illustrates some of the potential issues experienced at the gate structure as a result of a cleaning process using a traditional batch tool.
- the prolonged exposure of the gate structure to aggressive cleaning chemistry used in the batch tool results in the erosion of the hardmask, otherwise known as hardmask pullback.
- the hardmask erosion results in the premature exposure of the underlying layers leading to potential damage and/or further contamination of the gate features.
- the prolonged exposure to the cleaning chemistry may further result in the undercut of the metal layer, such as tungsten, tungsten suicide, etc., used in forming the metal electrode over the gate oxide eventually exposing the gate oxide to the cleaning chemistry.
- the pullback of the hardmask and the undercut of the metal and other layers of the gate structure including the gate oxide pose the greatest problems in the cleaning process.
- the premature exposure of the various layers of a gate stack to chemistries used in subsequent fabrication operations may result in further damage of the layers lending the gate structure inoperable. Efficient and non-damaging removal of contaminants during fabrication poses a great challenge
- the present invention fills the need by providing improved methods and apparatus for efficiently removing polymer residue contaminants formed around a metal gate structure on the surface of the substrate. It should be appreciated that the present invention can be implemented in numerous ways, including an apparatus and a method. Several inventive embodiments of the present invention are described below.
- a method for removing polymer residues from around a metal gate structure during a post-etch cleaning operation includes determining a plurality of process parameters associated with a metal gate structure and the polymer residue formed around the gate structure.
- the gate structure includes one or more layers of fabrication.
- the process parameters define one or more characteristics of the one or more fabrication layers comprising the gate structure and of the polymer residue formed around the gate structure.
- a first and a second cleaning chemistry, to treat the surface of the substrate, are identified.
- One or more application parameters for each of the first and second cleaning chemistries are defined based on the process parameters.
- the first and second cleaning chemistries are applied sequentially to a portion of the surface of the substrate using the application parameters in a controlled manner so as to provide an optimal exposure of the portion of the surface of the substrate to the first and second cleaning chemistries for an optimal period of time such that the polymer residues are substantially removed from around the gate structure while preserving the structural integrity of the one or more layers of the gate structure.
- a system for removing polymer residue from around a metal gate structure formed on a surface of a substrate during a post-etch cleaning operation includes a substrate supporting device to receive, support and transport the substrate through the system.
- a first proximity head is configured to introduce a first cleaning chemistry to a portion of the surface of the substrate as a meniscus.
- a second proximity head is configured to introduce a second cleaning chemistry to the portion of the surface of the substrate as a meniscus.
- the introduction of the first and second cleaning chemistries sequentially through the first and second proximity heads enables application of the first and second cleaning chemistries in a controlled manner to the portion of the surface of the substrate so that the portion of the surface of the substrate is optimally exposed to the first and second cleaning chemistries for an optimal period of time for substantial removal of the polymer residue formed around the metal gate structure while the structural integrity of the one or more layers of the gate structure is maintained.
- Figure 1 illustrates a simplified schematic diagram of a typical post-etch metal gate structure, in one embodiment of the invention.
- Figure 2 illustrates a simplified schematic diagram of potential issues and damages experienced at the post-etch metal gate structure illustrated in Figure 1 during cleaning operation, in one embodiment of the invention.
- Figures 3A-3D illustrate simplified schematic diagrams of various gate structures after etching operation.
- Figure 3A illustrates a simplified DRAM gate structure after full etch, in one embodiment of the invention.
- Figure 3B illustrates a simplified DRAM gate structure after partial etch, in another embodiment of the invention.
- Figure 3C illustrates a simplified Flash tungsten gate structure after an etching operation, in another embodiment of the invention.
- Figure 3D illustrates a simplified tungsten gate Logic structure after an etching operation, in another embodiment of the invention.
- Figure 3E illustrates a simplified schematic diagram of a tungsten metal gate structure after a typical tank cleaning operation, in one embodiment of the invention.
- Figures 4A-4C illustrate simplified schematic diagrams of desired cleaning results expected for various gate structures illustrated in Figures 3A-3C after a cleaning operation.
- Figure 4D illustrates a resultant metal gate structure after a cleaning operation using a first cleaning chemistry and second cleaning chemistry, in one embodiment of the invention.
- Figure 5 illustrates a simplified schematic diagram of a system used in the application of first and second application chemistry to the surface of the substrate, in one embodiment of the invention.
- Figures 6A and 6B illustrate graphs identifying effective removal rate of polymer residue using the first and second cleaning chemistry, in one embodiment of the invention.
- Figure 7 illustrates the optimal exposure time and carrier speed required for effective removal of metal containing polymer residue removal, in one embodiment of the invention.
- Figure 8 illustrates the optimum concentration for effective metal containing polymer residue removal rate, in one embodiment of the invention.
- Figure 9 illustrates various method operations involved in removing polymer residue from around a metal gate structure during post-etch cleaning operation, in one embodiment of the invention.
- the polymer residues formed around a metal gate structure are removed by sequentially applying aggressive chemistries to the surface of the substrate.
- the aggressive chemistries are applied in a very controlled manner so as to enable optimal removal of the polymer residue contaminants from around the gate structure while preserving the structural integrity of the gate structure.
- a plurality of process parameters associated with the gate structure and the polymer residue are determined.
- the process parameters are obtained by analyzing the plurality of fabrication layers forming the gate structure and the various types of polymer residues formed around the gate structure feature.
- the process parameters define one or more characteristics associated with the different layers of the gate structure and the polymer residue.
- a first and a second aggressive chemistry are identified and one or more application parameters are defined for the identified aggressive chemistries based on the process parameters.
- the application parameters are used in applying the aggressive chemistries sequentially in a controlled manner so that optimal removal of polymer residues is enabled without losing the structural integrity of the gate structure.
- FIG. 1 illustrates a simplified schematic diagram of a gate structure, in one embodiment of the invention.
- the gate structure is formed using a plurality of fabrication layers where fabrication materials are deposited over a surface of a substrate 100.
- the fabrication layers may include one or more layers of metal 120, 122 formed over a layer of gate oxide 115 on the surface of a substrate 100.
- the gate oxide layer 115 is usually a high dielectric constant film layer formed over the source/drain 105.
- Layers of metals are used to form a metal electrode.
- two layers of metal, Metal 1 120 and Metal 2 122, are used in forming the metal electrode.
- Some of the metals that are used for forming the metal electrode include Tungsten (W), Tungsten Suicide, Tungsten Nitride, Tantalum, poly-silicon (doped or undoped), Silicon Oxide (SiO 2 ) Tantalum Nitride (TaN), Hafnium Oxide, Aluminum Oxide, Nitrided Hafnium-silicate (HfSiON), etc.
- a polysilicon layer 125 is formed over the metals.
- a hardmask layer 130 is formed over the polysilicon layer 130.
- the hardmask layer 130 may be made up of a plurality of layers of hardmask 130, 132, 134. Typical materials used to form hardmask layers include Silicon Nitride, Silicon Oxide, etc.
- the hardmask layer is formed as a photoresist layer and is used to protect the underlying layers during an etching operation. During the etching operation, the etching chemicals used to define the metal gate structure will leave polymer residue contaminants 140 and metal containing polymer residue contaminants 142 on top and along the sidewalls of the metal gate structure. It is essential to remove the unwanted polymer residue contaminants 140, 142 while preserving the characteristics of the metal gate structure.
- the gate structure illustrated in Figure 1 is one example of a gate structure formed over the substrate. Variations of the gate structure are possible.
- Figures 3A-3D illustrate some variations of the gate structure illustrated in Figure 1.
- Figure 3 A illustrates a DRAM gate structure after a full etch.
- a gate stack of the gate structure includes a gate oxide 115 formed over a silicon substrate 100.
- a poly silicon layer 125 is formed over the gate oxide 1 15 followed by a layer of metal 1 120 and a layer of metal 2 122.
- a hardmask layer 130 is formed over the metal 2 layer.
- post-etch polymer residues 140 and metal containing polymer residues 142 form around the gate structure.
- Figure 3B illustrates a variation of the gate structure shown in Figure 3 A.
- the gate structure in Figure 3B is formed as a result of an open etch process with the poly silicon layer 125 formed over the entirety of the gate oxide 115 and the gate stack is formed over a portion of the poly silicon layer 125.
- Figure 3C illustrates an embodiment of a flash tungsten metal gate structure formed over the silicon substrate 100.
- the gate stack of the gate structure includes a gate oxide 1 15 formed over the substrate.
- a protective layer of silicon nitride 152 is formed over the gate oxide 115.
- Layers of metal 1, 120, metal 2, 122 and metal 3, 124, are formed on top of the silicon nitride layer 152.
- a hardmask layer 130 is formed on top of the metal layer 124.
- Figure 3D illustrates a post-etch gate structure formed over the silicon substrate 100, in one embodiment of the invention.
- a high dielectric constant film layer 115 is formed over the silicon substrate, a plurality of metal layers, such as a layer of metal 2, 122, and metal 1, 120, are formed over the high dielectric constant film layer 1 15.
- the metal layers may be tungsten or tantalum based metal layers, such as tungsten, tungsten suicide, tantalum, tantalum nitride, etc.
- a layer of poly silicon 125 is formed on top of the metal layers.
- a hardmask layer is formed. The various chemicals used in the etching operation deposit around the gate features as polymer residues 140.
- FIG. 2 illustrates one such example of potential cleaning issues of mask pullback and undercut to the metal layers due to metal corrosion, when the traditional cleaning tools were used.
- Figure 3E illustrates another potential cleaning issue when a batch tool is used during cleaning operation.
- a batch tool such as an immersion tank tool, (for example, Process of Record (POR) tank tool, is used to effectively remove the polymer residue contaminants.
- the batch tool exposes the substrate with the associated gate structure to the cleaning chemistry for effective removal of the polymer residue.
- POR Process of Record
- Using a less aggressive chemistry in the tank tool leads to inefficient cleaning process.
- the gate structure experiences high material loss, as illustrated in Figure 3E.
- the aggressive chemistry used to dissolve the metal containing polymer residue contaminant will also react with the hardmask layer severely eroding the hardmask layer thereby exposing the underlying layers of the gate structure to the aggressive cleaning chemistries during cleaning and post-cleaning process.
- the exposed layers of the gate structure may undergo severe damage from the aggressive cleaning and other fabrication chemicals resulting in a damaged or inoperable gate structure.
- Figures 4A-4C illustrate the cleaning results desired from a cleaning operation for various gate structures depicted in Figures 3A-3C.
- the expected desired result preserves the various fabrication layers of the gate structure while effectively removing the polymer residue contaminants from around the gate structure.
- Figure 4A illustrates the desired result expected after a cleaning operation for a full-etch gate structure illustrated in Figure 3 A
- Figure 4B illustrates the desired cleaning result for a open-etch gate structure illustrated in Figure 3B
- Figure 4C illustrates the desired cleaning result for a tungsten metal gate structure illustrated in Figure 3C.
- the desired results require effective removal of the polymer residue contaminants, including the metal containing residues, without damaging any of the fabrication layers.
- Figure 5 illustrates a system 500 within a clean room used to introduce a first cleaning chemistry and a second cleaning chemistry to a surface of a substrate 100 in a controlled manner to substantially remove polymer residues deposited around metal gate structures, in one embodiment of the invention.
- the system 500 includes a housing chamber 510 having a substrate supporting device, such as a carrier 550, to receive, support and transport a substrate through the housing chamber 510 on a selected plane.
- the substrate 100 is received at the substrate input region 515, transported through a region with one or more sets of proximity heads 545 and 555 and delivered to the substrate output region 560.
- the embodiment of Figure 5 shows a pair of proximity heads positioned on either side of the selected plane through which the substrate 100 is transported, to deliver the first and second cleaning chemistries to both sides of the substrate 100. It should be noted that this configuration of proximity heads is exemplary and should not be construed as limiting. As a result, other combinations and configurations of proximity heads may also be considered for effective cleaning of the substrate 100.
- the first set of proximity heads 545 are used to apply a first cleaning chemistry and the second set of proximity heads 555 are used to apply a second cleaning chemistry, respectively, as menisci to the surface of the substrate during a post-etch cleaning operation.
- the term, "meniscus,” as used herein, refers to a volume of liquid bounded and contained in part by surface tension of the liquid.
- the meniscus, defining a contained chemical region, is controllable and can be moved over a surface in the contained shape.
- the meniscus shape can be controlled through a computing system 505 connected to the proximity heads 545 and 555.
- the system 510 may include reservoirs 525 and 530 to receive, hold and supply the first and second cleaning chemistries to the proximity heads, 545 and 555.
- a chemistry application mechanism 520 connected to the reservoirs 525 and 530 control the flow of the first and second cleaning chemistries through the proximity heads 545 and 555.
- the chemistry application mechanism 520 may include one or more precision controls to enable controlled delivery of the first and second cleaning chemistries to the proximity heads 545 and 555.
- the precision controls may be remotely controlled by the computing system 505.
- Software in the computing system 505 may be used to manipulate the precision controls such that proper amount of first and second application chemistries are supplied to the proximity heads at appropriate stages of the cleaning process.
- a plurality of process parameters associated with the various fabrication layers and the polymer residue contaminants is used to manipulate the delivery controls so that adequate amounts of the first and second cleaning chemistries are delivered to the proximity heads.
- the application of the first and second cleaning chemistries is based on the plurality of process parameters.
- the process parameters are obtained by analyzing various fabrication layers that form the gate structure and the polymer residues that need to be removed.
- the process parameters define characteristics of each of the fabrication layers and the polymer residue.
- Some of the process parameters associated with each of the fabrication layers at the gate structure include one or more of type, size, and composition.
- Some of the process parameters associated with the polymer residue removal may include chemistry type, concentration, temperature, exposure time, and target removal rate on semiconductor materials used in the process of gate manufacturing.
- Some of the semiconductor materials used in the process of gate manufacturing may include Silicon oxide (SiO 2 ), Tungsten (W), Tungsten suicide, Tungsten Nitride, Tantalum Nitride, Tantalum, and others.
- the first cleaning chemistry and second cleaning chemistry are selected based on the process parameters so that the polymer residue contaminants are effectively and substantially removed without damaging the gate structure feature.
- the process parameters associated with the fabrication layers and polymer residues may vary from one substrate to the next. It is essential to preserve the gate structure formed on the surface of the substrate during the cleaning operation so that the functionality of the gate structure and that of the semiconductor device is maintained.
- the first and second cleaning chemistries that are selected based on process parameters are aggressive chemistries that are normally not used in traditional tools during the cleaning operation. These aggressive chemistries are known to cause considerable damage to the features formed on the substrate 100 when exposed over an extended period of time. However, these aggressive chemistries facilitate effective removal of polymer residues formed around the gate structures when applied in a controlled manner for a limited amount of time.
- the first cleaning chemistry is ammonium peroxide mixture (APM) and the second cleaning chemistry is diluted Hydrofluoric acid (dHF).
- APM is an effective cleaning chemistry as it is known to interact with metal containing polymer residues effectively removing them from around features formed on the substrate.
- APM is also known to be an aggressive chemistry with high removal rates for tungsten and tungsten containing compounds making it difficult to use it as an effective cleaning chemistry for cleaning tungsten containing device stacks, such as the gate structures, in conventional batch cleaning tools.
- the first and second cleaning chemistries are applied in a very controlled manner using the proximity heads 545 and 555, respectively, so as to limit the exposure of the surface of the substrate to the cleaning chemistries.
- the length and precise exposure time using proximity heads may be driven by a desired target removal rate of the polymer residue so as to enable one to define acceptable amount of metal film loss in the fabrication layers of the feature during APM application.
- one or more application parameters are defined for each of the first and second cleaning chemistries based on the process parameters associated with the various fabrication layers of the features, such as gate structures, and the polymer residue contaminants.
- Some of the application parameters that may be defined for each of the first and second cleaning chemistries may include chemistry type, the order of application of first and second cleaning chemistry, concentration, exposure time, temperature, pressure, and flow rate.
- exposure time may be further defined as a function of linear speed at which the substrate is transported under the proximity heads and the width of the meniscus that may be applied to the surface of the substrate.
- F(t exposure time) f (Meniscus Width/surface area, substrate linear speed).
- the linear speed of the wafer may be controlled using mechanical devices such as a motor.
- the linear speed of the substrate may be adjusted to about 20 mm/sec to give an exposure time for the application of first cleaning chemistry of 1 second.
- the linear speed of the substrate under the proximity heads may be adjusted accordingly using the motor.
- first and second cleaning chemistries are applied to the surface of the substrate sequentially in a controlled manner using the first and second proximity heads, 545 and 555, based on the application parameters.
- the order of the application of the cleaning chemistries is not rigid.
- first cleaning chemistry (APM) is applied using the first proximity head 545 followed by the application of the second cleaning chemistry (dHF) using the second proximity head 555.
- the first cleaning chemistry (APM) is applied using the second proximity head 555 sequentially after the application of the second cleaning chemistry (dHF) using the first proximity head 545.
- the order of application of the cleaning chemistries might be based on desired outcomes, such as the amount of metal oxide to be preserved.
- the controlled sequential application of the first and second cleaning chemistries aid in substantial removal of the polymer residue from around features, such as gate structures, without damaging the features.
- the exposure time of each of the cleaning chemistries is controlled by controlling the linear speed of the substrate under the corresponding proximity heads.
- each of the first and second cleaning chemistries may be followed by a rinsing operation using a rinsing chemistry.
- the rinsing chemistry is used to remove any residual cleaning chemistry applied to the substrate surface after the respective cleaning operation. Consequently, the order of treatment of various chemistries, in one embodiment of the invention, may include application of first cleaning chemistry, rinsing operation with a rinsing chemistry, application of second cleaning chemistry and rinsing operation with a rinsing chemistry.
- the rinsing operation following the application of each of the first and second cleaning chemistries may use the same rinsing chemistry or different rinsing chemistries.
- the first and second proximity heads (545, 555) are configured to deliver the cleaning chemistry and the rinsing chemistry as menisci to clean and rinse the surface of the substrate.
- the cleaning chemistry and rinsing chemistry menisci may be connected or separated. In one embodiment, the cleaning chemistries and rinsing chemistry menisci are connected.
- the proximity heads (545, 555) are configured to enable connection between the cleaning chemistry meniscus and rinsing chemistry meniscus. In this embodiment, the applied cleaning chemistries are used once and not reclaimed after the application. In another embodiment, the cleaning chemistries and rinsing chemistry menisci are separate.
- each of the proximity heads (545, 555) is configured such that the cleaning chemistry meniscus is kept distinct from the rinsing chemistry meniscus. Accordingly, in this embodiment, the applied cleaning chemistry can be reclaimed after application for re-use in subsequent cleaning operations.
- Each of the first and second proximity heads, 545, 555 is further configured to provide a drying operation to dry the surface of the substrate after the cleaning and rinsing operations, in one embodiment of the invention.
- the drying operation may include application of a drying chemistry, such as isopropyl alcohol (IPA) vapor, to the substrate surface.
- IPA isopropyl alcohol
- the drying operation is optional after the first cleaning and rinsing operation.
- DIW de-ionized water
- the drying operation is, however, included after the second cleaning and rinsing operation.
- the substrate is made to move radially under the proximity heads (545, 555), to ensure even application of various chemistries to all portions of the substrate surface.
- the size of the proximity heads is smaller than the width of the substrate. The speed of rotation of the substrate underneath the proximity heads is adjusted based on desired exposure time and the target removal rate of the polymer residue.
- the proximity heads are configured to have a head that is slightly larger than the diameter of the substrate so as to provide a more localized application of the cleaning chemistries with short exposure time.
- the substrate is moving linearly under the proximity heads.
- the short exposure time using proximity heads allows use of concentrated and aggressive chemistries in the cleaning process.
- the high flow conditions of the aggressive chemistries and the subsequent displacement with rinsing chemistries enables faster reaction with the polymer residue contaminants and faster suspension of the reaction thereby enabling optimal removal of the polymer residue contaminants while minimizing the exposure of the features to the aggressive chemistries thereby preventing pullback and undercut of fabrication layers of the features, such as the gate structures during the cleaning process.
- APM can be used to remove metal polymer residues around a metal gate structure where tungsten/tungsten compound is used.
- FIGs 6A, 6B and 7 illustrate charts 1, 2, and 3, respectively, depicting the residue cleaning rate with minimum oxide layer loss.
- the concentration of the APM may be adjusted to provide an etch rate of about 1 A/sec to about 10 A/sec with an optimal etch rate of about 5 A/sec.
- the material loss in the gate structure can be between about 5 A and about 10 A with about 5 second exposure time.
- the concentration of the APM and the exposure time may be adjusted to obtain acceptable range of polymer residue removal while maintaining low material loss of the gate structure material.
- the exposure time can be adjusted using precision controls to fine tune the exposure time to an order of about +0.1 seconds.
- a typical range of the composition of APM could be in the order of about 1: 1 :1 on the concentrated side to about 1:4:50 on the diluted side with a standard concentration of about 1 :4: 10.
- the range of concentration could be between about 1 : 10 on the concentrated side to about 1 : 1000 for diluted side with a standard concentration of about 1 :100.
- the standard exposure time would be about 2 seconds with a range between about 1 second to about 20 second.
- the speed of the substrate may be adjusted to provide the required exposure time.
- the proximity head width could be between about 10mm to about 40mm and the speed of the substrate could be adjusted to the required exposure time.
- Figure 8 illustrates a graph of the target exposure time to carrier speed for effective removal of polymer residue contaminants.
- the graph illustrated in Figure 8 depicts the scanning speed against exposure time for effective removal of the polymer residue contaminants with two different proximity head widths.
- the graph identifies the target removal rate of the polymer residue. Based on the desired removal rate, the concentration of the first and second application chemistries, speed of the substrate under the proximity heads and exposure time can be adjusted. For instance, if it is desired to remove 5 A of tungsten based residue, the graph identifies the optimal exposure time and speed of the substrate to achieve that goal.
- Figures 3D, 3E and 4D illustrate the resultant metal gate structure before and after a cleaning operation is performed, in one embodiment of the invention.
- Figure 3D illustrates a typical gate structure with polymer residue contaminants formed around the gate structure.
- Figure 3E illustrates the result of a traditional cleaning operation using aggressive chemistries. The polymer residue on top of a hardmask layer is stripped with severe erosion of hardmask layer, thereby exposing the underlying layers.
- Figure 4D illustrates the result after a cleaning operation using the first and second cleaning chemistries of the present invention.
- the precise delivery and controlled exposure of the first and second cleaning chemistries to the substrate surface enables efficient removal of the polymer residue formed on top of the hardmask without causing any negative effects on the hardmask layer. Additionally, the controlled exposure of the cleaning chemistries enables removal of the polymer residue formed on the sidewalls of the metal gate structure while substantially preserving the metal layers of the gate structure.
- Figure 9 illustrates the process operations involved in removing polymer residue from around a metal gate structure during post-etch cleaning operation, in one embodiment of the invention.
- the process begins at operation 910, wherein a plurality of process parameters associated with the metal gate structure and polymer residue formed around the metal gate structure, are determined.
- the metal gate structure may be a multi-layer structure formed using various fabrication operations.
- the process parameters are obtained by analyzing the fabrication layers that form the gate structure and by analyzing the polymer residue formed around the gate structure.
- the process parameters may include type, size, composition, temperature associated with each of the fabrication layers and of the polymer residue and target removal rate associated with the polymer residue to be removed.
- the process parameters define characteristics of each of the fabrication layers that comprise the gate structure and the polymer residue to be removed.
- a first cleaning chemistry and second cleaning chemistry are identified based on the process parameters, as illustrated in operation 920.
- the first and second cleaning chemistry may be aggressive cleaning chemistries and may include Ammonium peroxide mixture (APM) and dilute Hydrofluoric acid (dHF).
- APM Ammonium peroxide mixture
- dHF dilute Hydrofluoric acid
- the examples for first and second cleaning chemistry are exemplary and are not restricted to APM and dHF but may include other aggressive chemistries that are known to dissolve or effectively react to substantially remove the metal polymer residues.
- Some of the other aggressive chemistries that may be used as cleaning chemistries may include, for example, a mixture of Hydrofluoric and Hydrochloric acids (HF/HC1).
- a plurality of application parameters associated with the first and second cleaning chemistries are defined based on the plurality of process parameters, as illustrated in operation 930.
- Some of the application parameters associated with each of the first and second cleaning chemistries may include type, concentration, exposure time, temperature, pressure, and flow rate.
- the application parameters may include speed of the substrate under a first and a second set of proximity heads and the width of the meniscus at each proximity head.
- the exposure time may be calculated as a function of the speed of the substrate and the width of the meniscus at each proximity head.
- the application parameters are defined based on the target removal rate of the polymer residue from around the metal gate structure.
- the process concludes with the application of the first and second cleaning chemistries sequentially in a controlled manner using the application parameters, as illustrated in operation 940.
- the application of the first and second cleaning chemistries enables substantial removal of the polymer residue from around the metal gate structure while substantially preserving the structural integrity of the metal gate structure.
- the application of the first and second cleaning chemistries may be accomplished through a computing system that is communicatively connected to the first and second proximity heads.
- One or more precision controls available at a chemistry application mechanism communicatively connected to the proximity heads, may be manipulated using a software in the computing system to enable controlled application of the first and second cleaning chemistries so as to optimally remove the polymer residue from around the metal gate structure on the surface of the substrate while substantially preserving the structural integrity of the one or more fabrication layers that make up the gate structure.
- the applied cleaning chemistries may be reclaimed so that they can be re-used in subsequent cleaning operations thereby enabling optimal use of the simple but expensive cleaning chemistries.
- the various embodiments of the invention provide ways to remove polymer residues from around metal gate structures while preserving the structural integrity of the metal gate structure using aggressive chemistries that are known to easily dissolve the metal used in the metal gate structures.
Landscapes
- Cleaning Or Drying Semiconductors (AREA)
- Cleaning In General (AREA)
- Cleaning By Liquid Or Steam (AREA)
- Weting (AREA)
Abstract
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020117008695A KR101291346B1 (en) | 2008-09-17 | 2009-07-13 | Method and apparatus for surface treatment of semiconductor substrates using sequential chemical applications |
| JP2011527795A JP5331888B2 (en) | 2008-09-17 | 2009-07-13 | Method and apparatus for surface treatment of semiconductor substrates using sequential application of chemicals |
| CN200980137280.8A CN102160150B (en) | 2008-09-17 | 2009-07-13 | Method and apparatus for surface treatment of semiconductor substrates using sequential chemical applications |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/212,559 US8652266B2 (en) | 2008-07-24 | 2008-09-17 | Method and apparatus for surface treatment of semiconductor substrates using sequential chemical applications |
| US12/212,559 | 2008-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2010033144A1 true WO2010033144A1 (en) | 2010-03-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2009/004080 Ceased WO2010033144A1 (en) | 2008-09-17 | 2009-07-13 | Method and apparatus for surface treatment of semiconductor substrates using sequential chemical applications |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US8652266B2 (en) |
| JP (1) | JP5331888B2 (en) |
| KR (1) | KR101291346B1 (en) |
| CN (1) | CN102160150B (en) |
| WO (1) | WO2010033144A1 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120100721A1 (en) * | 2009-06-25 | 2012-04-26 | Lam Research Ag | Method for treating a semiconductor wafer |
| US8492891B2 (en) * | 2010-04-22 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with electrolytic metal sidewall protection |
| US8394667B2 (en) | 2010-07-14 | 2013-03-12 | Micron Technology, Inc. | Methods of forming memory cells, and methods of patterning chalcogenide-containing stacks |
| DE102010042229B4 (en) * | 2010-10-08 | 2012-10-25 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | A method for increasing the integrity of a high-k gate stack by creating a controlled sub-cavity based on wet chemistry and transistor produced by the methods |
| US20120260517A1 (en) * | 2011-04-18 | 2012-10-18 | Lam Research Corporation | Apparatus and Method for Reducing Substrate Pattern Collapse During Drying Operations |
| JP2013080904A (en) * | 2011-09-22 | 2013-05-02 | Hoya Corp | Substrate manufacturing method, wiring board manufacturing method, glass substrate, and wiring board |
| US8603837B1 (en) * | 2012-07-31 | 2013-12-10 | Intermolecular, Inc. | High productivity combinatorial workflow for post gate etch clean development |
| KR20140018746A (en) * | 2012-08-03 | 2014-02-13 | 삼성전자주식회사 | Substrate treating method and apparatus thereof |
| US8871107B2 (en) * | 2013-03-15 | 2014-10-28 | International Business Machines Corporation | Subtractive plasma etching of a blanket layer of metal or metal alloy |
| US20150079786A1 (en) * | 2013-09-17 | 2015-03-19 | Lam Research Corporation | Method and solution for cleaning metal residue |
| DE102015221646A1 (en) * | 2015-11-04 | 2017-05-04 | Gebr. Schmid Gmbh | Treatment fluid suction device and etching device containing the same |
| KR102098137B1 (en) * | 2016-04-15 | 2020-04-08 | 가부시키가이샤 덴소 | System and method for setting real-time location |
| CN109585315B (en) * | 2017-09-29 | 2020-11-03 | 联华电子股份有限公司 | Method of making a semiconductor structure |
| US10217815B1 (en) | 2017-10-30 | 2019-02-26 | Taiwan Semiconductor Manufacturing Co., Ltd | Integrated circuit device with source/drain barrier |
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| JP2000183018A (en) * | 1998-12-14 | 2000-06-30 | Nec Corp | Cleaning method and device of semiconductor substrate |
| JP2000262995A (en) * | 1999-03-17 | 2000-09-26 | Sumitomo Heavy Ind Ltd | Aerosol cleaning apparatus and multi-stage cleaning method using the same |
| JP2008028175A (en) * | 2006-07-21 | 2008-02-07 | Fujifilm Corp | Wafer cleaning equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6129091A (en) * | 1996-10-04 | 2000-10-10 | Taiwan Semiconductor Manfacturing Company | Method for cleaning silicon wafers with deep trenches |
| US7000622B2 (en) * | 2002-09-30 | 2006-02-21 | Lam Research Corporation | Methods and systems for processing a bevel edge of a substrate using a dynamic liquid meniscus |
| US6584989B2 (en) * | 2001-04-17 | 2003-07-01 | International Business Machines Corporation | Apparatus and method for wet cleaning |
| US7329321B2 (en) * | 2002-09-30 | 2008-02-12 | Lam Research Corporation | Enhanced wafer cleaning method |
| JP2005183937A (en) * | 2003-11-25 | 2005-07-07 | Nec Electronics Corp | Semiconductor device manufacturing method and resist removal cleaning apparatus |
| WO2007058286A1 (en) * | 2005-11-18 | 2007-05-24 | Mitsubishi Gas Chemical Company, Inc. | Method and apparatus for cleaning substrate |
-
2008
- 2008-09-17 US US12/212,559 patent/US8652266B2/en not_active Expired - Fee Related
-
2009
- 2009-07-13 JP JP2011527795A patent/JP5331888B2/en not_active Expired - Fee Related
- 2009-07-13 WO PCT/US2009/004080 patent/WO2010033144A1/en not_active Ceased
- 2009-07-13 KR KR1020117008695A patent/KR101291346B1/en not_active Expired - Fee Related
- 2009-07-13 CN CN200980137280.8A patent/CN102160150B/en not_active Expired - Fee Related
-
2013
- 2013-12-31 US US14/145,901 patent/US20140116476A1/en not_active Abandoned
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000183018A (en) * | 1998-12-14 | 2000-06-30 | Nec Corp | Cleaning method and device of semiconductor substrate |
| JP2000262995A (en) * | 1999-03-17 | 2000-09-26 | Sumitomo Heavy Ind Ltd | Aerosol cleaning apparatus and multi-stage cleaning method using the same |
| JP2008028175A (en) * | 2006-07-21 | 2008-02-07 | Fujifilm Corp | Wafer cleaning equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| US20100018553A1 (en) | 2010-01-28 |
| US20140116476A1 (en) | 2014-05-01 |
| KR20110063832A (en) | 2011-06-14 |
| CN102160150A (en) | 2011-08-17 |
| KR101291346B1 (en) | 2013-07-30 |
| JP2012503328A (en) | 2012-02-02 |
| US8652266B2 (en) | 2014-02-18 |
| CN102160150B (en) | 2014-08-20 |
| JP5331888B2 (en) | 2013-10-30 |
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