WO2010031840A1

WO2010031840A1 - Methods for the reduction of difference in phase following disconnection of a phase locked loop and devices implementing such methods

Info

Publication number: WO2010031840A1
Application number: PCT/EP2009/062119
Authority: WO
Inventors: Thierry Tapie; Serge Defrance; Louis Chevallier
Original assignee: Thomson Licensing
Priority date: 2008-09-22
Filing date: 2009-09-18
Publication date: 2010-03-25

Abstract

The present invention relates, according to a first aspect, a method for reduction of the difference in phase between a first signal and a second signal, a phase locked loop PLL₁ receiving the samples PCR_r from the first signal and producing local samples PCR_loc₁ from the second signal, said loop PLL₁ also producing a second signal from a difference ε between the samples received PCR_r and the local samples PCR_loc₁, parameters ADDEND from the phase locked loop being initialized and modified during the functioning. According to the invention, when the phase locked loop PLL1 functions in a regime established during a first connection, it comprises: - a step 10 of acquisition of at least one value Val1, Val2 of at least one parameter ADDEND of the phase locked loop PLL₁ as well as a timestamp t1, t2 at which the acquisition was realized, - a step 20 of memorization of the value Val1, Val2 of the parameter or parameters ADDEND in a database.

Description

METHODS FOR THE REDUCTION OF DIFFERENCE IN PHASE FOLLOWING

DISCONNECTION OF A PHASE LOCKED LOOP AND DEVICES

IMPLEMENTING SUCH METHODS

Scope of the invention

The present invention relates to the domain of Phase Locked Loops.

The present invention relates more specifically to methods for the reduction of phase difference between a first signal and a second signal when the samples of the first signal are received by a phase locked loop and the second signal is generated by the phase locked loop from a difference between the received samples and the local samples of the second signal. This phase difference has a heightened amplitude in the instants following a disconnection and a reconnection of the phase lock loop. This invention is particularly useful when the phase locked loop is used in a reception device to synchronise the equipment connected by a packet switching network. The invention also relates to devices implementing such methods.

Prior art

Progress in the ability of IP networks to transport all types of signal (data or video) has made it possible to use these networks as the "backbone" architecture for video studios. Of capital importance to this change is therefore having a single infrastructure for the transport of data. Whereas in the past, several media were necessary to transport different signal types between items of equipment, the multiplexing properties offered by the IP layer enable a reduction in the number of media necessary: an IP network that links the different items of equipment.

In the prior art, the synchronisation of items of video equipment (cameras, etc.) in a studio is carried out by the transmission of a synchronisation signal commonly called "Genlock" or "Black burst". For example, the Genlock signal comprises two synchronisation signals, one is repeated every 40 ms and indicates the start of the video frame, the other is repeated every 64 μs (for a standard format and less for an HD format) and indicates the start of lines in the video frame. The waveform of the synchronisation signals depends on the format of the image transmitted over the network. For example, for a high definition image, the synchronisation signal has a tri-level form (-30OmV, OV, +300 mV).

When a synchronisation signal is routed to different items of equipment to be synchronised by a dedicated coaxial cable, a constant transmission time, without jitter is ensured. From such a signal, all items of equipment are able to reconstruct a timing clock that is specific to its functioning, which guarantees that its functioning is rigorously in phase with all the equipment connected to the same network. For example, two cameras synchronised by a Genlock signal circulating on a dedicated coaxial cable each generate a video with different contents but rigorously in frequency and in phase with one another.

In the prior art, devices are known for reconstructing, for each camera, a timing clock specific to this camera enabling the jitter to be overcome. The underlying principle of these devices is based on a high attenuation of the synchronisation signal jitter amplitude at the level of reception. In such a way, it can be guaranteed that an image generated by a camera is rigorously in phase with all of the images generated by neighbouring cameras connected to the same network.

Examples of such devices are described in the international PCT application

FR2007/050918, they act on program clock reference (PCR) signals that represent very accurate reference clock signals. These digital signals are sent to cameras across a network so that they can locally reconstruct clock signals that are in phase with the reference clock.

According to the prior art, the reception device comprises:

- means for receiving packets containing PCR_r samples realized on a first signal every T_eCh period,

- means to regenerate a first counter CSR_PCRi using a phase locked loop PLL₁, the loop PLL₁ producing a second signal from a difference between the received samples PCR_r and the local samples PCRJoC₁ of the second signal realized every T_eCh period, - means for initialising a second CPT counter every zero-crossing of said first counter CSR-PCR₁,

- means for generating image cues at every zero-crossing of the said second CPT counter, and

- means for reconstituting a synchronisation signal from said image cues. The phase-locked loop PLL₁ (Phase Locked Loop) of the reception device acts as a low-pass filter that partially attenuates the jitter present in the samples received PCR_r that have circulated on the network.

Usually, two phases are distinguished in the functioning of the loop PLL₁:

- a first phase, known as the "acquisition phase", during which the phase- locked loop PLL₁ internally produces local samples PCRJoC₁ that are very different from the received samples PCR_r. This first phase begins, with the start-up of the loop PLL₁ with a reception of samples PCR_r and ends when the local samples PCRJ0C₁ produced by the loop PCRJoci are very similar to the received samples PCR_R. During this functioning phase, the synchronisation signal reconstructed on the reception side by means of the loop PLL₁ presents a non-null phase difference with the synchronisation signal on the transmission side,

- a second phase, known as the "continuation phase" begins at the end of the acquisition phase and ends when a difference of reduced amplitude between the local samples PCRJoC₁ and the received samples PCR_r is detected. The criteria following which a difference is considered to have a reduced amplitude can for example be a threshold value of amplitude difference. During this second functioning phase, a reconstructed synchronisation signal on the reception side is perfectly in phase with the synchronisation signal on the transmission side.

A disadvantage of the reception devices of the prior art is that during the acquisition phase, the phase difference between the synchronization signal reconstructed on the reception side and the synchronization signal on the transmission side presents an elevated amplitude. It is particularly sensitive at the start-up of the acquisition phase. In fact, if the amplitude of the phase difference decreases with time during the acquisition phase, it creates an imprecision between the synchronization signals that is all the more heightened as the amplitude of the phase difference is heightened. It is therefore of great interest to be able to reduce the amplitude of phase difference immediately after connection of the phase locked loop as this enables reduction of the imprecision between the synchronization signals. It can be demonstrated that the amplitude of the phase difference is an increasing function of the difference between the samples PCR_r received by the loop PLL₁ and the local samples PCRJoC₁ generated by this same loop.

One of the purposes of the present invention is to reduce the amplitude of the phase difference using the phase locked loop to select initialization parameters that are adapted so that the difference ε between the samples received and the local samples is reduced.

Summary of the invention

The technical problem that the present invention proposes to resolve is to determine from the parameters of the phase locked loop memorized while the phase locked loop functions in an established regime (or continuation phase), parameters of the phase locked loop that are adapted so that during a new connection to the network the difference ε between the samples received PCR_r and the local samples PCRJoci is reduced. For this purpose, the present invention relates, according to a first aspect, a method for reduction of the difference in phase between a first signal and a second signal, a phase locked loop PLL₁ receiving the samples PCR_r from the first signal and producing local samples PCRJoci from the second signal, said loop PLL₁ also producing a second signal from a difference ε between the samples received PCR_r and the local samples PCRJoC₁, parameters ADDEND from the phase locked loop being initialized and modified during the functioning of the phase locked loop.

According to the invention, when the phase locked loop PLL₁ functions in a regime established during a first connection, it comprises:

- a step 10 to determine a timestamp t|_Nιτi of the start of the first connection and to acquire at least two values VaM , Val2 of at least one parameter ADDEND of the phase lock loop PLL₁ as well as two timestamps t1 , t2 to which the acquisition is realized,

- a step 20 of memorization of values VaM , Val2 of the parameter or parameters ADDEND and their acquisition timestamp t1 , t2 in a memory MEM.

According to the invention, the steps 10, 20 execute successively in a loop until the first connection ends.

According to the invention, during a second connection of the phase locked loop PLL₁ following the first connection, it comprises:

- a step 40 to determine a timestamp t|_Nπ-₂ of the start of the second connection,

- a step 50 to evaluate from the value VaM , Val2, of the acquisition timestamp t1 , t2 and the timestamps of the start of the first and second connections t|_Nιτi, tiNiτ2 3 value VALiNi_T of the parameter ADDEND able to initialise the phase locked loop PLL₁ so that the difference in phase between the first signal and the second signal is reduced, and

- a step 60 to assign the evaluated value VAL|_Nιτ of the parameter ADDEND to the phase locked loop. The present invention relates, according to a second aspect, to a device comprising the means to receive samples PCR_r of a first signal, the means to evaluate a difference ε between the samples received PCR_r and the local samples

PCRJoci, the means to produce local samples PCRJoci and a second signal from the difference ε. According to the invention, it comprises:

- the means ACQ to acquire regularly, when the device functions in an established regime, at least one value VaM , Val2 of a parameter ADDEND of the device as well as a timestamp t1 , t2 to which the acquisition is realized,

- the means MEM to memorize the value or values acquired VaM , Val2 of the parameter ADDEND and the corresponding acquisition timestamp(s) t1 , t2 in a database linked to said device,

- the means AFF to evaluate from the values VaM , Val2, the acquisition timestamps t1 , t2 and the timestamps of the start of the first and second connections tiNiτi, tiNiτ2 , a value VAL|_Nιτ of the parameter ADDEND adapted to initialize the device so that the difference in phase between the first signal and the signal are reduced,

- the means AFF to assign the evaluated value VAL|_Nπ- to the parameter ADDEND of the phase locked loop.

Brief description of the drawings

The invention will be better understood from the following description of an embodiment of the invention provided as an example by referring to the annexed figures, wherein:

Figure 1 represents very diagrammatically a phase locked loop used in a known reception device, Figure 2 represents very diagrammatically a phase locked loop used in a reception device according to the invention,

Figure 3 represents a flowchart of a method according to the invention implemented by a reception device according to the invention.

Detailed description of the embodiments of the invention

Figure 1 shows a phase-locked loop architecture according to the prior art in the domain in Z. PCR_r samples of a first signal are received and compared with samples PCRJ0C₁ of a second signal. The result of this comparison is a difference ε that is used to produce the second signal.

The block H(Z) represents the combined functions of a digital parametric oscillator supplying a counter followed by a value maintenance device triggered by a top Tec_h, of a counter and a sampler. These various elements are not shown.

C(z) represente un correcteur dont Ia fonction consiste a obtenir une boucle a verrouillage de phase PLL1 dont Ia reponse impulsionnelle en boucle fermee est celle d'un filtre du deuxieme ordre. De nombreuses methodes existe pour synthetiser un tel correcteur : par exemple, une methode dite « RST » qui permet d'aboutir au correcteur decrit dans Ia demande internationale PCT/EP08/061756. Une autre methode dite de Zdan permet egalement d'obtenir ce resultat.

The corrector C(z) enables a null error speed in the sense of servo systems to be obtained, as it comprises an additional integrator that inserts itself into the chain to be integrated from the parametric oscillator. The output of corrector C(z) attacks the input of the digital VCO which is one of the constituents of the block H(z). This input is a register named ADDEND.

During a disconnection occurring while the phase locked loop is functioning in an established regime, it can be recognised that if a new connection survives very little time after the disconnection, the difference e between the samples received and the local samples is reduced if the value of the register ADDEND is unchanged, however it is important if the duration that separates the reconnection from the disconnection is great.

Figure 2 shows a device according to the invention. It differs from that of figure

1 in that it also comprises:

- the means ACQ to acquire regularly, when the device functions in an established regime, at least one value VaM , Val2 of a parameter ADDEND of the device as well as a timestamp t1 , t2 to which the acquisition is realized, - the means MEM to memorize the value or values acquired VaM , Val2 of the parameter ADDEND and the corresponding acquisition timestamp(s) t1 , t2 in the memory MEM linked to said device,

- the means DAT to determine a start timestamp of the first connection t|_Nιτi

- the means AFF to evaluate from the values VaM , Val2, the acquisition timestamps t1 , t2 and the timestamps t|_Nιτi, t|_Nιτ2 , a value VAL|_Nπ- of the parameter ADDEND adapted to initialize the device so that the difference in phase between the first signal and the signal are reduced,

- the means AFF to assign the evaluated value VAL|_Nιτ to the parameter ADDEND of the phase locked loop. For example, during the first connection the means AFF establishing a function ADEND (t) describing the value of the parameter ADDEND according to the duration separating a current timestamp t from the timestamp of the first connection tιnιt1 -

An interpolation, for example linear is realized between ordinate values vail , val2 acquired successively and their respective abscissa t1-t_ιnιti, t2-t_ιmti-

For example for a timestamp comprised between t1-t_ιnιti and t2-t_ιnιti, ADDEND(t) is equal to (t-t1 ).(Val2-Val1 ) /(t2-t1 )+Val1.

When a second connection intervenes, the means DAT determine a start timestamp of the second connection t|_Nιτ₂ of the device. The means AFF determine VAL|_Nπ- at a current timestamp t from the function,

ADEND (t-(tinit2- tinit1 )) = (t - (tinit2- tinit1 )-t1 ).(Val2-Val1 ) /(t2-t1 )+Val1

Hence, the value VAL|_Nπ- corresponds to a linear interpolation for a timestamp t so that t-tinit2 is comprised between t1-tinit1 and t2-tinit1.

Outside of this interval, the value VAL|_Nπ- corresponds to an extrapolation, here linear, of values of the parameter ADDEND measured at the first connection.

The interval considered is the first timestamp t1 at which the first value vail is acquired and the timestamp tn at which the last timestamp vain is acquired.

Advantageously, the means AFF realise an interpolation of the values VaM , Val2 to determine the initialization value ValiNiτ for a timestamp t so that t-tinit2 is less than t2-tinit1 and greater than t1-tinit1.

Advantageously, the means AFF realise an extrapolation of the values VaM , Val2 to determine the initialization value ValiNiτ for a timestamp t so that t-tinit2 is less than t1-tinit1 and greater than t2-tinit1.

Advantageously, the reception device according to the invention also comprises:

- means to determine the identity MAC1 , MAC2 of a device transmitting PCR_r samples during a first connection, - means to memorize the identity MAC1 , MAC2 in the memory (MEM) linked to said device,

- means to determine the identity MAC1 , MAC2 of a device transmitting PCR_r samples during the second connection, and - means to select from among the values memorized VaM , Val2 in the database linked to said device, the values of the parameter ADDEND that were memorized when the device acquired the PCR_r samples transmitted by the transmitter device with the identity MAC1 , MAC2.

MAC1 , MAC2 correspond for example to an address MAC (Medium Access Control) of a device but can also correspond to unique identifiers associated with a clock.

Figure 3 represents a flowchart of a method according to the invention implemented by a reception device according to the invention. The phase locked loop PLL₁ receives the samples PCR_r of a first signal and produces local samples PCRJoci of a second signal. The loop PLL₁ also produces the second signal from a difference ε between the received samples PCR_r and the local samples PCRJoC₁ of the second signal. The values of parameters ADDEND of the phase locked loop are initialized at each start-up of the phase locked loop being able to be modified during the functioning of the loop PLL₁.

Step 5 of the flowchart shows the functioning according to the prior art. During this step, sequentially, the phase locked loop PLL₁ receives a sample PCR_r and compares it with a local sample produced from the second signal. This second signal can be for example synthesized by a digital parametric oscillator. The register ADDEND is a parameter from which the frequency of the synthesized signal is determined. The ADDEND parameter is updated during a functioning of the loop PLL₁ in such a way to reduce the difference ε between the samples received and the local samples.

According to the invention, when the phase locked loop is connected, as soon as it enters into an established regime (or into continuation phase), the steps 10 and 20 are executed periodically until a disconnection occurs.

The functioning of the established regime is determined for example on the basis of a criteria of a minimum amplitude of the difference ε πεvδαvτ υvε δυpfε T. Step 10 consists in a determination of a timestamp t|_Nιτi of the start of the first connection and an acquisition of at least two values VaM , Val2 of at least a parameter ADDEND of the phase locked loop PLL₁ as well as a simultaneous acquisition of the timestamps t1 , t2 to which the acquisitions of values are realized - a step 20 of memorization of values VaM , Val2 acquired and the corresponding acquisition timestamps t1 , t2.

The steps 10 and 20 are executed periodically, until a disconnection intervenes. A disconnection originates in a rupture of supply of the device of reception or a loss of packets provisionally interrupting the functioning of the phase locked loop PLL₁.

When a connection is again possible, either because the power supply of the reception device has been re-established, or because the packets again reach the loop PLL₁ after a long interruption, the steps 40, 50 and 60 are executed sequentially until the end of the acquisition phase. At the end of the acquisition phase, the normal functioning of the loop PLL₁ restarts. This normal functioning is symbolized by step 5 already described previously.

The step 40 consists in determining a timestamp t|_Nιτ₂ of the start of the second connection. The step 50 consists in evaluating from the values memorized VaM , Val2 the acquisition timestamps t1 , t2 and the timestamps of the start of the first and second connections t|_Nιτi_> t|_Nιτ2 a value VAL|_Nπ- of the parameter ADDEND able to initialise the phase locked loop PLL₁ so that the difference in phase between the first signal and the second signal is reduced. For example at the timestamp t the value assigned to ADDEND is (t- tinit1 ).(Val2-Val1 ) /(t2-t1 )+Val1. For the values of t comprised between tinit2+t1-tinit1 et tinit2+t2-tinit1 , the value VAL|_Nπ- corresponds to an interpolation of the values vail and val2. Outside of this interval, the value corresponds to an extrapolation.

The step 60 consists in assigning the evaluated value VAL|_Nιτ of the parameter ADDEND to the phase locked loop.

Advantageously, the acquisition step 10 comprises a step to determine the identity MAC1 , MAC2 of a device transmitting the PCR_r samples during the first connection at timestamps t1 , t2.

Advantageously, the step of memorization 20 also comprises a step of memorization of the identity MAC1 , MAC2 for example in the memory MEM. Advantageously, during the second connection, the step of evaluation 50 of the value VAL|_Nπ- comprises a step to determine the identity MAC1 , MAC2 of the device transmitting the PCR_r samples and a step to select in the memory MEM the values VaM , Val2 that were memorized when the device carrying the identity MAC1 , MAC2 transmitted the PCR_r samples.

In other words, for a second connection starting with the reception of samples from a device having the identity MAC1 , the reception device according to the invention must identify the first connection as the last connection to date having been realized with samples from the device carrying the identity MAC1.

The invention is described in the preceding text as an example. It is understood that those skilled in the art are capable of producing variants of the invention without leaving the scope of the patent.

Claims

1. Method for reduction of the difference in phase between a first signal and a second signal, a phase locked loop (PLL₁) receiving the samples (PCR_r) from the first signal and producing local samples (PCRJoci) from the second signal, said loop (PLL₁) also producing a second signal from a difference (ε) between the samples received (PCR_r) and the local samples (PCRJoC₁), parameters (ADDEND) from the phase locked loop being initialized and modified during the functioning of the phase locked loop, characterized in that, when the loop (PLL₁) functions in a regime established during a first connection, it comprises: - a step (10) to determine a timestamp (t|_Nιτi) of the start of the first connection and to acquire at least two values (VaH , Val2) of at least one parameter (ADDEND) of the phase lock loop (PLL₁) as well as two timestamps (t1 , t2) at which the acquisition is realized,

- a step (20) of memorization of values (VaH , Val2) of the parameter or parameters (ADDEND) and their acquisition timestamp (t1 , t2) in a memory (MEM), and in that, during a second connection of the phase locked loop (PLL₁) following the first connection, it comprises:

- a step (40) to determine a timestamp (t|_Nιτ2) of the start of the second connection, - a step (50) to evaluate from the value (VaH , Val2), of the acquisition timestamp (t1 , t2) and the timestamps of the start of the first and second connections (t|_Nιτi_> t|_Nιτ2) a value (VAL|_Nπ-) of the parameter (ADDEND) able to initialise the phase locked loop (PLL₁) so that the difference in phase between the first signal and the second signal is reduced, and - a step (60) to assign the evaluated value (VAL|_Nπ-) of the parameter

(ADDEND) to the phase locked loop.

2. Method according to claim 1 , characterized in that steps (10, 20) execute successively in a loop until the first connection ends.

3. Method according to claim 2, characterized in that the acquisition step (10) comprises a step to determine an identity (MAC1 , MAC2) of a device transmitting PCR_r samples during the first connection at timestamp (t1 , t2) in that the memorization step (20) also comprises a step of memorization on the identity (MAC1 , MAC2), and in that during the second connection, the step of evaluation (50) of the value (VAL|_Nπ-) comprises a step to determine the identity (MAC1 , MAC2) of the device transmitting the PCR_r samples and a step to select in the memory (MEM) the values VaM , Val2) that were memorized when the device carrying the identity (MAC1 , MAC2) transmitted the PCR_r samples.

4. Reception device comprising the means to receive samples (PCR_r) of a first signal, the means to evaluate a difference (ε) between the samples received (PCR_r) and the local samples (PCRJoci), the means to produce local samples (PCRJoci) and a second signal from the difference (ε), characterized in that it comprises:

- the means (ACQ) to acquire regularly, when the device functions in an established regime, at least one value (VaH , Val2) of a parameter (ADDEND) of the device as well as a timestamp (t1 , t2) at which the acquisition is realized,

- the means (MEM) to memorize the value or values acquired (VaH , Val2) of the parameter (ADDEND) and the corresponding acquisition timestamp(s) (t1 , t2) in the memory linked to said device,

- the means (DAT) to determine a start timestamp of the second connection (tiNiτ2) of the device,

- the means (AFF) to evaluate from the values (VaH , Val2), the acquisition timestamps (t1 , t2) and the timestamps of the start of the first and second connections (t|_Nιτi, tiNiτ2)_> a value (VAL|_Nπ-) of the parameter (ADDEND) adapted to initialize the device so that the difference in phase between the first signal and the signal are reduced,

- the means (AFF) to assign the evaluated value (VAL|_Nιτ) to the parameter (ADDEND) of the phase locked loop.

5. Reception device according to the preceding claim characterized in that it also comprises:

- means to determine the identity (MAC1 , MAC2) of a device transmitting (PCR_r) samples during a first connection, - means to memorize the identity (MAC1 , MAC2) in the memory (MEM) linked to said device,

- means to determine the identity (MAC1 , MAC2) of a device transmitting (PCR_r) samples during the second connection, and - means to select from among the values memorized (VaH , Val2) in the database linked to said device, the values of the parameter (ADDEND) that were memorized when the device acquired the (PCR_r) samples transmitted by the transmitter device with the identity (MAC1 , MAC2).

6. Reception device according to the preceding claim, characterized in that the identity is the address MAC of the transmitter device.

7. Reception device according to one of claims 4 to 6, characterized in that the means (AFF) realizing an interpolation of the values (VaH , Val2) to determine the initialization value (Val|_Nιτ) for a timestamp t so that t-tinit2 is less than t2- tiniti and greater than t1-tinit1.

8. Reception device according to one of claims 4 to 7, characterized in that the means (AFF) realizing an extrapolation of the values (VaH , Val2) to determine the initialization value (ValiNiτ) for a timestamp t so that t-tinit2 is less than t1- tiniti and greater than t2-tinit1.