WO2010024914A1 - System and method for reusing dvb-s2 ldpc codes in dvb-c2 - Google Patents

System and method for reusing dvb-s2 ldpc codes in dvb-c2 Download PDF

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Publication number
WO2010024914A1
WO2010024914A1 PCT/US2009/004888 US2009004888W WO2010024914A1 WO 2010024914 A1 WO2010024914 A1 WO 2010024914A1 US 2009004888 W US2009004888 W US 2009004888W WO 2010024914 A1 WO2010024914 A1 WO 2010024914A1
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WIPO (PCT)
Prior art keywords
bit
pointer
blockwise
multiples
cyclic shift
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PCT/US2009/004888
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French (fr)
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Jing LEI
Wen Gao
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Thomson Licensing
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Publication of WO2010024914A1 publication Critical patent/WO2010024914A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H03M13/356—Unequal error protection [UEP]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]

Definitions

  • the present invention relates to systems and methods for digital video broadcasting, and more particularly to systems and methods using DVB-S2 LDPC codes for DVB-C2 broadcasting .
  • ETSI European Telecommunications Standards Institute
  • DVB-S2 Digital Video Broadcasting Satellite - Second Generation
  • LDPC Low Density Parity Check
  • PSK phase shift keying
  • the ETSI announced the development of the Digital Video Broadcasting - Cable - Second Generation (DVB-C2) standard for terrestrial cable broadcasting.
  • This new standard is also set to use LDPC codes, but has very high demands for spectral efficiency, and as such will use high-order Quadrature Amplitude Modulation (QAM) (e.g., as high as 4096-QAM) .
  • QAM Quadrature Amplitude Modulation
  • DVB-S2 LDPC codes for error correction in DVB-C2, thereby saving significant effort in design as well as significant cost in implementation.
  • the DVB-S2 codes, and the bit interleavers designed for use with those codes were not designed for high-order modulations .
  • a method for transmitting information reliably includes encoding data with a code that has varying levels of bit protection, interleaving the encoded data with an interleaver in accordance with varying levels of capacity in a modulation scheme, and modulating the data according to the modulation scheme.
  • the step of interleaving further includes block interleaving parity bits such that vulnerable bits are collected into blocks and block allocating information and parity bits into bit pipes such that less reliable bits are matched with more highly protected bit positions in the modulation scheme.
  • a system for transmitting information reliably includes an encoder configured to encode data with a code that has varying levels of bit protection, an interleaver configured to interleave the encoded data in accordance with varying levels of capacity in a modulation scheme, and a modulator configured to modulate the data according to the modulation scheme.
  • the interleaver includes a block interleaver configured to interleave parity bits such that vulnerable bits are collected into blocks and a block allocator configured to allocate information and parity bits into bit pipes such that less reliable bits are matched with more highly protected bit positions in the modulation scheme
  • a DVB-C2 system which employs DVB-S2 LDPC codes includes an encoder configured to encode data with a DVB-S2 LDPC code, an interleaver configured to interleave the encoded data in accordance with the varying levels of capacity in a Binary Reflected Gray Code (BRGC) labeled QAM scheme, and a modulator configured to modulate the data according to the QAM scheme .
  • BRGC Binary Reflected Gray Code
  • FIG. 1 is a block diagram of a system/method for communicating data using LDPC codes over quadrature amplitude modulation (QAM) .
  • QAM quadrature amplitude modulation
  • FIG. 2 is a graph showing the capacity of various bit levels at various signal-to-noise ratios (SNRs) for uniform 256-QAM.
  • SNRs signal-to-noise ratios
  • FIG. 3 is a block diagram showing a system/method for interleaving LDPC encoded data in preparation for QAM.
  • FIG. 4 is a diagram showing the block interleaving of parity bits .
  • FIG. 5 is a diagram showing the block allocation of bits.
  • FIG. 6 is a diagram showing the cyclical shifting of bit pipes .
  • FIG. 7 is a diagram showing a constellation for uniform 1024-QAM.
  • FIG. 8 is a diagram showing a constellation for nonuniform 1024-QAM.
  • FIG. 9a is a graph showing the capacity of various bit levels at various SNRs for uniform 1024-QAM.
  • FIG. 9b is a graph showing the capacity of various bit levels at various SNRs for non-uniform 1024-QAM.
  • FIG. 10 is a graph showing the overall capacity of systems using every combination of non-uniform, uniform, bit interleaved coded modulation, and standard coded modulation as compared to the Shannon limit.
  • FIG. 1 a block/flow diagram illustrating an exemplary transmitter/receiver system is shown.
  • the transmitter 102 receives video data 100.
  • This video data is then encoded at the Low Density Parity Check (LDPC) encoder 104.
  • LDPC encoder 104 uses one of the LDPC codes disclosed in the DVB-S2 specification.
  • the encoded data is interleaved at bit interleaver 106 before being modulated at quadrature amplitude modulation (QAM) modulator 108.
  • QAM quadrature amplitude modulation
  • the transmitter then sends the modulated, encoded data along cable channel 110.
  • the receiver 112 When the receiver 112 accepts the data from the cable channel 110, it reverses the steps taken by the transmitter. First the data is demodulated at QAM demodulator 114. Next the data is de-interleaved at bit de-interleaver 116. Finally the data is decoded at LDPC decoder 118. This decoding corrects for transmission errors which accumulated in the cable channel 110. The receiver outputs video data 120.
  • QAM modulation may use binary reflected Gray code (BRGC) labeling. Under this system, different bit positions within a single QAM symbol have different capacities (i.e., they are more or less susceptible to error) . For example, FIG. 2 depicts the capacities of the four bit levels of a 256- QAM symbol.
  • BRGC binary reflected Gray code
  • the capacity is shown in bits per channel symbol.
  • the signal- to-noise ratio (SNR) is shown in decibels.
  • SNR signal- to-noise ratio
  • Each of the four bit levels in the 256-QAM symbol is shown at six different SNRs.
  • the bit interleaver 106 takes advantage of the differing capacities of QAM bit levels and assigns the most vulnerable parity bits to the most protected bit levels.
  • the bit interleaver 106 uses information on the degree irregularity and trapping sets of the LDPC code, as well as the non-uniform bitwise protection of QAM, in making this assignment.
  • the assignment further takes into account the bit degree profile (i.e., taking into account the number of parity check equations in which each bit is involved, or the "degree" of each bit in the LDPC code word) .
  • bit interleaver 106 is designed to avoid Check Node (CND) collisions.
  • CND Check Node
  • a CND collision takes place when interleaved bits are group mapped to the same symbol and are checked by the same parity constraint. This is undesirable because symbol error induces bit-wise log- likelihood-ratio (LLR) errors. It is difficult for check nodes to produce reliable soft information when they receive multiple incorrect LLR messages. Frequent CND collisions may lead to a concentration of bit errors that cannot be corrected by message passing decoding, greatly reducing the reliability of transmission.
  • CND collision may be avoided by cyclic-shifting the bit pipes.
  • the bit interleaver 106 performs two functions, as shown in FIG. 3.
  • the LDPC codes used in DVB-S2 are systematic codes, allowing for a distinction between the information bits and the parity bits in a given codeword.
  • the bit interleaver 106 after receiving encoded data from LDPC encoder 104, the bit interleaver 106 first block-interleaves the parity bits 302 and then block-allocates all of the bits 304. Because the DVB- S2 LDPC codes are known, it is possible to anticipate which bits in a code are particularly vulnerable.
  • the block- interleaving of parity bits takes advantage of that fact and performs its interleaving such that the most vulnerable parity bits are grouped together into blocks. This is illustrated in FIG. 4.
  • FIG. 4 FIG.
  • Block allocation 304 then assembles the blocks according to the bit levels of the QAM scheme. The most vulnerable blocks are assigned to the most significant bit levels of the QAM scheme as shown in FIG. 5, providing for additional protection. If there are more vulnerable bits than will fit in the most significant bit levels of the QAM scheme, the remaining vulnerable bits are filled into intermediate bit levels .
  • the type of QAM used by QAM modulator 108 and QAM demodulator 114 also has a role in affecting the error floor of the system.
  • Many QAM systems use a form of uniform QAM, where the symbols of the constellation are equally spaced.
  • FIG. 7 shows an exemplary, uniform 1024-QAM constellation.
  • the X axis shows the amplitude of the in-phase component of a symbol, while the Y axis shows the amplitude of the quadrature component of the symbol.
  • FIG. 8 shows an exemplary, non-uniform 1024-QAM constellation.
  • symbols which are in the regions of a non-uniform constellation that are more spread out will have a higher capacity than the equivalent symbol in a uniform constellation.
  • FIG. 9a shows the capacities of uniform 1024-QAM
  • FIG. 9b shows the capacities of non-uniform 1024-QAM
  • the X axis representing the SNR
  • the Y axis representing the capacity in bits per symbol per bit level.
  • FIGs. 9a and 9b shows that the higher levels (such as level V) have higher capacities in the non-uniform system as compared to the uniform system.
  • FIG. 10 depicts the total capacity of systems using uniform versus non-uniform QAM, as well as bit interleaved coded modulation (BICM) according to the present principles versus standard coded modulation (CM) , and compares all of these to the theoretical Shannon limit. It is evident that, in the range of 5-16dB, representing the operating region of most systems, non-uniform QAM beats uniform QAM. FIG. 10 also illustrates how near to the theoretical maximum for CM systems and the Shannon limit the present BICM principles can reach. [0032] The following tables show exemplary configurations for a variety of QAM systems and LDPC code rates. Configurations are shown for BRGC-labeled 256-QAM, 1024-QAM, and 4096-QAM.
  • Each DVB-S2 LDPC long code has a block length of 64800 bits.
  • the bits are partitioned into blocks of 180 consecutive bits, indexed from 1 to 360.
  • 1024- and 4096- QAM the bits are partitioned into blocks of 360 consecutive bits, indexed from 1 to 180.
  • the tables show how the bit interleaver may assign blocks to the different bit levels of the QAM in order to provide greater protection for the more vulnerable blocks.
  • the cyclic shift of the pointer represents the amount of cyclic shift of the bit pipe for a given bit pipe to use before the bit mapping to minimize CND collisions. For example, denote the bits in a bit pipe before cyclic shift as bo,bi,..., b ⁇ o99.
  • Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4 20 21 22 23 24 25 26 27 105 106 107 108 109 110 111 112 113
  • Blockwise Bit Assignment (in multiples of 180) for Bit Level : 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
  • Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6 12 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 193 194 195 321 Cyclic shift of pointer : 29
  • Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4 9 10 11 12 13 14 15 16 17 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 Cyclic shift of pointer : 46
  • Blockwise Bit Assignment (in multiples of 180) for Bit Level : 8 34 35 36 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 273 274 275 276 277 278 279 280 281 282 283 284 285 286 Cyclic shift of pointer : 36
  • Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203
  • Blockwise Bit Assignment (in multiples of 180) for Bit Level : 8 26 31 32 33 34 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 344 347 348 349 350 353 354 359 360 Cyclic shift of pointer : 42
  • Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2 39 40 41 42 43 44 45 109 110 111 134 142 147 151 152 153 167
  • Blockwise Bit Assignment ( in multiples of 360 ) for Bit Level 10 31 32 33 34 35 36 103 104 105 106 107 108 175 176 177 178 179
  • data may be sent and received over (and using protocols associated with) fiber optic cables, universal serial bus (USB) cables, small computer system interface (SCSI) cables, telephone lines, digital subscriber line/loop (DSL) lines, line-of-sight connections, and cellular connections .
  • USB universal serial bus
  • SCSI small computer system interface
  • DSL digital subscriber line/loop
  • the implementations described herein may be implemented in, for example, a method or process, an apparatus, or a software program. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method) , the implementation of features discussed may also be implemented in other forms (for example, an apparatus or program) .
  • An apparatus may be implemented in, for example, appropriate hardware, software, and firmware.
  • the methods may be implemented in, for example, an apparatus such as, for example, a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device.
  • Processing devices also include communication devices, such as, for example, computers, cell phones, portable/personal digital assistants ("PDAs") , and other devices that facilitate communication of information between end-users.
  • communication devices such as, for example, computers, cell phones, portable/personal digital assistants ("PDAs") , and other devices that facilitate communication of information between end-users.
  • PDAs portable/personal digital assistants
  • Implementations of the various processes and features described herein may be embodied in a variety of different equipment or applications, particularly, for example, equipment or applications associated with data transmission and reception.
  • equipment include video coders, video decoders, video codecs, web servers, set-top boxes, laptops, personal computers, and other communication devices.
  • the equipment may be mobile and even installed in a mobile vehicle.
  • the methods may be implemented by instructions being performed by a computer, and such instructions may be stored on a computer-readable medium such as, for example, an integrated circuit, a software carrier or other storage device such as, for example, a hard disk, a compact diskette, a random access memory ("RAM"), or a readonly memory (“ROM”) .
  • the instructions may form an application program tangibly embodied on a computer-readable medium.
  • a computer may include a computer-readable medium having, for example, instructions for carrying out a process.
  • such a computer may include a processor to carry out such instructions, as well as input and/or output devices, such as a mouse, a keyboard, or a monitor display.
  • implementations may also produce a signal formatted to carry information that may be, for example, stored or transmitted.
  • the information may include, for example, instructions for performing a method, or data produced by one of the described implementations.
  • a signal may be formatted, for example, as an electromagnetic wave (for example, using a radio frequency portion of spectrum) or as a baseband signal.
  • the formatting may include, for example, encoding a data stream, packetizing the encoded stream, and modulating a carrier with the packetized stream.
  • the information that the signal carries may be, for example, analog or digital information.
  • the signal may be transmitted over a variety of different wired or wireless links, as is known.

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  • Error Detection And Correction (AREA)
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Abstract

A system/method is shown for reusing digital video broadcasting for satellite, second generation (DVB-S2), low-density parity check (LDPC) codes, and hence also DVB-S2 hardware, in digital video broadcasting for cable, second generation (DVB-C2) contexts. LDPC codes are susceptible to an error threshold, beyond which the coded information cannot be accurately retrieved. By matching the varying levels of protection within an LDPC codeword with the varying levels of protection in quadrature amplitude modulation, the number of errors can be kept below the error threshold.

Description

SYSTEM AND METHOD FOR REUSING DVB-S2 LDPC CODES IN DVB-C2
BACKGROUND
Technical Field
[0001] The present invention relates to systems and methods for digital video broadcasting, and more particularly to systems and methods using DVB-S2 LDPC codes for DVB-C2 broadcasting .
Description of the Related Art
[0002] In 2005, the European Telecommunications Standards Institute (ETSI) ratified the Digital Video Broadcasting Satellite - Second Generation (DVB-S2) standard for satellite broadcasting. This standard uses Low Density Parity Check (LDPC) codes for error correction and phase shift keying (PSK) modulation to transmit data. In 2008, the ETSI announced the development of the Digital Video Broadcasting - Cable - Second Generation (DVB-C2) standard for terrestrial cable broadcasting. This new standard is also set to use LDPC codes, but has very high demands for spectral efficiency, and as such will use high-order Quadrature Amplitude Modulation (QAM) (e.g., as high as 4096-QAM) .
[0003] It would be advantageous to use DVB-S2 LDPC codes for error correction in DVB-C2, thereby saving significant effort in design as well as significant cost in implementation. However, the DVB-S2 codes, and the bit interleavers designed for use with those codes, were not designed for high-order modulations .
[0004] Simply attempting to extend DVB-S2 bit interleavers to high-order modulations result in high decoding thresholds and/or high error floors. In other words, the signal-to-noise ratio (SNR) required for reliable decoding when using DVB-S2 bit interleavers for high-order modulations becomes unacceptably high.
SUMMARY
[0005] A method for transmitting information reliably includes encoding data with a code that has varying levels of bit protection, interleaving the encoded data with an interleaver in accordance with varying levels of capacity in a modulation scheme, and modulating the data according to the modulation scheme. The step of interleaving further includes block interleaving parity bits such that vulnerable bits are collected into blocks and block allocating information and parity bits into bit pipes such that less reliable bits are matched with more highly protected bit positions in the modulation scheme.
[0006] A system for transmitting information reliably includes an encoder configured to encode data with a code that has varying levels of bit protection, an interleaver configured to interleave the encoded data in accordance with varying levels of capacity in a modulation scheme, and a modulator configured to modulate the data according to the modulation scheme. The interleaver includes a block interleaver configured to interleave parity bits such that vulnerable bits are collected into blocks and a block allocator configured to allocate information and parity bits into bit pipes such that less reliable bits are matched with more highly protected bit positions in the modulation scheme
[0007] A DVB-C2 system which employs DVB-S2 LDPC codes includes an encoder configured to encode data with a DVB-S2 LDPC code, an interleaver configured to interleave the encoded data in accordance with the varying levels of capacity in a Binary Reflected Gray Code (BRGC) labeled QAM scheme, and a modulator configured to modulate the data according to the QAM scheme .
[0008] The details of one or more implementations are set forth in the accompanying drawings and the description below. Even if described in one particular manner, it should be clear that implementations may be configured or embodied in various manners. For example, an implementation may be performed as a method, or embodied as an apparatus configured to perform a set of operations or an apparatus storing instructions for performing a set of operations. Other aspects and features will become apparent from the following detailed description considered in conjunction with the accompanying drawings and the claims . BRIEF DESCRIPTION OF DRAWINGS
[0009] The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
[0010] FIG. 1 is a block diagram of a system/method for communicating data using LDPC codes over quadrature amplitude modulation (QAM) .
[0011] FIG. 2 is a graph showing the capacity of various bit levels at various signal-to-noise ratios (SNRs) for uniform 256-QAM.
[0012] FIG. 3 is a block diagram showing a system/method for interleaving LDPC encoded data in preparation for QAM. [0013] FIG. 4 is a diagram showing the block interleaving of parity bits .
[0014] FIG. 5 is a diagram showing the block allocation of bits.
[0015] FIG. 6 is a diagram showing the cyclical shifting of bit pipes .
[0016] FIG. 7 is a diagram showing a constellation for uniform 1024-QAM.
[0017] FIG. 8 is a diagram showing a constellation for nonuniform 1024-QAM.
[0018] FIG. 9a is a graph showing the capacity of various bit levels at various SNRs for uniform 1024-QAM. [0019] FIG. 9b is a graph showing the capacity of various bit levels at various SNRs for non-uniform 1024-QAM. [0020] FIG. 10 is a graph showing the overall capacity of systems using every combination of non-uniform, uniform, bit interleaved coded modulation, and standard coded modulation as compared to the Shannon limit.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS [0021] Referring now in detail to the figures in which like numerals represent the same or similar elements and initially to FIG. 1, a block/flow diagram illustrating an exemplary transmitter/receiver system is shown. The transmitter 102 receives video data 100. This video data is then encoded at the Low Density Parity Check (LDPC) encoder 104. In this case, the LDPC encoder 104 uses one of the LDPC codes disclosed in the DVB-S2 specification. The encoded data is interleaved at bit interleaver 106 before being modulated at quadrature amplitude modulation (QAM) modulator 108. The transmitter then sends the modulated, encoded data along cable channel 110.
[0022] When the receiver 112 accepts the data from the cable channel 110, it reverses the steps taken by the transmitter. First the data is demodulated at QAM demodulator 114. Next the data is de-interleaved at bit de-interleaver 116. Finally the data is decoded at LDPC decoder 118. This decoding corrects for transmission errors which accumulated in the cable channel 110. The receiver outputs video data 120. [0023] QAM modulation may use binary reflected Gray code (BRGC) labeling. Under this system, different bit positions within a single QAM symbol have different capacities (i.e., they are more or less susceptible to error) . For example, FIG. 2 depicts the capacities of the four bit levels of a 256- QAM symbol. On the vertical axis, the capacity is shown in bits per channel symbol. On the horizontal axis, the signal- to-noise ratio (SNR) is shown in decibels. Each of the four bit levels in the 256-QAM symbol is shown at six different SNRs. It is clear from the figure that L'evel 1, representing the most significant bits (MSB) , has the highest capacity, and that the capacity decreases through the levels until Level 4, representing the least significant bits (LSB) , is reached. [0024] Meanwhile, the LDPC codes used in DVB-S2 are irregular codes. One result of this is that the bits of any given codeword will have different reliabilities. Expressed another way, the different coded bits connect to a different number of parity check equations, resulting in varying robustness against error. Furthermore, some codes are part of a trapping set (roughly speaking, a trapping set comprises coded bits whose hard decisions remain unchanged at the decoder output after a finite number of iterations) , and as a result, they are vulnerable to noise and less reliable. [0025] Thus, the bit interleaver 106 takes advantage of the differing capacities of QAM bit levels and assigns the most vulnerable parity bits to the most protected bit levels. The bit interleaver 106 uses information on the degree irregularity and trapping sets of the LDPC code, as well as the non-uniform bitwise protection of QAM, in making this assignment. The assignment further takes into account the bit degree profile (i.e., taking into account the number of parity check equations in which each bit is involved, or the "degree" of each bit in the LDPC code word) .
[0026] In addition, the bit interleaver 106 is designed to avoid Check Node (CND) collisions. A CND collision takes place when interleaved bits are group mapped to the same symbol and are checked by the same parity constraint. This is undesirable because symbol error induces bit-wise log- likelihood-ratio (LLR) errors. It is difficult for check nodes to produce reliable soft information when they receive multiple incorrect LLR messages. Frequent CND collisions may lead to a concentration of bit errors that cannot be corrected by message passing decoding, greatly reducing the reliability of transmission. Advantageously, CND collision may be avoided by cyclic-shifting the bit pipes.
[0027] The bit interleaver 106 performs two functions, as shown in FIG. 3. The LDPC codes used in DVB-S2 are systematic codes, allowing for a distinction between the information bits and the parity bits in a given codeword. Thus, after receiving encoded data from LDPC encoder 104, the bit interleaver 106 first block-interleaves the parity bits 302 and then block-allocates all of the bits 304. Because the DVB- S2 LDPC codes are known, it is possible to anticipate which bits in a code are particularly vulnerable. The block- interleaving of parity bits takes advantage of that fact and performs its interleaving such that the most vulnerable parity bits are grouped together into blocks. This is illustrated in FIG. 4. FIG. 4 shows three sets of LDPC encoded bits, having high degree, medium degree, and low degree respectively. The high degree bits are more strongly protected by the code, and are therefore less susceptible to errors. The low degree bits are more vulnerable. These are the parity bits, and they are not naturally arranged in appropriate blocks. The block interleaving 302 assembles vulnerable bits into blocks. [0028] Block allocation 304 then assembles the blocks according to the bit levels of the QAM scheme. The most vulnerable blocks are assigned to the most significant bit levels of the QAM scheme as shown in FIG. 5, providing for additional protection. If there are more vulnerable bits than will fit in the most significant bit levels of the QAM scheme, the remaining vulnerable bits are filled into intermediate bit levels .
[0029] FIG. 6 shows an example of the cyclic shifting of the bit pipes, which represents the set of bits assigned to a given bit level. By starting the allocation at different points in a given bit pipe, CND collisions may be minimized. The tables shown below include information on block allocation and cyclic shifts that has been gleaned through trial and error to produce bit assignments which, when QAM modulated, provide optimally reliable results.
[0030] The type of QAM used by QAM modulator 108 and QAM demodulator 114 also has a role in affecting the error floor of the system. Many QAM systems use a form of uniform QAM, where the symbols of the constellation are equally spaced. FIG. 7 shows an exemplary, uniform 1024-QAM constellation. The X axis shows the amplitude of the in-phase component of a symbol, while the Y axis shows the amplitude of the quadrature component of the symbol. In contrast, FIG. 8 shows an exemplary, non-uniform 1024-QAM constellation. Intuitively, symbols which are in the regions of a non-uniform constellation that are more spread out will have a higher capacity than the equivalent symbol in a uniform constellation. This is borne out by the data, as shown in FIGs. 9a and 9b. FIG. 9a shows the capacities of uniform 1024-QAM, while FIG. 9b shows the capacities of non-uniform 1024-QAM, with the X axis representing the SNR and the Y axis representing the capacity in bits per symbol per bit level. FIGs. 9a and 9b shows that the higher levels (such as level V) have higher capacities in the non-uniform system as compared to the uniform system. [0031] FIG. 10 depicts the total capacity of systems using uniform versus non-uniform QAM, as well as bit interleaved coded modulation (BICM) according to the present principles versus standard coded modulation (CM) , and compares all of these to the theoretical Shannon limit. It is evident that, in the range of 5-16dB, representing the operating region of most systems, non-uniform QAM beats uniform QAM. FIG. 10 also illustrates how near to the theoretical maximum for CM systems and the Shannon limit the present BICM principles can reach. [0032] The following tables show exemplary configurations for a variety of QAM systems and LDPC code rates. Configurations are shown for BRGC-labeled 256-QAM, 1024-QAM, and 4096-QAM. Each DVB-S2 LDPC long code has a block length of 64800 bits. In 256-QAM, the bits are partitioned into blocks of 180 consecutive bits, indexed from 1 to 360. In 1024- and 4096- QAM, the bits are partitioned into blocks of 360 consecutive bits, indexed from 1 to 180. The tables show how the bit interleaver may assign blocks to the different bit levels of the QAM in order to provide greater protection for the more vulnerable blocks. The cyclic shift of the pointer represents the amount of cyclic shift of the bit pipe for a given bit pipe to use before the bit mapping to minimize CND collisions. For example, denote the bits in a bit pipe before cyclic shift as bo,bi,..., bβo99. If the cyclic shift of pointer is 47, the bits in the bit pipe after cyclic shift will be given as: b47, hue,..., bβo99> bo, bi,..., b46. A graphical representation of this assignment is shown in FIGs. 4, 5, and 6. These tables have been optimized using density evolution.
Bit Interleaver Configuration for 256-QAM and LOPC Code Rate of 2by5
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 1
49 50 51 52 53 54 55 56 57 58 59 60 61 62 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 275 276 353 354 359 360 Cyclic shift of pointer : 47
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 2
63 64 65 66 67 68 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Cyclic shift of pointer : 3
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 3
5 6 13 69 70 71 72 73 74 75 76 77 78 79 80 81 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 Cyclic shift of pointer : 33
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4
14 21 22 31 32 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 238 239 240 241 242 243 244 245 246 Cyclic shift of pointer : 21
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 5
1 2 3 4 7 8 9 10 11 12 15 16 17 18 19 20 23 24 25 35 36 39 40 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 Cyclic shift of pointer : 21
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6 26 27 28 29 113 114 115 116 117 118 119 269 270 271 272 273
274 277 278 279 280 281 282 283 284 285 286 287 288 289 290
291 292 293 294 295 296 297 298 299 300 301 302 303 304
Cyclic shift of pointer : 40
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 7
30 33 34 120 121 122 123 124 125 126 127 128 129 130 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 Cyclic shift of pointer : 29
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 8
37 38 41 42 43 44 45 46 47 48 131 132 133 134 135 136 137 138 139 140 141 142 143 144 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 355 356 357 358 Cyclic shift of pointer : 29
Bit Interleaver Configuration for 256-QAM and LDPC Code Rate of Iby2
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 1
1 2 3 4 5 6 7 8 11 12 13 14 31 32 73 74 75 76 77 78 79 80 81 82 83 84 169 170 181 182 183 184 185 186 187 188 189 190 191 192 193 299 300 355 356 Cyclic shift of pointer : 35
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 2
9 10 15 16 17 85 86 87 88 89 90 91 92 93 94 194 195 196 197
198 199 200 201 202 203 204 205 206 207 208 209 210 211 212
213 214 215 216 217 218 219 220 221 222 223 Cyclic shift of pointer : 8
Blockwise Bit Assignment (in multiples of 180) for Bit Level 3
18 19 95 96 97 98 99 100 101 102 103 104 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Cyclic shift of pointer : 5
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4 20 21 22 23 24 25 26 27 105 106 107 108 109 110 111 112 113
114 115 116 117 118 119 120 121 122 257 258 259 260 261 262
263 264 265 266 267 268 269 270 271 272 273 274 275
Cyclic shift of pointer : 32
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 5
28 29 30 33 34 35 36 37 38 39 40 41 42 123 124 125 126 127 128
129 130 131 132 133 134 135 276 277 278 279 280 281 282 283
284 285 286 287 288 289 290 291 292 293 294
Cyclic shift of pointer : 7
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6
43 44 45 46 47 136 137 138 139 140 141 142 143 144 145 146 147 295 296 297 298 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 Cyclic shift of pointer : 28
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 7
48 49 50 148 149 150 151 152 153 154 155 156 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 357 358 359 Cyclic shift of pointer : 2
Blockwise Bit Assignment (in multiples of 180) for Bit Level :
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 157 158 159 160 161 162 163 164 165 166 167 168 171 172 173 174 175 176 177 178 179 180 360 Cyclic shift of pointer : 37
Bit Interleaver Configuration for 256-QAM and LDPC Code Rate of 3by5
Blockwise Bit Assignment (in multiples of 180) for Bit Level :
1
1 2 3 4 5 6 7 8 9 10 217 218 219 220 221 222 223 224 225 226 227 233 234 247 248 249 250 251 252 267 268 283 284 293 294 301 302 303 304 305 306 333 334 345 346 Cyclic shift of pointer : 11 Blockwise Bit Assignment (in multiples of 180) for Bit Level : 2
II 12 13 14 15 16 17 18 19 20 228 229 230 231 232 235 236 237 238 239 240 241 242 243 244 245 246 253 254 255 256 257 258 259 260 261 262 263 264 265 266 269 270 271 272
Cyclic shift of pointer : 11
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 3
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
III 112 113 114 115 116 117 Cyclic shift of pointer : 2
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4
118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147
148 149 150 151 152 153 154 155 156 157 158 159 160 161 162
Cyclic shift of pointer : 31
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 5
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 163 164 165 166 167 168 169 170 171 273 274 275 276 277 278 279 280 281 282 Cyclic shift of pointer : 24
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6
47 48 49 50 51 52 53 54 55 56 57 58 285 286 287 288 289 290
291 292 295 296 297 298 299 300 307 308 309 310 311 312 313
314 315 316 317 318 319 320 321 322 323 324 325 Cyclic shift of pointer : 11
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 7
59 60 61 62 63 64 65 66 67 68 69 70 71 72 326 327 328 329 330
331 332 335 336 337 338 339 340 341 342 343 344 347 348 349
350 351 352 353 354 355 356 357 358 359 360
Cyclic shift of pointer : 20
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
187 188 189 190 191 192 193 194 195 196 197 198 199 200 201
202 203 204 205 206 207 208 209 210 211 212 213 214 215 216
Bit Interleaver Configuration for 256-QAM and LDPC Code Rate of 2by3
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 1
47 48 57 58 107 108 111 112 137 138 241 242 243 244 245 246
247 248 249 250 251 252 253 254 255 256 257 258 259 260 261
262 263 264 265 266 267 283 284 287 288 327 328 345 346
Cyclic shift of pointer : 42
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 2
3 4 13 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 49 191 192 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 285 286 Cyclic shift of pointer : 8
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 3
1 2 5 6 14 50 51 52 53 54 55 56 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Cyclic shift of pointer : 14
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4
7 8 9 10 11 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 109 110 113 114 115 116 117 118 119 120 121 122 123 124
125 126 127 128 129 130 131 132 289 290 291
Cyclic shift of pointer : 25
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 5
133 134 135 136 139 140 141 142 143 144 145 146 147 148 149 150 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 Cyclic shift of pointer : 40
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6 12 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 193 194 195 321 Cyclic shift of pointer : 29
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 7
196 197 198 199 200 201 202 203 204 205 322 323 324 325 326
329 330 331 332 333 334 335 336 337 338 339 340 341 342 343
344 347 348 349 350 351 352 353 354 355 356 357 358 359 360 Cyclic shift of pointer : 27
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 8
15 16 17 18 19 20 21 22 23 24 206 207 208 209 210 211 212 213
214 215 216 217 218 219 220 221 222 223 224 225 226 227 228
229 230 231 232 233 234 235 236 237 238 239 240
Cyclic shift of pointer : 4
Bit Interleaver Configuration for 256-QAM and LDPC Code Rate of 3by4
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 1
1 2 3 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 103 104 161 162 189 190 197 198 227 228 273 274 277 278 279 280 283 284 285 286 295 296 305 306 313 Cyclic shift of pointer : 22
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 2
4 5 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 314 317 318 323 324 327 328 329 330 351 352 Cyclic shift of pointer : 46
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 3
6 7 8 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 105 106 107 108 109 110 111 112 113 114 115 271 272 275 276 281 282 287 288 Cyclic shift of pointer : 37
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4 9 10 11 12 13 14 15 16 17 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 Cyclic shift of pointer : 46
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 5
152 153 154 155 156 157 158 159 160 289 290 291 292 293 294
297 298 299 300 301 302 303 304 307 308 309 310 311 312 315
316 319 320 321 322 325 326 331 332 333 334 335 336 337 338
Cyclic shift of pointer : 34
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6
163 164 165 166 167 168 169 170 171 172 173 174 175 176 177
178 179 180 181 182 183 184 185 186 187 188 191 192 193 194
195 196 199 200 339 340 341 342 343 344 345 346 347 348 349 Cyclic shift of pointer : 32
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 7
18 19 20 21 201 202 203 204 205 206 207 208 209 210 211 212
213 214 215 216 217 218 219 220 221 222 223 224 225 226 229
230 231 232 233 234 350 353 354 355 356 357 358 359 360
Cyclic shift of pointer : 19
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 8
22 23 24 25 26 27 28 29 30 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 Cyclic shift of pointer : 13
Bit Interleaver Configuration for 256-QAM and LDPC Code Rate of 4by5
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 1
45 46 53 54 61 62 99 100 107 108 181 182 297 298 299 300 301 302 305 306 307 308 311 312 315 316 323 324 327 328 331 332 339 340 341 342 343 344 347 348 355 356 357 358 359 Cyclic shift of pointer : 27 Blockwise Bit Assignment (in multiples of 180) for Bit Level : 2
1 37 38 39 40 41 42 43 44 47 48 49 50 51 52 55 56 57 58 59 60 63 64 65 66 67 68 69 70 71 72 73 74 187 188 193 194 217 218 231 232 271 272 287 288
Cyclic shift of pointer : 33
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 3
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 101 102 103 104
Cyclic shift of pointer : 26
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4
19 20 21 22 23 24 25 26 27 28 105 106 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Cyclic shift of pointer : 15
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 5
142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
157 158 289 290 291 292 293 294 295 296 303 304 309 310 313
314 317 318 319 320 321 322 325 326 329 330 333 334 335 360 Cyclic shift of pointer : 40
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6
29 30 31 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 183 184 185 186 189 190 191 192 195 196 197 198 199 200 201 202 203 204 205 206 Cyclic shift of pointer : 15
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 7
32 33 207 208 209 210 211 212 213 214 215 216 219 220 221 222 223 224 225 226 227 228 229 230 233 234 235 236 237 238 239 240 241 242 336 337 338 345 346 349 350 351 352 353 354 Cyclic shift of pointer : 44
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 8 34 35 36 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 273 274 275 276 277 278 279 280 281 282 283 284 285 286 Cyclic shift of pointer : 36
Bit Interleaver Configuration for 256-QAM and LDPC Code Rate of 5bγ6
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 1
57 58 71 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 327 328 333 334 337 338 339 340 343 344 349 350 353 354 355 356 357 358 Cyclic shift of pointer : 6
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 2
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 59 60 72 87 88 127 128 141 142 147 148 157 158 221 222 245 246 293 294 Cyclic shift of pointer : 48
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 3
1 61 62 63 64 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 82 83 84 85 86 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Cyclic shift of pointer : 18
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
124 125 126 129 130 131 132 133 134 135 136 137 325 326 329
330 331 332 335 336 341 342 345 346 347 348 351 352 359 360 Cyclic shift of pointer : 23
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 5
138 139 140 143 144 145 146 149 150 151 152 153 154 155 156
159 160 161 162 163 164 165 166 167 168 169 170 171 172 173
174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 Cyclic shift of pointer : 15
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203
204 205 206 207 208 209 210 211 212 213 214 215 216 217 218
219 220 223 224 225 226 227 228 229 230 231 232 233 234 235 Cyclic shift of pointer : 20
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 7
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 236 237
238 239 240 241 242 243 244 247 248 249 250 251 252 253 254
255 256 257 258 259 260 261
Cyclic shift of pointer : 22
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 8
23 24 25 26 27 28 29 30 262 263 264 265 266 267 268 269 270
271 272 273 274 275 276 277 278 279 280 281 282 283 284 285
286 287 288 289 290 291 292 295 296 297 298 299 300 Cyclic shift of pointer : 28
Bit Interleaver Configuration for 256-QAM and LDPC Code Rate of 8by9
Blockwise Bit Assignment (in multiples of 180) for Bit Level :
1
61 62 65 66 71 72 73 74 109 110 115 116 125 126 139 140 159
160 167 168 169 170 191 192 193 194 209 210 235 236 237 238
241 242 259 260 271 272 287 288 293 294 301 302 309
Cyclic shift of pointer : 12
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 2
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63
64 67 68 69 70 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 310
Cyclic shift of pointer : 26
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 3
1 2 13 14 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 111 112 113 114 117 118 119 120 121 122 123 124 127 128 129 130 131 132 133 134 135 136 321 322 325 Cyclic shift of pointer : 19 Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4
3 4 5 6 7 8 9 10 11 12 15 31 32 33 34 137 138 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 326 327 328 331 332 333 334 337 338 341 Cyclic shift of pointer : 22
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 5
161 162 163 164 165 166 171 172 173 174 175 176 177 178 179
180 181 182 183 184 185 186 187 188 189 190 195 196 197 198
199 200 201 202 203 204 205 206 207 208 211 212 213 214 215
Cyclic shift of pointer : 4
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 35 36 37 38 323
324 329 330 335 336 339 340 342 343 344 345 346 347 348 349
350 351 352 353 354 355 356 357 358 359
Cyclic shift of pointer : 20
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 7
39 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 239 240 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 261 262 263 264 265 266 267 Cyclic shift of pointer : 49
Blockwise Bit Assignment (in multiples of 180) for Bit Level :
40 268 269 270 273 274 275 276 277 278 279 280 281 282 283 284 285 286 289 290 291 292 295 296 297 298 299 300 303 304 305 306 307 308 311 312 313 314 315 316 317 318 319 320 360 Cyclic shift of pointer : 14
Bit Interleaver Configuration for 256-QAM and LDPC Code Rate of 9byO
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 1
37 38 39 40 41 42 43 44 45 46 47 65 66 71 72 75 76 95 96 109 110 141 142 153 154 157 158 161 .162 175 176 179 180 183 184 185 186 191 192 249 250 251 252 265 266 Cyclic shift of pointer : 27 Blockwise Bit Assignment (in multiples of 180) for Bit Level : 2
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 67 68 69 70
73 74 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 97 98 99 100
Cyclic shift of pointer : 12
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 3
101 102 103 104 105 106 107 108 111 112 113 114 115 116 117
118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
133 134 135 136 137 138 139 140 143 144 145 146 147 148 149 Cyclic shift of pointer : 9
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 4
7 8 150 151 152 155 156 159 160 163 164 165 166 167 168 169
170 171 172 173 174 177 178 181 182 187 188 189 190 193 194
195 196 197 198 199 200 201 202 335 336 337 338 341 342
Cyclic shift of pointer : 31
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 5
1 2 3 4 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 35 36 325 326 327 328 329 330 331 332 345 346 351 352 355 356 357 358 Cyclic shift of pointer : 40
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 6
203 204 205 206 207 208 209 210 211 212 213 214 215 216 217
218 219 220 221 222 223 224 225 226 227 228 229 230 231 232
233 234 235 236 237 238 239 240 241 242 243 244 245 246 247
Cyclic shift of pointer : 14
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 7
248 253 254 255 256 257 258 259 260 261 262 263 264 267 268
269 270 271 272 273 274 275 276 277 278 279 280 281 282 283
284 285 286 287 288 289 290 291 292 293 333 334 339 340 343
Cyclic shift of pointer : 30
Blockwise Bit Assignment (in multiples of 180) for Bit Level : 8 26 31 32 33 34 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 344 347 348 349 350 353 354 359 360 Cyclic shift of pointer : 42
Bit Interleaver Configuration for 1024-QAM and LDPC Code Rate of 2by5
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
3 7 25 26 73 74 75 76 77 78 79 80 81 82 83 138 177 180 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
11 16 27 28 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
18 20 29 30 31 32 33 34 35 98 99 100 101 102 103 104 105 106 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
1 2 36 37 38 39 107 108 109 110 111 112 113 114 115 116 117
118
Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
4 5 40 41 42 43 44 45 46 119 120 121 122 123 124 125 126 127 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
6 8 9 47 128 129 130 131 132 133 134 135 136 137 139 140 141
142
Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7 10 12 48 49 50 51 52 53 54 143 144 145 146 147 148 149 150 151 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8
13 14 55 56 57 58 59 60 61 152 153 154 155 156 157 158 159 160 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
15 17 19 21 22 62 63 64 65 161 162 163 164 165 166 167 168 169 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
23 24 66 67 68 69 70 71 72 170 171 172 173 174 175 176 178 179 Cyclic shift of pointer : 0
Bit Interleaver Configuration for 1024-QAM and LDPC Code Rate of Iby2
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
1 6 7 16 37 85 91 92 93 94 95 96 97 98 99 100 150 178 Cyclic shift of pointer : 42
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
2 3 4 38 39 40 41 42 43 101 102 103 104 105 106 107 108 109 Cyclic shift of pointer : 12
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
5 44 110 111 112 113 114 115 116 117 118 119 120 121 122 123
124 125
Cyclic shift of pointer : 40
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
8 9 10 11 12 13 45 46 47 48 49 50 126 127 128 129 130 131 Cyclic shift of pointer : 12 Blockwise Bit Assignment (in multiples of 360) for Bit Level
5
14 15 17 51 52 53 54 55 56 57 58 59 132 133 134 135 136 137 Cyclic shift of pointer 46
Blockwise Bit Assignment ( in multiples of 360) for Bit Level 6
18 19 20 60 61 62 63 64 65 66 67 68 138 139 140 141 142 143 Cyclic shift of pointer 17
Blockwise Bit Assignment (in multiples of 360) for Bit Level 7
21 22 23 24 25 26 69 70 71 72 73 74 75 144 145 146 147 148 Cyclic shift of pointer 9
Blockwise Bit Assignment ( in multiples of 360) for Bit Level 8
27 28 76 77 78 149 151 152 153 154 155 156 157 158 159 160 161
162
Cyclic shift of pointer : 12
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
29 30 31 32 79 80 163 164 165 166 167 168 169 170 171 172 173
174
Cyclic shift of pointer : 30
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
33 34 35 36 81 82 83 84 86 87 88 89 90 175 176 177 179 180 Cyclic shift of pointer : 23
Bit Interleaver Configuration for 1024-QAM and LDPC Code Rate of 3by5
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
1 2 3 4 5 6 7 8 9 10 37 38 46 53 117 124 125 126 Cyclic shift of pointer : 6
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2 39 40 41 42 43 44 45 109 110 111 134 142 147 151 152 153 167
173
Cyclic shift of pointer : 32
Blockwise Bit Assignment ( in multiples of 360) for Bit Level 3
47 48 49 50 5: L 52 54 55 56 57 58 59 60 112 113 114 115 116 Cyclic shift c?f pointer 23
Blockwise Bit Assignment ( in multiples of 360) for Bit Level 4
61 62 63 64 65 66 118 119 120 121 122 123 127 128 129 130 131
132
Cyclic shift of pointer : 12
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
11 12 13 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 Cyclic shift of pointer : 47
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
14 15 16 17 18 19 20 21 22 23 133 135 136 137 138 139 140 141 Cyclic shift of pointer : 23
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
82 83 84 85 86 87 143 144 145 146 148 149 150 154 155 156 157
158
Cyclic shift of pointer : 22
Blockwise Bit Assignment (in multiples of 360) for Bit Level 8
24 25 26 27 28 29 30 88 89 90 91 92 93 94 95 159 160 1 61 Cyclic shift of pointer : 38
Blockwise Bit Assignment (in multiples of 360) for Bit Level 9
96 97 98 99 100 101 102 162 163 164 165 166 168 169 170 171
172 174
Cyclic shift of pointer : 24
Blockwise Bit Assignment ( in multiples of 360 ) for Bit Level 10 31 32 33 34 35 36 103 104 105 106 107 108 175 176 177 178 179
180
Cyclic shift of pointer : 6
Bit Interleaver Configuration for 1024-QAM and LDPC Code Rate of 2bγ3
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
1
13 14 15 16 17 18 19 20 21 22 23 24 25 29 54 56 69 96 Cyclic shift of pointer : 3
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
26 27 28 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Cyclic shift of pointer : 2
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
45 46 47 48 49 50 51 52 53 55 57 58 59 60 61 62 63 64 Cyclic shift of pointer : 26
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
65 66 67 68 70 71 72 73 74 75 76 77 121 122 142 144 164 173 Cyclic shift of pointer : 38
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
1 2 3 4 5 6 7 8 9 10 11 12 78 79 80 81 82 83 Cyclic shift of pointer : 46
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
84 85 86 87 88 89 90 91 92 93 94 95 97 98 99 100 101 102 Cyclic shift of pointer : 6
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
118 119 120
Cyclic shift of pointer : 28 Blockwise Bit Assignment (in multiples of 360) for Bit Level :
123 124 125 126 127 128 129 130 131 132 133 134 135 136 137
138 139 140
Cyclic shift of pointer : 23
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
141 143 145 146 147 148 149 150 151 152 153 154 155 156 157
158 159 160
Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
161 162 163 165 166 167 168 169 170 171 172 174 175 176 177
178 179 180
Cyclic shift of pointer : 16
Bit Interleaver Configuration for 1024-QAM and LDPC Code Rate of 3by4
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
16 17 18 19 20 21 22 23 52 81 95 99 114 137 139 140 142 143 Cyclic shift of pointer : 5
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 148 Cyclic shift of pointer : 7
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
1 41 42 43 44 45 46 47 48 49 50 51 53 54 55 56 57 153 Cyclic shift of pointer : 41
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
2 3 4 136 138 141 144 145 146 147 149 150 157 159 162 164 165 176
Cyclic shift of pointer : 21 Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
58 59 60 61 62 63 64 65 66 67 68 151 152 154 155 156 158 160 Cyclic shift of pointer : 6
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
69 70 71 72 73 74 75 76 77 78 79 80 82 161 163 166 167 168 Cyclic shift of pointer : 16
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
83 84 85 86 87 88 89 90 91 92 93 94 96 97 98 100 101 169 Cyclic shift of pointer : 4
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8
102 103 104 105 106 107 108 109 110 111 112 113 115 116 117
118 170 171
Cyclic shift of pointer : 1
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
5 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
Cyclic shift of pointer : 32
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
6 7 8 9 10 11 12 13 14 15 172 173 174 175 177 178 179 180 Cyclic shift of pointer : 6
Bit Interleaver Configuration for 1024-QAM and LDPC Code Rate of 4by5
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
19 20 21 22 23 24 25 27 31 50 54 91 94 97 109 116 136 144 Cyclic shift of pointer : 47
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2 26 28 29 30 32 33 34 35 36 37 38 39 40 41 42 43 149 150 Cyclic shift of pointer : 5
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
44 45 46 47 48 49 51 52 53 55 56 57 58 59 60 61 62 63 Cyclic shift of pointer : 11
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 151 Cyclic shift of pointer : 19
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
I 2 3 4 5 6 7 8 9 10 81 82 83 84 153 154 156 158 Cyclic shift of pointer : 42
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
II 85 86 87 88 89 90 92 93 95 162 164 166 170 171 172 174 178 Cyclic shift of pointer : 8
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
12 13 14 15 16 17 96 98 99 100 145 146 147 148 152 155 179 180 Cyclic shift of pointer : 26
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8
18 101 102 103 104 105 106 107 108 110 111 112 113 114 157 159
160 161
Cyclic shift of pointer : 36
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
115 117 118 119 120 121 122 123 124 125 163 165 167 168 169
173 175 176
Cyclic shift of pointer : 42
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10 126 127 128 129 130 131 132 133 134 135 137 138 139 140 141
142 143 177
Cyclic shift of pointer : 15
Bit Interleaver Configuration for 1024-QAM and LDPC Code Rate of 5by6
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
1
16 17 18 19 20 21 22 29 36 44 64 71 74 79 111 123 147 151 Cyclic shift of pointer : 37
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
23 24 25 26 27 28 30 31 32 33 34 35 37 38 152 153 154 156 Cyclic shift of pointer : 42
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
39 40 41 42 43 45 46 47 48 49 50 51 52 160 161 162 164 167 Cyclic shift of pointer : 30
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
53 54 55 56 57 58 59 60 61 62 63 65 66 67 68 69 70 169 Cyclic shift of pointer : 5
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
1 2 3 4 5 6 7 8 9 155 157 158 170 172 175 177 178 179 Cyclic shift of pointer : 22
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
72 73 75 76 77 78 80 81 82 83 84 85 159 163 165 166 168 171 Cyclic shift of pointer : 32
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
10 11 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 Cyclic shift of pointer : 2 Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8
12 13 14 15 102 103 104 105 106 107 108 109 110 112 113 173
174 176
Cyclic shift of pointer : 1
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
114 115 116 117 118 119 120 121 122 124 125 126 127 128 129
130 131 180
Cyclic shift of pointer : 14
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
148 149 150
Cyclic shift of pointer : 46
Bit Interleaver Configuration for 1024-QAM and LDPC Code Rate of 8by9
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
1
31 33 36 37 55 58 63 70 80 84 85 96 97 105 118 119 121 130 Cyclic shift of pointer : 25
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
21 22 23 24 25 26 27 28 29 30 32 34 35 136 144 147 151 155 Cyclic shift of pointer : 32
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 56 Cyclic shift of pointer : 7
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
57 59 60 61 62 64 65 66 67 68 69 71 72 73 74 75 76 77 Cyclic shift of pointer : 31
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 161 163 Cyclic shift of pointer : 22
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
78 79 81 82 83 86 87 88 89 90 91 92 93 94 95 98 99 100 Cyclic shift of pointer : 39
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
15 18 19 20 101 102 103 104 106 107 108 109 110 111 112 164
166 167
Cyclic shift of pointer : 25
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8
113 114 115 116 117 120 122 123 124 125 162 165 168 169 170
171 175 178
Cyclic shift of pointer : 17
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
126 127 128 129 131 132 133 134 135 137 138 139 140 141 142
143 145 146
Cyclic shift of pointer : 12
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
148 149 150 152 153 154 156 157 158 159 160 172 173 174 176
177 179 180
Cyclic shift of pointer : 24
Bit Interleaver Configuration for 1024-QAM and LDPC Code Rate of 9byO
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
23 33 36 38 48 55 71 77 79 81 88 90 92 93 96 125 126 133 Cyclic shift of pointer : 26
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2 19 20 21 22 24 25 26 27 28 29 30 31 32 34 35 37 39 40 Cyclic shift of pointer : 38
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
41 42 43 44 45 46 47 49 50 51 52 53 54 56 57 58 59 60 Cyclic shift of pointer : 3
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
61 62 63 64 65 66 67 68 69 70 72 73 74 75 76 78 80 82 Cyclic shift of pointer : 19
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
83 84 85 86 87 89 91 94 95 97 98 99 100 101 102 103 104 105 Cyclic shift of pointer : 43
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
1 2 3 4 9 11 12 14 15 18 163 168 169 171 173 176 178 179 Cyclic shift of pointer : 49
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
121 122 123
Cyclic shift of pointer : 22
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
124 127 128 129 130 131 132 134 135 136 137 138 139 140 141
142 143 144
Cyclic shift of pointer : 40
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159
160 161 162
Cyclic shift of pointer : 3
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10 5 6 7 8 10 13 16 17 164 165 166 167 170 172 174 175 177 180 Cyclic shift of pointer : 38
Bit Interleaver Configuration for 4096-QAM and LDPC Code Rate of 2by5
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
3 7 25 73 74 75 76 77 78 79 80 81 138 177 180 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
11 16 18 82 83 84 85 86 87 88 89 90 91 92 93 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
1 20 26 27 28 29 30 31 94 95 96 97 98 99 100 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
2 32 33 34 35 36 37 38 39 101 102 103 104 105 106 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
4 5 40 41 42 43 44 45 107 108 109 110 111 112 113 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
6 8 46 47 48 49 50 114 115 116 117 118 119 120 121 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
9 51 52 53 54 55 56 57 122 123 124 125 126 127 128 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8 10 12 58 59 129 130 131 132 133 134 135 136 137 139 140 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
13 14 15 60 61 62 63 141 142 143 144 145 146 147 148 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
17 19 149 150 151 152 153 154 155 156 157 158 159 160 161 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 11
21 22 64 65 66 67 162 163 164 165 166 167 168 169 170 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 12
23 24 68 69 70 71 72 171 172 173 174 175 176 178 179 Cyclic shift of pointer : 0
Bit Interleaver Configuration for 4096-QAM and LDPC Code Rate of Iby2
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
6 7 37 38 39 40 41 42 85 91 92 93 94 150 178 Cyclic shift of pointer : 28
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
1 16 95 96 97 98 99 100 101 102 103 104 105 106 107 Cyclic shift of pointer : 23
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
2 3 4 5 8 9 43 44 45 108 109 110 111 112 113 Cyclic shift of pointer : 0 Blockwise Bit Assignment (in multiples of 360) for Bit Level 4
10 11 46 47 48 49 50 51 114 115 116 117 118 119 120. Cyclic shift of pointer : 16
Blockwise Bit Assignment (in multiples of 360) for Bit Level 5
12 52 53 54 55 56 57 121 122 123 124 125 126 127 128 Cyclic shift of pointer : 8
Blockwise Bit Assignment (in multiples of 360) for Bit Level 6
13 14 15 17 58 59 60 61 62 129 130 131 132 133 134 Cyclic shift of pointer : 39
Blockwise Bit Assignment (in multiples of 360) for Bit Level 7
18 19 63 64 65 135 136 137 138 139 140 141 142 143 144 Cyclic shift of pointer : 15
Blockwise Bit Assignment (in multiples of 360) for Bit Level
20 66 67 68 69 145 146 147 148 149 151 152 153 154 155 Cyclic shift of pointer : 26
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
21 22 23 24 25 26 70 71 72 73 156 157 158 159 160 Cyclic shift of pointer : 8
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
27 28 29 74 75 76 77 161 162 163 164 165 166 167 168 Cyclic shift of pointer : 30
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 11
30 31 32 33 34 78 79 80 81 82 169 170 171 172 173 Cyclic shift of pointer : 13
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 12 35 36 83 84 86 87 88 89 90 174 175 176 177 179 180 Cyclic shift of pointer : 32
Bit Interleaver Configuration for 4096-QAM and LDPC Code Rate of 3by5
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
1 37 38 39 40 41 46 53 117 124 125 126 134 142 147 Cyclic shift of pointer : 19
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
2 42 43 44 45 47 109 110 111 112 151 152 153 167 173 Cyclic shift of pointer : 26
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
3 48 49 50 51 52 113 114 115 116 118 119 120 121 122 Cyclic shift of pointer : 43
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
4 5 54 55 56 57 58 59 60 123 127 128 129 130 131 Cyclic shift of pointer : 20
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
6 7 61 62 63 64 132 133 135 136 137 138 139 140 141 Cyclic shift of pointer : 9
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
8 9 65 66 67 68 69 70 71 72 73 74 75 76 143 Cyclic shift of pointer : 28
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
10 11 12 13 77 78 79 80 81 82 83 144 145 146 148 Cyclic shift of pointer : 38
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8 14 84 85 86 87 88 89 149 150 154 155 156 157 158 159 Cyclic shift of pointer : 46
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
15 16 17 18 19 20 21 22 23 24 25 26 27 28 90 Cyclic shift of pointer : 41
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
29 30 31 32 91 92 93 94 95 96 160 161 162 163 164 Cyclic shift of pointer : 33
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 11
33 34 35 97 98 99 165 166 168 169 170 171 172 174 175 Cyclic shift of pointer : 41
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 12
36 100 101 102 103 104 105 106 107 108 176 177 178 179 180 Cyclic shift of pointer : 37
Bit Interleaver Configuration for 4096-QAM and LDPC Code Rate of 2by3
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
1
24 29 121 122 123 124 125 126 127 128 129 142 144 164 173 Cyclic shift of pointer : 41
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
13 14 15 16 17 18 19 20 21 54 56 69 96 130 131 Cyclic shift of pointer : 49
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
2 22 23 25 26 27 28 132 133 134 135 136 137 138 139 Cyclic shift of pointer : 36 Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
7 30 31 32 33 34 35 36 37 38 39 40 41 140 141 Cyclic shift of pointer : 17
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
1 42 43 44 45 46 47 48 49 50 51 52 53 55 143 Cyclic shift of pointer : 29
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
3 57 58 59 60 61 62 63 64 65 66 67 68 70 145 Cyclic shift of pointer : 5
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
4 71 72 73 74 75 76 77 78 79 80 146 147 148 149 Cyclic shift of pointer : 45
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8
5 81 82 83 84 85 86 87 150 151 152 153 154 155 156 Cyclic shift of pointer : 43
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
6 88 89 90 91 92 93 157 158 159 160 161 162 163 165 Cyclic shift of pointer : 40
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
94 95 97 98 99 166 167 168 169 170 171 172 174 175 176 Cyclic shift of pointer : 13
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
11
8 9 10 11 100 101 102 103 104 105 106 107 108 177 178 Cyclic shift of pointer : 29
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 12 12 109 110 111 112 113 114 115 116 117 118 119 120 179 180 Cyclic shift of pointer : 1
Bit Interleavβr Configuration for 4096-QAM and LDPC Code Rate of 3by4
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
1
16 17 18 19 20 21 52 81 95 99 114 137 139 140 142 Cyclic shift of pointer : 20
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
22 23 24 25 26 27 28 29 30 31 32 33 34 143 148 Cyclic shift of pointer : 28
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
35 36 37 38 39 40 41 42 43 44 45 46 47 48 153 Cyclic shift of pointer : 22
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
49 50 51 53 54 55 56 57 58 59 60 61 62 63 157 Cyclic shift of pointer : 27
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Cyclic shift of pointer : 12
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
1 2 3 4 5 6 7 136 138 141 159 162 164 165 176 Cyclic shift of pointer : 32
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
79 80 82 83 84 85 86 87 88 89 90 91 144 145 146 Cyclic shift of pointer : 17
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8 92 93 94 96 97 98 100 101 102 103 104 105 106 107 108 Cyclic shift of pointer : 13
Blockwise Bit Assignment (in multiples of 360) for Bit Level 9
109 110 111 112 113 147 149 150 151 152 154 155 156 158 160 Cyclic shift of pointer : 4
Blockwise Bit Assignment (in multiples of 360) for Bit Level 10
8 9 10 115 116 117 118 119 120 121 122 12: 1 124 125 126 Cyclic shift of pointer : 21
Blockwise Bit Assignment (in multiples of 360) for Bit Level
11
127 128 129 130 131 132 133 134 161 163 166 167 168 169 170 Cyclic shift of pointer : 18
Blockwise Bit Assignment (in multiples of 360) for Bit Level 12
11 12 13 14 15 135 171 172 173 174 175 177 178 179 180 Cyclic shift of pointer : 9
Bit Interleaver Configuration for 4096-QAM and LDPC Code Rate of 4by5
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
1
19 20 21 23 27 31 50 54 91 94 97 109 116 136 144 Cyclic shift of pointer : 46
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
22 24 25 26 28 29 30 32 33 34 35 36 37 38 39 Cyclic shift of pointer : 6
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
40 41 42 43 44 45 46 47 48 49 51 149 150 151 153 Cyclic shift of pointer : 0 Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
52 53 55 56 57 58 59 60 61 154 156 158 162 164 166 Cyclic shift of pointer : 10
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Cyclic shift of pointer : 44
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
77 78 79 80 81 82 83 84 85 86 87 88 89 170 171 Cyclic shift of pointer : 34
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
90 92 93 95 96 98 99 100 101 102 103 104 105 106 107 Cyclic shift of pointer : 37
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8
108 110 111 112 113 114 115 117 118 119 172 174 178 179 180 Cyclic shift of pointer : 10
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
1 2 3 4 5 6 7 8 9 10 145 146 147 148 152 Cyclic shift of pointer : 40
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
11 12 120 121 122 123 124 125 126 127 128 129 130 131 132 Cyclic shift of pointer : 44
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 11
133 134 135 137 138 139 140 141 142 143 155 157 159 160 161 Cyclic shift of pointer : 0
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 12 13 14 15 16 17 18 163 165 167 168 169 173 175 176 177 Cyclic shift of pointer : 5
Bit Interleaver Configuration for 4096-QAM and LDPC Code Rate of 5by6
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
16 17 18 19 20 29 36 44 64 71 74 79 111 123 147 Cyclic shift of pointer : 17
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
1 2 3 4 5 21 22 23 24 25 26 27 28 30 31 Cyclic shift of pointer : 30
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
32 33 34 35 37 38 39 40 151 152 153 154 156 160 161 Cyclic shift of pointer : 34
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
41 42 43 45 46 47 48 49 50 51 52 162 164 167 169 Cyclic shift of pointer : 18
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
5
53 54 55 56 57 58 59 60 61 62 63 170 172 175 177 Cyclic shift of pointer : 18
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
6 7 8 9 10 11 155 157 158 159 163 165 166 178 179 Cyclic shift of pointer : 7
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
65 66 67 68 69 70 72 73 75 76 77 78 80 81 82 Cyclic shift of pointer : 27
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Cyclic shift of pointer : 44
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
98 99 100 101 102 103 104 105 106 107 108 109 110 112 113 Cyclic shift of pointer : 20
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
114 115 116 117 118 119 120 121 122 168 171 173 174 176 180 Cyclic shift of pointer : 25
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 11
12 13 14 15 124 125 126 127 128 129 130 131 132 133 134 Cyclic shift of pointer : 35
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 12
135 136 137 138 139 140 141 142 143 144 145 146 148 149 150 Cyclic shift of pointer : 21
Bit Interleaver Configuration for 4096-QAM and LDPC Code Rate of 8by9
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
31 33 36 37 55 58 63 70 80 84 85 96 97 105 118 Cyclic shift of pointer : 10
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
21 22 23 24 25 26 27 119 121 130 136 144 147 151 155 Cyclic shift of pointer : 36
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
28 29 30 32 34 35 38 39 40 41 42 43 44 45 46 • Cyclic shift of pointer : 23 Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
1 2 3 7 16 17 161 163 164 166 167 169 171 175 178 Cyclic shift of pointer : 34
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
47 48 49 50 51 52 53 54 56 57 59 60 61 62 64 Cyclic shift of pointer : 17
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
4 5 6 8 9 10 11 12 13 65 66 67 68 69 162 Cyclic shift of pointer : 35
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
71 72 73 74 75 76 77 78 79 81 82 83 86 87 88 Cyclic shift of pointer : 40
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 8
89 90 91 92 93 94 95 98 99 100 101 102 103 104 106 Cyclic shift of pointer : 15
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
107 108 109 110 111 112 113 114 115 116 117 120 122 123 124 Cyclic shift of pointer : 24
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
125 126 127 128 129 131 132 133 134 135 137 138 139 140 141 Cyclic shift of pointer : 18
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 11
142 143 145 146 148 149 150 152 153 154 156 157 158 159 160 Cyclic shift of pointer : 8
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 12 14 15 18 19 20 165 168 170 172 173 174 176 177 179 180 Cyclic shift of pointer : 0
Bit Interleaver Configuration for 4096-QAM and LDPC Code Rate of 9byO
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 1
23 33 36 38 48 55 71 77 79 81 88 90 92 93 96 Cyclic shift of pointer : 16
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 2
19 20 21 22 24 25 26 27 28 29 30 31 125 126 133 Cyclic shift of pointer : 46
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 3
4 9 11 32 34 35 37 39 40 41 42 43 168 169 171 Cyclic shift of pointer : 4
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 4
12 14 15 18 44 45 46 47 49 50 51 173 176 178 179 Cyclic shift of pointer : 14
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 5
1 2 52 53 54 56 57 58 59 60 163 164 165 166 167 Cyclic shift of pointer : 20
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 6
3 5 6 7 8 10 13 16 17 170 172 174 175 177 180 Cyclic shift of pointer : 29
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 7
61 62 63 64 65 66 67 68 69 70 72 73 74 75 76 Cyclic shift of pointer : 8
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 78 80 82 83 84 85 86 87 89 91 94 95 97 98 99 Cyclic shift of pointer : 31
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 9
100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Cyclic shift of pointer : 10
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 10
115 116 117 118 119 120 121 122 123 124 127 128 129 130 131 Cyclic shift of pointer : 3
Blockwise Bit Assignment (in multiples of 360) for Bit Level :
11
132 134 135 136 137 138 139 140 141 142 143 144 145 146 147 Cyclic shift of pointer : 37
Blockwise Bit Assignment (in multiples of 360) for Bit Level : 12
148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 Cyclic shift of pointer : 8
[0033] Features and aspects of described implementations may be applied to various applications. Applications include, for example, implementing DVB-S2 codes in a DVB-C2 system to promote interoperability and save in costs. However, the features and aspects herein described may be adapted for other application areas and, accordingly, other applications are possible and envisioned. For example, the technique may be used to reuse LDPC codes from any given standard in a more error-prone context. Additionally, protocols and communication media other than satellite and cable may be used. For example, data may be sent and received over (and using protocols associated with) fiber optic cables, universal serial bus (USB) cables, small computer system interface (SCSI) cables, telephone lines, digital subscriber line/loop (DSL) lines, line-of-sight connections, and cellular connections .
[0034] The implementations described herein may be implemented in, for example, a method or process, an apparatus, or a software program. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method) , the implementation of features discussed may also be implemented in other forms (for example, an apparatus or program) . An apparatus may be implemented in, for example, appropriate hardware, software, and firmware. The methods may be implemented in, for example, an apparatus such as, for example, a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processing devices also include communication devices, such as, for example, computers, cell phones, portable/personal digital assistants ("PDAs") , and other devices that facilitate communication of information between end-users. [0035] Implementations of the various processes and features described herein may be embodied in a variety of different equipment or applications, particularly, for example, equipment or applications associated with data transmission and reception. Examples of equipment include video coders, video decoders, video codecs, web servers, set-top boxes, laptops, personal computers, and other communication devices. As should be clear, the equipment may be mobile and even installed in a mobile vehicle.
[0036] Additionally, the methods may be implemented by instructions being performed by a computer, and such instructions may be stored on a computer-readable medium such as, for example, an integrated circuit, a software carrier or other storage device such as, for example, a hard disk, a compact diskette, a random access memory ("RAM"), or a readonly memory ("ROM") . The instructions may form an application program tangibly embodied on a computer-readable medium. As should be clear, a computer may include a computer-readable medium having, for example, instructions for carrying out a process. As noted above, such a computer may include a processor to carry out such instructions, as well as input and/or output devices, such as a mouse, a keyboard, or a monitor display.
[0037] As should be evident to one of skill in the art, implementations may also produce a signal formatted to carry information that may be, for example, stored or transmitted. The information may include, for example, instructions for performing a method, or data produced by one of the described implementations. Such a signal may be formatted, for example, as an electromagnetic wave (for example, using a radio frequency portion of spectrum) or as a baseband signal. The formatting may include, for example, encoding a data stream, packetizing the encoded stream, and modulating a carrier with the packetized stream. The information that the signal carries may be, for example, analog or digital information. The signal may be transmitted over a variety of different wired or wireless links, as is known.
[0038] A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, elements of different implementations may be combined, supplemented, modified, or removed to produce other implementations. Additionally, one of ordinary skill will understand that other structures and processes may be substituted for those disclosed and the resulting implementations will perform at least substantially the same function (s), in at least substantially the same way(s), to achieve at least substantially the same result(s) as the implementations disclosed. Accordingly, these and other implementations are within the scope of the following claims .

Claims

1. A method for transmitting information, comprising: encoding data 104 with a code that has a plurality of levels of bit protection; interleaving 106 the encoded data with an interleaver in accordance with a plurality of levels of capacity in a modulation scheme, wherein said interleaving comprises: block interleaving 302 parity bits such that vulnerable bits are collected into blocks; and block allocating 304 information and parity bits into bit pipes such that less reliable bits are matched with more highly protected bit positions in the modulation scheme; and modulating 108 the data according to the modulation scheme .
2. The method of claim 1, wherein the code is an irregular, systematic low-density parity check (LDPC) code.
3. The method of claim 1, wherein the bit pipes are cyclically shifted before modulating.
4. The method of claim 2, wherein the code is a DVB-S2 LDPC code .
5. The method of claim 1, wherein the modulation scheme is selected from the group consisting of binary-reflected Gray code (BRGC) labeled 256 Quadrature Amplitude Modulation (QAM) , 1024-QAM, and 4096-QAM.
6. The method of claim 5, wherein the modulation scheme is non-uniform.
7. A computer readable storage medium having computer readable program code embodied therewith, wherein the computer readable program code when executed on a computer causes the computer to perform the method of claim 1.
8. A system for transmitting information, comprising: an encoder 104 configured to encode data with a code that has a plurality of levels of bit protection; an interleaver 106 configured to interleave the encoded data in accordance with a plurality of levels of capacity in a modulation scheme, wherein said interleaver further comprises: a block interleaver 302 configured to interleave parity bits such that vulnerable bits are collected into blocks; and a block allocator 304 configured to allocate information and parity bits into bit pipes such that less reliable bits are matched with more highly protected bit positions in the modulation scheme; and a modulator 108 configured to modulate the data according to the modulation scheme.
9. The system of claim 8, wherein the bit pipes are cyclically shifted before modulating.
10. The system of claim 8, wherein the code is an irregular, systematic low-density parity check (LDPC) code.
11. The system of claim 10, wherein the code is a DVB-S2 LDPC code .
12. The system of claim 8, wherein the modulation scheme is selected from the group consisting of binary reflected Gray code (BRGC) labeled 256 Quadrature Amplitude Modulation (QAM) , 1024-QAM, and 4096-QAM.
13. The system of claim 12, wherein the modulation scheme is non-uniform.
14. A system which employs low-density parity check (LDPC) codes, comprising: an encoder 104 configured to encode data with a DVB-S2 LDPC code; an interleaver 106 configured to interleave the encoded data in accordance with a plurality of levels of capacity in a BRGC-labeled quadrature amplitude modulation (QAM) scheme; and a modulator 108 configured to modulate the data according to the QAM scheme.
15. The system of claim 14, wherein the interleaver comprises : a block interleaver 302 configured to interleave parity bits such that vulnerable bits are collected into blocks; and a block allocator 304 configured to allocate information and parity bits into bit pipes such that less reliable bits are matched with more highly protected bit positions in the QAM scheme.
16. The system of claim 15, wherein the bit pipes are cyclically shifted before modulating.
17. The system of claim 14, wherein the QAM scheme is selected from the group consisting of 256 Quadrature Amplitude Modulation (QAM), 1024-QAM, and 4096-QAM.
18. The system of claim 16, wherein the QAM scheme is nonuniform.
PCT/US2009/004888 2008-08-29 2009-08-27 System and method for reusing dvb-s2 ldpc codes in dvb-c2 WO2010024914A1 (en)

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