WO2010023583A1

WO2010023583A1 - Method of testing analog circuitry in an integrated circuit device

Info

Publication number: WO2010023583A1
Application number: PCT/IB2009/053579
Authority: WO
Inventors: Leon Van De Logt; Alexander Guido Gronthoud
Original assignee: Nxp B.V.
Priority date: 2008-08-26
Filing date: 2009-08-13
Publication date: 2010-03-04

Abstract

A built-in self test (BIST) scheme for testing analog circuitry in an integrated circuit device comprises applying test stimuli to a circuit under test (CUT), obtaining the responses of the circuit under test to the test stimuli and examining the responses to determine if the circuit under test is of an acceptable standard. The test stimuli are generated using pulse width modulation (PWM) techniques to provide high frequency test signals from low frequency signals. The test mode control uses the standard JTAG interface but with modification to enable effective control.

Description

DESCRIPTION

METHOD OF TESTING ANALOG CIRCUITRY IN AN INTEGRATED CIRCUIT DEVICE

The present invention relates to a method of testing analog circuitry in an integrated circuit (IC) device. The present invention has particular but not exclusive application to generating test stimuli for testing RF/analog circuitry in an integrated circuit device which may be an analog functional core circuitry (FCCA) device or have both digital and analog circuitry.

The Institute of Electrical and Electronics Engineers (IEEE) formed special committees to generate test standards that would assist IC manufacturers and equipment manufacturers to carry out testing on various electronic circuits in a standardised manner. One such committee, termed the Joint Test Access Group (JTAG), generated several standards for testing printed circuit boards (PCBs) and ICs using a boundary scan technique that utilizes test-related hardware built inside ICs. The IEEE 1149.1 Test Access Port and Boundary Scan Standard is a test scheme to test digital ICs using embedded boundary-scan hardware and a four-wire test bus. If required a five-wire test bus is used if an optional test reset (TRST) pin is included. The IEEE 1149.4 standard was developed subsequently to test ICs containing mixed digital as well as analog circuitry, using a six-wire bus while remaining backwards compatible to the IEEE 1149.1 standard.

In order to facilitate an understanding of the present invention the requirements of the IEEE 1149.1 and 1149.4 standards will be explained with reference to Figure 1 which is a block schematic diagram of an IC 100 having digital functional core circuitry 130 and analog functional core circuitry 205. The circuitry enclosed in a broken line box 102 relates to the testing of analog circuitry. Initially the following description will be concerned with the testing of digital circuitry. At an IC level, the IEEE 1149.1 standard requires that each primary input pin and each primary output pin of an IC be supplemented with a multi-purpose element called a "boundary-scan cell". Each boundary scan cell contains at least one flip-flop. Multiple such flip-flops of different boundary scan cells can be cascaded to form a boundary-scan test chain. In Figure 1 boundary scan registers 111 to 113 and 117 to 119 are connected to I/O pins 124 and 126 and can be cascaded together to form a test chain referred to as the boundary-scan register chain. A boundary scan register operates independently of the digital functional core circuit 130, which is the primary circuit contained in the IC 100, assuming a digital only IC. In a test mode, a circuit under test (CUT) 104 is connected between test control circuitry 106 and boundary scan register 111 of the boundary-scan register chain. A digital signal fed into an input pin TDI (Test Data In) 120 constitutes an input signal into the boundary-scan register chain, and the resultant output digital signal of the boundary-scan register chain appears on an output pin TDO (Test Data Out) 123. Boundary-scan testing provides information related to electrical short-circuits and open-circuits of the I/O pins of IC 100 that are typically soldered onto metal pads.

TMS (Test Mode Select) 121 and TCK (Test Clock) 122 are two other pins that form together with TDM 20 and TDO 123, the external test interface pins specified by the IEEE 1149.1 standard. These four test interface I/O pins, collectively referred to as a test-access port (TAP), permit test equipment to gain test access to the I/O pins 124, 125 and 126 of the IC 100 via the boundary scan register. The testing of faults, such as internal short-circuits and open- circuits, may be carried-out by providing test-stimulus in the form of a digital data input stream via TDI 120, initialising all the internal flip-flops and capturing the responsive digital data output data stream at the TDO 123 pin.

Considering now the IEEE 1149.4 standard and taking into account the circuitry in the broken line box 102, the CUT 104 now comprises a mixed signal IC incorporating a boundary scan cell 108. The analog functional core circuitry as well as analog I/O pins 202 are contained entirely within the IC and in operation are effectively by-passed while testing the digital I/O pins 124 and 126 which are associated with the digital functional core circuitry 130. It can been seen that this type of boundary scan testing, while effective for additionally testing the digital functional core circuitry, precludes testing of the analog functional core circuitry 205 of the mixed-signal IC. IEEE 1149.4 addressed the issue of testing mixed-signal ICs by specifying that every I/O pin, digital as well as analog, be provided with a boundary-scan module. The IEEE 1149.4 boundary-scan module is very similar to the boundary-scan cell of IEEE 1149.1 and is referred to as an analog boundary-scan module (ABM). In Figure 1 ABMs 206, 208 typically employ a switching network connected between analog I/O pins 202 and the analog functional core circuitry 205, thereby permitting the analog I/O pins to be placed in a core-disconnect (CD) state. In a non-test mode, an analog signal is applied by way of a pin 200 and may be routed through the CUT 104 into the FCCA 205 without any test related processing being performed on it.

Many modern ICs often comprise analog as well as digital parts. Especially in the case of those ICs that have a RF front-end with a local oscillator, the analog circuitry can occupy about 50% of the total chip area. Although functional tests are common in practice to test for the correctness of the analog part of the IC, these tests, which frequently require expensive RF test equipment, are becoming more and more of a problem to inexpensive testing of ICs. Generally speaking test failures show that the analog testing was not complete and the failure analysis on these ICs is very expensive.

From literature many variations to alternative radio frequency/analog mixed signal (RF/AMS) testing exist. Among these publications a lot deal with variations to the currently available test signals. Amplitude modulated, single tone, dual tone and oscillation based test techniques are applied. Often these signals have low frequencies in order to meet the goal of excluding expensive RF/AMS equipment. The signal processing is often a more complex processing then is generally seen with traditional functional tests. An interesting approach for optimal test stimuli for electronic circuits is derived by Burdiek et.al. ["The qualitative form of optimum transient test signals for analog circuits derived from control theory methods" Burdiek, B, ISCAS 2002 IEEE Symposium on Circuits and Systems 2002, Volume 1 26 - 29 May 2002 Pages: 1-157 to 1 -160 vol.1 and "Generation of optimum test stimuli for non-linear analog circuits using non-linear programming and time- domain sensitivities" Burdiek, B, Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings 13 - 16 March 2001. Pages: 603 - 608]. The mathematical approach described is general and derived from control theory. It is not specifically targeted for electronic circuits but also holds for other system like mechanical ones. Engineers now try to develop this mathematical theory into practical applications for electronic circuits. The theory states that an optimal test stimuli consists of a binary level pulse train with maximum amplitude. It is not described how this can be applied for radio frequency/analog mixed signal (RF/AMS) testing. Some attempts have been to inject an equally spaced binary signal into the system. However, there is no correlation with the dynamic characteristics of the circuit under test. One earlier approach to define a practical optimal test stimulus is given by Variyam et al ["Efficient test generation for transisent testing of analog circuits using partial numerical simulation" Variyam, P. N, Hou, J, Chatterjee, A, VLSI Test Symposium, 199. Proceedings 17^th IEEE 25-29 April 1999 Pages 214 - 219]. They use piecewise linear elements for the test stimuli based on numerical calculation of the circuit. However, as will be described later, this approach is clearly different from the present invention which uses pulse width modulation (PWM) generation produced by on-chip hardware. Another approach is disclosed in US Patent 7,032,151 issued to Haider A which relates to systems and methods for digital-based standards-compatible, testing of analog circuits embedded inside integrated circuits. In particular this patent discloses interconnect testing, parametric testing and internal testing on ICs designed to accommodate the IEEE 1149.4 standard. The proposed test system compares an arbitrary test signal with another reference signal. The comparison result is then sampled using the boundary scan cells of JTAG. However, the test system relies on using boundary scan cells as sampler, which is very slow and only applicable for very low frequency signals.

Other cited literature refers to the use of analog test signal derived from sigma delta modulator. Much of this work is published by Roberts et al [Optimized periodic sigma-delta bit streams for analog signal generation" Roberts, G. W, Dufot. B. Proceedings of the 40^th Midwest Symposium on Circuits and Systems, 1997. Volume 1 , 3-6 Aug. 1997, Pages 289-292 vol. 1 ; "On-chip analog signal generator for mixed-signal built-in self-test" Roberts G. W, Dufort, B, Custom Integrated Circuits Conference 1998, Proceedings of the IEEE 1998. Pages 549-552; "Signal generation using periodic single and multi-bit sigma-delta modulated streams" Robert G W, Dufort B, Test Conference, 1997. Proceedings, International 1 -6 Nov 1997 Pages 396-405]. Main goal in these publications is to generate alternative analog signals for analog to digital/digital to analog (ADDA) converters. Here the authors reproduce samples of the output bitstreams from converters in order to generate a test large variety of bitstreams. These bitstreams represent closely the functional signals passing through converters. In addition, the authors implement hardware based on a shift register and 1 bit DAC to generate the repeated samples. These techniques however, do not exploit the high frequency behaviour of PWM signals but merely target optimal bit stream generation for ADDA converters.

WO 2006/012503 discloses a built in self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio and linearity measurements. The BIST scheme utilizes a built-in direct digital synthesiser as a test pattern generator that can generate various test waveforms such as chirp, ramp, step frequency, two- tone frequencies, sweep frequencies, MSK, phase modulation, amplitude modulation, QAM (quadrature amplitude modulation) and other hybrid modulations.

An object of the present invention is to improve of the testing of ICs including analog circuitry. According to a first aspect of the present invention there is provided a method of testing analog circuitry in an integrated circuit device, the method comprising applying test stimuli to a circuit under test, obtaining the responses of the circuit under test to the test stimuli and examining the responses to determine if the circuit under test is of an acceptable standard, characterised in that the test stimuli are generated using pulse width modulation (PWM) techniques.

According to a second aspect of the present invention there is provided an integrated circuit comprising an analog circuit and a built-in self test scheme having means to produce test stimuli by PWM techniques.

This invention proposes an alternative to the traditional functional tests applied during RF and AMS circuit testing. A feature of this invention is that it uses a PWM signal which is generated from different sources on-chip. The source that serves best for the test application depends on the frequency domain in which the circuit operates.

In implementing the method in accordance with the present invention the signal generation is done on-chip and, if needed, external frequencies are low frequency compared to the specific application. As a result the need for expensive test equipment is avoided. In addition, this invention meets the specific dynamics of the circuit. Generally, designers of RF/AMS circuits have derived a set of parameters to qualify the performance of their design. These parametric tests or specification tests consist of Gain, Signal-to-Noise Ratio (SNR), total harmonic distortion and noise (THD+N), second order intermodulation product (IP2), third order intermodulation product (IP3), and compression point (CP). These tests actually are a limited representation of the responses of the circuit. It targets the amplification, linearity, noise and harmonic/intermodulation distortion. Stated differently, most known tests target amplitude, noise and distortion level measurements use a limited set of one or two sinusoidal signals. These test signals, however, are always in the functional bandwidth of the circuit under test. This also implies that these test stimuli effectively target the dynamic characteristics of the design. As a result many of these parameters are taken by the test engineers for measurement during production testing. It is obvious that if the parameters chosen by the designer are typical for the qualification of the circuit, these parameter specifications must also be met by the production test. If not, the circuit fails the intended performance and is rejected. However, the designer only picks those parameters which are to his opinion sufficient for correct operation. Parametric defects often lead to marginal deviation from the specification test but may lead to fails in the field at the customer site.

In this respect the present invention uses test stimuli that are much richer in frequency content, compared to the traditional test stimuli as pointed out before. The generated test stimuli in this invention can also target the responses from the earlier mentioned specification based tests. The frequency content is optimal for linearity and distortion tests and amplitude can be varied as well targeting gain. The method in accordance with the present invention enables a high frequency test signal to be produced from low frequency signals, which is very advantageous for production testing. The relationship to the control theory is that this high frequency test signal is based upon functional frequency content of the CUT and that as such it is a good representation of an optimal test stimulus. Therefore the PWM signal meets the frequency and amplitude content also present in traditional functional test stimuli.

The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a block schematic diagram of an IC and illustrates testing in accordance with the IEEE 1149.1 and IEEE 1149.4 standards,

Figure 2 is a block schematic diagram illustrating an architecture for using a PWM signal on an analog CUT controlled by JTAG,

Figure 3 is a block schematic diagram of one embodiment of generating a PWM signal,

Figure 4 illustrates two examples of the spectral content of a produced PWM waveform, Figure 5 is a block schematic diagram of a second embodiment of generating a PWM signal,

Figure 6 is a block schematic diagram of a third embodiment of generating a PWM signal, Figure 7 illustrates an example of a test vector,

Figure 8 is a flow chart illustrating an embodiment of a test procedure, and

Figure 9 is a flow chart illustrating an embodiment of a process for analysing a response output of the test procedure. In the drawings the same reference numerals have been used to illustrate corresponding features.

As Figure 1 has been described already, the description will not be repeated. Figure 2 illustrates a device under test (DUT) 140 which comprises a radio receiver having an analog circuit under test (CUT) 142, a frequency synthesiser 146 consisting of a voltage controlled oscillator and a phase locked loop, and a digital block 144. The CUT 142 has two inputs 178, 179 and an output 143 and the CUT 142 may comprise in combination a RF section including a low noise amplifier at its input. The frequency synthesiser 140 has an output 148.

A JTAG controller 150 has TDI inputs 120, TDO outputs 122, a Test Mode select (not shown) and a test clock TCK 122. A PWM-enable register 152 comprises a flip-flop 151 having a signal-in (Sl) port 154, a TCK input 156 and a signal-out (SO) port 158 for a PWM enable bit. A PWM generator 160 has inputs 162, 164 and 165 for a test clock signal TCK, a PWM enable bit and a VCO signal, respectively. A multiplexer 166 has an input coupled to a source 169 of a sinusoidal signal, a first output port 172 for a sinusoidal signal which is applied to an input 170 of the PWM generator and a second output port 176 which is coupled to the input 178 of the analog CUT 142. The multiplexer 166 has a control input 168 for a PWM-enable bit derived from the PWM-enable register 152. An output 174 of the PWM generator 160 is coupled to a first input 182 of a multiplexer 180 which has an output coupled to the input 179 of the analog CUT 142. An input 184 of the multiplexer 180 is connected a functional signal input 185. A PWM-enable bit is applied to a control input 186 of the multiplexer 186.

In operation when the JTAG controller 150 initiates testing of the analog CUT 142, the PWM-enable register 152 is caused to produce a PWM- enable bit. In response to the PWM-enable bit, the multiplexer 166 switches the sinusoidal signal source to the PWM generator 160, the multiplexer 180 connects the output 174 of the PWM generator to the input 179 of the analog CUT 142 and the PWM generator uses the sinusoidal signal and the TCK signal on its input 162 to produce a test stimulus signal. At the end of the test the PWM-enable register inhibits the generation of the test stimulus signal and causes the multiplexer 166 to connect the sinusoidal signal source 169 to the output 176 and the demultiplexer 180 to connect the signal input 185 to the input 179 of the analog CUT 142. Now both inputs 169 and 185 can be used for normal functional application.

Figure 3 illustrates a first embodiment of the PWM generator 160. The embodiment uses the test clock TCK applied to the input 162. From test point of view this option is most convenient since now the PWM test is fully controlled by the JTAG controller 150 (Figure 2) and is completely independent of both the operational digital block144 as well as the analog CUT block 142. In test mode, the test clock TCK is applied to a clock buffer 190 which is enabled by a PWM-enable bit on the input 164. The clock buffer 190 is used to obtain a robust clock signal for the PWM generator. Alternatively, when not in test mode, the clock buffer 190 is disabled to prevent the PWM generator 160 producing high frequency signals that may impair the normal operation of the circuit due to electro-magnetic interference (EMI). In test mode the test clock TCK is fed by the clock buffer 190 to a RC filter 192. The RC filter 192 produces a saw-tooth or triangular waveform which is directed to an inverting input 196 of a comparator 194. The RC filter 192 may be a first order or second order low pass filter depending on the required accuracy for the sawtooth signal that is present after the filter. This saw-tooth signal is used in the comparator to make natural sampling used for example in Class D amplifiers possible. In order to have a suitable PWM signal with a sufficiently high frequency content for test to be made, a non-inverting input 197 of the comparator 194 is fed by a sinusoidal signal with a frequency at least 10 times lower than the saw-tooth frequency. A PWM output signal is derived from an output 198 of the comparator 194. The principle can be summarised by feeding two signals to the comparator 194 from which a rail-to-rail PWM signal is obtained. In effect the sawtooth signal acts as a reference against which the sinusoidal signal is compared. When the instantaneous value of the sinusoidal signal is greater than the reference value then a pulse is produced but when the converse occurs no pulse is produced, the mark-space ratio in the resultant PWM signal is variable.

The sinusoidal signal can be derived from an external tester output but may also be generated on-chip. The sinusoidal signal is a relatively low frequency signal which is easily and advantageously be received from external equipment. In Figure 3 it is assumed that the sinusoidal signal is derived externally by multiplexing with a functional (analog) signal. In normal operation the multiplexer directs the functional input signal on the input 185 (Figure 2) to the DUT 140. Varying the amplitude of the sinusoidal signal, which is easy to do, enables the amplitude variation or energy content of the PWM signal (targeting gain related failures).

For illustration, Figure 4 shows the spectral content of a real implementation in a BiCMOS process of the comparator 194 and low pass filter 192. The TCK is set to 10MHz in the lower diagram 210 and 33MHz in the upper diagram 212. The sinusoidal signal is 1 MHz. It is clear that there is a lot of high frequency content especially in the 33 MHz one. To obtain sufficient spectral content a 10x ratio is minimal as can be seen from the upper diagram 212. In functional operation these high frequency distorting components would normally be filtered out (i.e. by LC filters). However, in the present invention it is required to use this high frequency content as test stimuli for the analog circuit since it targets the functional bandwidth of the DUT. As can be seen the power of the harmonics of interest (i.e. 2e and 3e harmonic band) is still high since the PWM is a rail-to-rail signal. Also, it will be realized that with a 1 MHz sinusoidal signal, it is possible to test a DUT 140 with a 100MHz range.

The spectrum is scalable when other frequencies are supplied to the comparator 194. If the sinusoidal signal amplitude is changed while keeping the saw-tooth amplitude constant, the amplitude (energy) content of the PWM signal can be varied.

A limitation of using TCK for sampling is the limited bandwidth of the typical JTAG protocol. Usually, TCKmax < 100MHz which limits this option for PWM generation when very high RF circuits are targeted. However, for mixed signal type of circuits this option is not limiting.

Referring to Figure 5, a second embodiment of generating a PWM signal generation uses the VCO or PLL 146 (Figure 2) typically available in RF circuits to generate the sampling saw-tooth or triangular signal. This option is advantageous when TCK speed is too low to generate sufficient high spectral content in the bandwidth of the RF circuit. Figure 5 illustrates the option with the use of VCO/PLL on the input 165 of the PWM generator 160. The input 165 is applied to a buffer amplifier 190 which is enabled by a PWM- enable bit on the input 164. The output of the buffer amplifier 190 is applied to the inverting input 196 of the comparator 194. A sinusoidal signal on the input 170 is applied to the non-inverting input 197 of the comparator 194. A PWM signal is obtained from the output 198 of the comparator. Since the VCO produces normally an oscillator frequency close to modulation frequency, this VCO is a good way to produce the PWM signal. Generally, the VCO can be tuned through the N-divider, so this can also be used to tune the PWM signal frequency. Further the operation is similar as described with reference to Figures 3 and 4.

Figure 6 illustrates a third embodiment of a PWM generator 160. This embodiment is similar to the first embodiment except that the clock frequency is derived from a dedicated oscillator or from a system clock 210 which is built into the circuit as part of the built-in self test (BIST) solution. This option is advantageous for analog architectures where no PLL is available or for whatever reason cannot be used or where TCK is not present. Figure 6 illustrates the use of such oscillator 210 which can be made simply from a delayed inverter comparable to a ring oscillator. In hardware, an inverter 212 is connected to a delay line 214 having a feedback connection 216 to an input of the inverter 212. The PWM-enable bit is applied to the inverter 212 to enable the oscillator when in test mode. The delay introduced by the delay line 214 can be predefined to generate the oscillation frequency required to produce the correct spectral content from PWM. The same test JTAG control signal as used to control the multiplexers 166, 180 (Figure 2) is used for this purpose. The protocol for JTAG control is as follows: The standard states defined by IEEE1149.1 standard are used.

In an instruction register of the JTAG controller 150 (Figure 2) an additional instruction is implemented (i.e. PWM-TEST). This instruction selects a dedicated data control register (i.e. PWM-enable) for shifting data into. Since the control of the multiplexers 166 and 180 (Figure 2) and the PWM generator 160 (Figure 2) is simple the register only needs to be 1 bit wide. Alternatively, this PWM-enable bit can be derived from the JTAG controller 150. When the JTAG controller 150 is in run test idle state the test can be executed since the enable bit is already set by the instruction. However, shifting in data using a 1 bit register enables full control during test mode and is preferred. Here a further explanation of this feature will be given.

When test mode is invoked using the instruction "PWM-TEST", the JTAG controller 150 proceeds to the data shift cycle (SDR). During this SDR state, the PWM enable bit can be set by shifting in data through the TDI pin. At each TCK clock edge the bit value will be passed onto the "PWM enable bit" (the flip-flop 151 (Figure 2) clocks the data from D to Q). In other words, full control over the PWM generator 160 is provided by the bit value shifted into the PWM-enable register 152 (Figure 2) and also by the bit-stream length. During shift data register (SDR) the total PWM test time can be controlled by setting/resetting the bit value and by varying the length of the shifted code word. We call this the PWM-enable test vector. With this feature the test time is well controlled by the TCK clock. For example, the user may define a PWM-enable vector of 100 bit length which indicates a test time of 100^*Tτcκ.

The content of this PWM-enable vector determines if the PWM generator is on or off. When leaving SDR state after completing the shifted tested test vector (i.e. 100 bit), the JTAG protocol will complete the test cycle by disabling the PWM generator 160 and switching the multiplexers 166, 180 to functional operation.

Figure 7 illustrates an example of PWM test vector to be shifted into through TDI =>TDO. Code bits 1 to N are supplied to the TDI input 120 (Figure 2) of the JTAG controller 150. These bits have one of two values, either "1 " or "0". "1 " relates to the PWM generator 160 being on and "0" relates to the PWM generator being off. Thus in Figure 7 bits 1 to 5 have a value "0" so that the PWM-enable register 152 does not produce a PWM-enable bit and the PWM generator 160 does not produce test stimuli and the multiplexers 166, 180 are set in a functional input mode. The next 6 bits have a Value "1 " and the PWM-enable register 152 produces a PWM-enable bit which causes the PWM generator 160 to be active and applying test stimuli to the input 182 of the multiplexer 180 which together with the multiplexer 166 is switched to set a test state. As indicated by the sequences of "1 s" and "0s" in the test vector the PWM generator and the multiplexers 166, 180 are alternately in a test mode and a non-test mode. In the test mode control signals from the JTAG controller selects the correct multiplexing for the input PWM signal at the input 179 of the DUT 140 (Figure 2) and the observed output response signal on the output 143. By analysing the PWM output and using the high frequency content as the test signal it ensures that the test signal fits the bandwidth of the CUT.

Referring to the flow chart shown in Figure 8, an embodiment of a conceptual test procedure is shown. Test procedures using the PWM signal as a test signal are under development. At this stage in the development programme it is assumed that the functional core is set in normal conditions as would also be done for functional tests such as gain, second order intermodulation product (IP2) and others mentioned in this specification. In Figure 8 block 220 relates to invoking a test mode through JTAG specification. Block 222 relates to selecting a PWM register. Block 224 relates to putting the device under test (DUT) 140 (Figure 2) under test or in a user defined state. Block 226 relates to shifting-in the PWM test vector and using this data also as a trigger for data capture on external equipment. Block 228 relates to carrying-out the tests. Block 230 relates to checking if the testing operation has been completed. If the answer is yes (Y), the flow chart proceeds to block 232 which relates to analysing the test data. Alternatively, if the answer from block 230 is no (N) the flow chart reverts to the block 228. Figure 9 is a flow chart relating to analysing the output from the test procedure. The analysis may be done in several ways. What is believed to be a most suitable way will now be described with reference to Figure 9. Block 240 relates to the test vector being complete. Block 242 relates to capturing the signal using a fast sampler and a high resolution analog-to-digital converter (ADC) fitting the requirements of the DUT bandwidth. Such fast sampling equipment and high resolution ADC are obtainable as test equipment from commercial suppliers. Block 244 relates to carrying-out a Fast Fourier Transform (FFT) analysis and obtaining results. Block 246 relates to comparing the analysed results with a test reference such as a good known device. Differences in number of harmonics, amplitudes of harmonics and increased noise floor is an indication of a failing device. So, this FFT, must then be compared with the response signal of a good device. This data content from a good device can be stored in the test equipment as golden reference data and the responses from the DUT can be compared with this golden reference data. Finally, block 248 relates to obtaining the test results.

Depending on the criteria of the circuit , a tester may also decide to look selectively for harmonic levels not present in the golden reference or, if noise is the most critical factor, only to look at the differences in the noise floor. It is anticipated that, given time, smart algorithms will be developed to analyse the response of the DUT with a PWM input signal. The test procedure targets dynamic parametric failures, that is, non-linearities and compression in circuits (high frequency content in PWM spectrum) and gain issues (varying the amplitude of the PWM through the sinusoidal). For example gain is measured by comparing input and output levels; linearity is measured by varying the amplitude of the input signal and measuring the gain stability and distortion, that is unwanted frequency components, is measured from one or two tone input signals.

In the present specification and claims the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Further, the word "comprising" does not exclude the presence of other elements or steps than those listed.

The use of any reference signs placed between parentheses in the claims shall not be construed as limiting the scope of the claims. From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of test apparatus compliant with IEEE 1149.1 and 1149.4 standards therefor and which may be used instead of or in addition to features already described herein.

Claims

1. A method of testing analog circuitry in an integrated circuit device, the method comprising applying test stimuli to a circuit under test

(CUT), obtaining the responses of the circuit under test to the test stimuli and examining the responses to determine if the circuit under test is of an acceptable standard, characterised in that the test stimuli are generated using pulse width modulation (PWM) techniques.

2. A method as claimed in claim 1 , characterised in that the test stimuli are generated by comparing a sinusoidal signal with a triangular or saw tooth waveform.

3. A method as claimed in claim 2, characterised in that the sinusoidal signal has a lower frequency than the triangular or saw tooth waveform.

4. A method as claimed in claim 2, characterised in that the sinusoidal signal has a frequency at least ten times lower than that of the triangular or saw tooth waveform.

5. A method as claimed in claim 2, 3 or 4, characterised in that there are a plurality of on-chip PWM sources and in that a selected one of the plurality of PWM sources is selected by a Joint Test Access group (JTAG) instruction.

6 A method as claimed in claim 2, characterised in that a triangular or saw tooth waveform is produced by applying a clock signal to a low pass filter (192).

7. A method as claimed in claim 6, characterised in that the clock signal is a Joint Test Access Group (JTAG) TCK signal.

8. A method as claimed in claim 6, characterised in that the clock signal is generated by a delayed inverter (210).

9. A method as claimed in claim 2, characterised in that the triangular or saw tooth waveform is generated using an on-chip voltage controlled oscillator (VCO).

10. A method as claimed in any one of claims 1 to 9, characterised in that the test mode is invoked on-chip.

11. A method as claimed in any one of claims 1 to 10, characterised in that the method is controlled by a test mode implemented in a standard Joint

Test Access Group (JTAG) protocol.

12. A method as claimed in claim 11 , characterised in that the test mode is invoked using a PWM-TEST instruction and in response to the instruction a JTAG controller proceeds to a data shift cycle.

13. A method as claimed in claim 12, characterised in that data is shifted-in using a 1 bit register.

14. An integrated circuit comprising an analog circuit and a built-in self test scheme having means to produce test stimuli by PWM techniques.

15. An integrated circuit as claimed in claim 14, characterised in that the means to produce test stimuli comprises means ((190, 192,194; 192, 194, 214; 190) for producing a triangular or saw tooth waveform, means for deriving a sinusoidal signal and a comparator (194) having inputs (196,197) for the triangular or saw tooth waveform and the sinusoidal signal and an output (198) for the test stimuli.

16. An integrated circuit as claimed in claim 12, characterised in that the sinusoidal signal has a lower frequency than that of the triangular or saw tooth waveform.

17. An integrated circuit as claimed in claim 15, characterised in that the sinusoidal signal has a frequency which at least 10 times lower than that of the triangular or saw tooth waveform.

18. An integrated circuit as claimed in any one of claims 10 to 17, characterised by a plurality of means for producing PWM stimuli and means responsive to a dedicated JTAG signal for selecting one of the said means.

19. An integrated circuit as claimed in any one claims 14 to 18, characterised by a 1 -bit register for shifting-in data.