WO2010023499A1 - Procédé pour la synthèse de réseaux de communication sur puce asynchrones optimaux à partir de contraintes de niveau système - Google Patents

Procédé pour la synthèse de réseaux de communication sur puce asynchrones optimaux à partir de contraintes de niveau système Download PDF

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Publication number
WO2010023499A1
WO2010023499A1 PCT/IB2008/003568 IB2008003568W WO2010023499A1 WO 2010023499 A1 WO2010023499 A1 WO 2010023499A1 IB 2008003568 W IB2008003568 W IB 2008003568W WO 2010023499 A1 WO2010023499 A1 WO 2010023499A1
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WO
WIPO (PCT)
Prior art keywords
network
components
component
byte
library
Prior art date
Application number
PCT/IB2008/003568
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English (en)
Inventor
David Fritz
Original Assignee
David Fritz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by David Fritz filed Critical David Fritz
Priority to PCT/IB2008/003568 priority Critical patent/WO2010023499A1/fr
Publication of WO2010023499A1 publication Critical patent/WO2010023499A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/35—Delay-insensitive circuit design, e.g. asynchronous or self-timed

Definitions

  • FIG. 1 is a top level flow chart in accordance with the present invention.
  • FIG. 2 shows data being attached to a network component port.
  • the "derive connectivity network process” 110 creates the first approximation of a completely functional, though perhaps suboptimal, ANoC network.
  • the cluster derivation process 302 uses TDM techniques to minimize the likelihood of arbitration between the processing blocks within S, and utilizes the concept of communication locality to provide candidate processing blocks.
  • step 310 is a TX component.
  • find component will be described as a subroutine 600 and the desired component to be found is simply the argument passed to logic flow 600. If step 306 determines that a TX component has been assigned to the instant component (in a previous iteration of the loop comprising steps 304 to 318) the TX component is checked at step 308 to see if an additional switch is needed, step 308 detailed further in FIG. 5 as logical flow 500.
  • step 712 tests to see if any improvement has been made as a result of the flow 700. If TRUE, the process is repeated from step 702 until FALSE, signifying that no further improvement is available. It is possible that some error in slack (that is, any negative slack) has been introduced during the optimization process.
  • FIG. 14 illustrates a "fix up slack process" 714, which walks the optimized network and increases the size of components in an attempt to resolve any negative slack situations that exist in the network. The test for each component's slack is step 1402. If negative slack is found step 1404 looks for a larger component in the component library (flow 600), replacing the instant component with that found by step 1404.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention offre aux concepteurs de puces un moyen de profiter d'une interconnexion ANoC, la combinaison de deux technologies, les circuits asynchrones et le réseau sur puce (ANoC), leur permettant de concevoir des puces importantes plus facilement et plus rapidement qu'avant. Le concepteur développe une table d'exigences d'interconnexion, en spécifiant les connexions souhaitées et certaines contraintes telles que la surface, la puissance et la latence. L'invention développe un réseau de connectivité à l'aide d'une bibliothèque de composants caractérisés, puis optimise le réseau par la sélection de divers composants alternatifs provenant de la bibliothèque et l'examen des combinaisons de largeur de lien alternatives. Le réseau optimisé est vérifié par rapport aux exigences prédéterminées. Si la vérification est concluante, un fichier de matrice est obtenu. Si la vérification n'est pas concluante, le processus d'optimisation est répété à condition que certaines améliorations aient été faites.
PCT/IB2008/003568 2008-08-25 2008-08-25 Procédé pour la synthèse de réseaux de communication sur puce asynchrones optimaux à partir de contraintes de niveau système WO2010023499A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/IB2008/003568 WO2010023499A1 (fr) 2008-08-25 2008-08-25 Procédé pour la synthèse de réseaux de communication sur puce asynchrones optimaux à partir de contraintes de niveau système

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2008/003568 WO2010023499A1 (fr) 2008-08-25 2008-08-25 Procédé pour la synthèse de réseaux de communication sur puce asynchrones optimaux à partir de contraintes de niveau système

Publications (1)

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WO2010023499A1 true WO2010023499A1 (fr) 2010-03-04

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PCT/IB2008/003568 WO2010023499A1 (fr) 2008-08-25 2008-08-25 Procédé pour la synthèse de réseaux de communication sur puce asynchrones optimaux à partir de contraintes de niveau système

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030115564A1 (en) * 1998-09-30 2003-06-19 Cadence Design Systems, Inc. Block based design methodology
US20040044514A1 (en) * 2002-09-04 2004-03-04 Granny Nicola V. Polymorphic computational system and method in signals intelligence analysis
US20080049628A1 (en) * 2006-08-22 2008-02-28 Bugenhagen Michael K System and method for modifying connectivity fault management packets
US20080082786A1 (en) * 2006-10-02 2008-04-03 William Stuart Lovell Super-scalable, continuous flow instant logic™ binary circuitry actively structured by code-generated pass transistor interconnects

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030115564A1 (en) * 1998-09-30 2003-06-19 Cadence Design Systems, Inc. Block based design methodology
US20040044514A1 (en) * 2002-09-04 2004-03-04 Granny Nicola V. Polymorphic computational system and method in signals intelligence analysis
US20080049628A1 (en) * 2006-08-22 2008-02-28 Bugenhagen Michael K System and method for modifying connectivity fault management packets
US20080082786A1 (en) * 2006-10-02 2008-04-03 William Stuart Lovell Super-scalable, continuous flow instant logic™ binary circuitry actively structured by code-generated pass transistor interconnects

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