WO2010021213A1

WO2010021213A1 - Magnetoresistive storage device

Info

Publication number: WO2010021213A1
Application number: PCT/JP2009/062713
Authority: WO
Inventors: 有光加藤
Original assignee: 日本電気株式会社
Priority date: 2008-08-18
Filing date: 2009-07-14
Publication date: 2010-02-25

Abstract

A magnetoresistive storage device includes: a first structure (6), a second structure (9), a temperature increase means (11), and a magnetization direction setting means (12). The first structure (6) is formed by a first magnetic body (1) having a fixed magnetization direction, a first non-magnetic body (2), and a second magnetic body (3) having a magnetization state changed by data which are layered on one another. The second structure (9) is formed by antiferromagnetic material (7) and a third magnetic body (8) which are layered on each other. The temperature increase means (11) increases the temperature of the antiferromagnetic material (7) to a desired temperature. The magnetization direction setting means (12) orients the magnetization direction of the third magnetic body (8) to a desired direction. The antiferromagnetic material (7) is exchange-coupled to the third magnetic body (8). The second magnetic body (3) is magnetically coupled to the third magnetic body (8).

Description

Magnetoresistive memory device

The present invention relates to a magnetoresistive storage device that stores data as a resistance value using a magnetic material.

A magnetic random access memory (MRAM: Magnetic Random Access Memory) is known as an example of a device that stores a resistance value using a magnetic material. MRAM is a promising nonvolatile memory from the viewpoint of high integration and high-speed operation. In the MRAM, a magnetoresistive element exhibiting a “magnetoresistance effect” such as a TMR (Tunnel MagnetoResistance) effect is used. In the magnetoresistive element, for example, a magnetic tunnel junction (MTJ; Magnetotunic Tunnel Junction) in which a tunnel barrier layer is sandwiched between two ferromagnetic layers is formed. The two ferromagnetic layers are composed of a pinned layer (magnetization pinned layer) whose magnetization direction is fixed and a free layer (magnetization free layer) whose magnetization direction is reversible (Roy Scheuerlein et al. , “A 10 ns Read and Write Non-Volatile Memory Array Usage a Magnetic Tunnel Junction and FET SwitchinEachNeSNRC”, 2000 IEEE InternalCRS. reference).

The resistance value (R + ΔR) of the MTJ when the magnetization directions of the pinned layer and the free layer are “anti-parallel” is larger than the resistance value (R) when they are “parallel” due to the magnetoresistance effect. It is known. The MRAM uses the magnetoresistive element having the MTJ as a memory cell, and stores data in a nonvolatile manner by utilizing the change in the resistance value. Data is written to the memory cell by reversing the magnetization direction of the free layer.

The asteroid method is known as a method of writing data to the MRAM (M. Durlam et al., “Nonvolatile RAM based on Magnetic Junction Elements”, 2000 IEEE International International Solid-StateCirC: 130-131 .: see non-patent document 2). According to the asteroid method, the reversal magnetic field necessary for reversing the magnetization of the free layer increases in inverse proportion to the memory cell size. That is, the write current tends to increase as the memory cell is miniaturized. Such a tendency is not preferable for miniaturization of memory cells and increase in capacity of MRAM.

“Spin injection method” has been proposed as a write method that can suppress an increase in write current due to miniaturization (Yagami and Suzuki, “Research Trends in Spin Transfer Magnetizing Switching” (research trend of spin injection magnetization reversal). ), Journal of Japan Society of Applied Magnetics, Vol. 28, No. 9, 2004, pp. 937-948: Non-patent document 3). According to the spin transfer method, a spin-polarized current is injected into a ferromagnetic conductor, and a direct interaction between the spin of a conduction electron carrying the current and the magnetic moment of the conductor is performed. Magnetization is reversed (hereinafter referred to as “Spin Transfer Magnetization Switching”).

Spin inversion magnetization reversal will be described with reference to the drawings. FIG. 1 is a diagram for explaining data writing using spin injection magnetization reversal. In FIG. 1, the magnetoresistive element includes a free layer 101, a pinned layer 103, and a tunnel barrier layer 102 that is a nonmagnetic layer sandwiched between the free layer 101 and the pinned layer 103. Here, the pinned layer 103 whose magnetization direction is fixed is formed so as to be thicker than the free layer 101, and plays a role as a mechanism (spin filter) for creating a spin-polarized current. The state where the magnetization directions of the free layer 101 and the pinned layer 103 are parallel is associated with data “0”, and the state where they are antiparallel is associated with data “1”.

The spin injection magnetization reversal shown in FIG. 1 is realized by a CPP (Current Perpendicular to Plane) method, and a write current is injected perpendicularly to the film surface. Specifically, current flows from the pinned layer 103 to the free layer 101 at the time of transition from data “0” to data “1”. In this case, electrons having the same spin state as the pinned layer 103 as a spin filter move from the free layer 101 to the pinned layer 103. Then, the magnetization of the free layer 101 is reversed by a spin transfer (spin angular momentum transfer) effect. On the other hand, at the transition from data “1” to data “0”, the direction of the current is reversed, and the current flows from the free layer 101 to the pinned layer 103. In this case, electrons having the same spin state as the pinned layer 103 as a spin filter move from the pinned layer 103 to the free layer 101. Due to the spin transfer effect, the magnetization of the free layer 101 is reversed.

Thus, in spin injection magnetization reversal, data is written by the movement of spin electrons. The direction of magnetization of the free layer 101 can be defined by the direction of the spin-polarized current injected perpendicular to the film surface. Here, it is known that the threshold for writing (magnetization reversal) depends on the current density. Therefore, as the memory cell size is reduced, the write current required for magnetization reversal decreases. Since the write current decreases with the miniaturization of the memory cell, the spin transfer magnetization reversal is important for realizing the large capacity of the MRAM and the miniaturization of the memory cell.

As a related technique, JP-A-2005-150303 (Patent Document 1) describes a magnetoresistive effect element and a magnetic memory. This magnetoresistive effect element has a ferromagnetic tunnel junction including a three-layer structure of a first ferromagnetic layer / tunnel barrier layer / second ferromagnetic layer. The coercive force of the first ferromagnetic layer is greater than the coercivity of the second ferromagnetic layer. The magnetization of the end portion of the second ferromagnetic layer is fixed in a direction having a component orthogonal to the easy axis direction of the second ferromagnetic layer.

The above example is a method of storing two pieces of information using two easy magnetization directions of the free layer. On the other hand, there is also a method for storing information by using an exchange bias magnetic field acting between the pinned layer and the antiferromagnetic material layer. For example, Japanese Patent No. 2967980 (Patent Document 2) describes a magnetic surname memory. 2A and 2B are cross-sectional views showing the configuration of this magnetic memory. As shown in FIGS. 2A and 2B, this magnetic memory has a structure in which an antiferromagnetic layer 110, a magnetic pinned layer 111, a nonmagnetic layer 112, and a magnetic sense layer 113 are stacked. In writing data to the magnetic memory, when the antiferromagnetic layer 110 is heated and cooled, a magnetic field in a direction corresponding to the data is applied to the magnetic pinned layer 111. Thereby, the magnetization direction of the magnetic pinned layer 111 faces the direction of the applied magnetic field. For this reason, the magnetization state of the antiferromagnetic layer 110 changes corresponding to the direction of the exchange bias magnetic field acting between the magnetic pinned layer 111 and the antiferromagnetic layer 110, and data is stored in the magnetic memory. The However, FIG. 2A shows a high resistance state, and FIG. 2B shows a low resistance state.

As a related technique, Japanese Patent Laid-Open No. 2002-117510 (Patent Document 3) describes a method and system for providing a TMR sensor using a hard magnetic material that deflects a free layer. This magnetoresistive sensor reads data from a recording medium, and includes a free layer, a pin layer, a barrier layer, and a hard magnetic layer. The free layer has ferromagnetism and has a first side and a second side opposite to the first side. The pinned layer has a magnetization direction and is ferromagnetic. The direction of magnetization of the pinned layer is fixed in a specific direction. This pinned layer is on the first side of the free layer. The barrier layer separates the first-side free layer and the pinned layer. This barrier layer is an insulating layer having a thickness sufficient to allow a tunnel of charged particles between the pinned layer and the free layer. The hard magnetic layer is on the second side of the free layer. This hard magnetic layer magnetically deflects the free layer.

As a related technique, Japanese Unexamined Patent Application Publication No. 2003-124541 (Patent Document 4) discloses an exchange coupling film, a magnetoresistive effect element, a magnetic head, and a magnetic random access memory. This exchange coupling film includes an antiferromagnetic material layer, an exchange coupling imparting layer, and an exchange coupling enhancement layer. The antiferromagnetic material layer is made of a disordered alloy. The exchange coupling imparting layer is made of a ferromagnetic material of Co or a CoFe alloy having a face-centered cubic crystal structure and is in contact with the antiferromagnetic material layer to provide exchange coupling at the interface with the antiferromagnetic material layer. The exchange coupling enhancement layer is disposed on the surface opposite to the antiferromagnetic layer in the exchange coupling imparting layer and is made of a ferromagnetic material of Fe or a body-centered cubic CoFe alloy and is provided by the exchange coupling imparting layer. Amplify exchange bonds.

As a related technique, a magnetoresistive memory device is disclosed in Japanese Patent Laid-Open No. 2005-116658 (Patent Document 5). In this magnetoresistive memory device, a plurality of word lines and bit lines and a plurality of magnetoresistive memory elements are arranged. The plurality of word lines and bit lines intersect on the semiconductor substrate in a non-contact manner to form a matrix. A plurality of magnetoresistive memory elements are formed by laminating a free layer having a variable magnetization direction and a magnetization fixed layer having a fixed magnetization direction interposed between the plurality of bit lines and the word lines and intersecting each other through an insulating layer. ing. The magnetoresistive memory device writes magnetization information to a magnetoresistive memory element at an intersection selected by a magnetizing current flowing through the bit line and the word line, and detects a resistance change of the current flowing through the magnetoresistive memory element by a tunnel effect. To read the magnetization information. The plurality of magnetoresistive memory elements are arranged at positions deviated from the intersections of the plurality of bit lines and word lines, and the free layer magnetism of each magnetoresistive memory element is disposed between the bit lines and the word lines at each intersection. The free layer extension part which extended only the body is arrange | positioned non-contactingly.

As a related technique, Japanese Patent Application Laid-Open No. 2007-220945 (Patent Document 6) discloses a magnetoresistive effect element, a magnetic head, a magnetic reproducing device, and a method of manufacturing a magnetoresistive element. The magnetoresistive effect element includes a magnetoresistive effect film, a magnetic coupling layer, a ferromagnetic layer, an antiferromagnetic layer, a bias mechanism part, and a pair of electrodes. The magnetoresistive film includes a magnetization free layer having a magnetic film whose magnetization direction changes according to an external magnetic field, a magnetization fixed layer having a magnetic film whose magnetization direction is substantially fixed to one side, An intermediate layer disposed between the magnetization free layer and the magnetization pinned layer. The magnetic coupling layer is disposed on the magnetization pinned layer of the magnetoresistive effect film. The ferromagnetic layer is disposed on the magnetic coupling layer. The antiferromagnetic layer is disposed on the ferromagnetic layer. The bias mechanism unit applies a bias magnetic field to the magnetization free layer in a direction substantially parallel to the film surface of the magnetoresistive film and substantially perpendicular to the magnetization direction of the magnetization pinned layer. The pair of electrodes energize the magnetoresistive film with a current in a direction from the magnetization fixed layer to the magnetization free layer. Bias point is greater than 50%.

JP 2005-150303 A Japanese Patent No. 2967980 JP 2002-117510 A JP 2003-124541 A JP-A-2005-116658 JP 2007-220945 A

The inventors' research has revealed that there is a correlation between the magnitude of the write current and the thermal disturbance tolerance of data storage. That is, it has been found that the more data can be written at a lower current, the more likely data destruction occurs due to thermal disturbance, and it is difficult to ensure reliability even when the current is reduced. In the case of a magnetoresistive element using an exchange bias magnetic field, it is necessary to heat an antiferromagnetic layer in contact with the magnetic pinned layer, and a tunnel insulating film (nonmagnetic) in contact with the other surface of the magnetic pinned layer. The body layer) is also heated. At this time, the element characteristics fluctuated due to material diffusion between the tunnel insulating film and the peripheral material and alteration of the tunnel insulating film itself, and it became clear that it was difficult to ensure the element life and reliability. A highly reliable magnetoresistive memory device having high thermal disturbance resistance is desired. In general, a magnetoresistive element using the easy magnetization direction of the free layer has only two easy magnetization directions. Further, the inventors' research has revealed that control becomes extremely difficult when the easy magnetization direction is set to multiple directions. That is, it is difficult to store multiple values in one magnetoresistive element. A magnetoresistive storage device capable of multi-value storage is required.

An object of the present invention is to provide a magnetoresistive memory device having high thermal disturbance resistance and high reliability.

The magnetoresistive storage device of the present invention includes a first structure, a second structure, a temperature raising means, and a magnetization direction setting means. The first structure is formed by laminating a first magnetic body whose magnetization direction is fixed, a first nonmagnetic body, and a second magnetic body whose magnetization state changes according to data. The second structure is formed by laminating an antiferromagnetic material and a third magnetic material. The temperature raising means raises the temperature of the antiferromagnetic material to a desired temperature. The magnetization direction setting means directs the magnetization direction of the third magnetic body in a desired direction. The antiferromagnetic material and the third magnetic material are exchange coupled. The second magnetic body and the third magnetic body are magnetically coupled.

The magnetoresistive memory device writing method of the present invention comprises preparing the above magnetoresistive memory device, raising the temperature of the antiferromagnetic material to a desired temperature by the temperature raising means, and applying the third magnetic property by the magnetization direction setting means. Setting the magnetization direction of the body to a direction corresponding to the data to be written, and stopping the temperature raising means and the magnetization direction setting means to lower the temperature of the antiferromagnetic material and fixing the magnetization direction of the third magnetic material. It has.

According to the present invention, it is possible to provide a highly reliable magnetoresistive memory device that is highly resistant to thermal disturbance and capable of multi-value storage.

FIG. 1 is a diagram for explaining data writing using spin injection magnetization reversal in the related art. FIG. 2A is a cross-sectional view showing a configuration of a magnetic memory in the related art. FIG. 2B is a cross-sectional view showing a configuration of a magnetic memory in the related art. FIG. 3A is a schematic cross-sectional view showing the configuration of the main part of the magnetoresistive memory element in the magnetoresistive memory device according to the embodiment of the present invention. FIG. 3B is a schematic cross-sectional view showing a configuration of a main part of the magnetoresistive memory element in the magnetoresistive memory device according to the embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of the memory array portion of the magnetoresistive memory device as a first example according to the embodiment of the present invention. FIG. 5 is a cross-sectional view showing a configuration of a main part of a magnetoresistive memory device as a first example according to the embodiment of the present invention. FIG. 6 is a top view showing a configuration of a main part of the magnetoresistive memory device as a first example according to the embodiment of the present invention. FIG. 7 is a circuit diagram showing a configuration of a memory array portion of a magnetoresistive memory device as a second example according to the embodiment of the present invention. FIG. 8 is a cross-sectional view showing a configuration of a main part of a magnetoresistive memory device as a second example according to the embodiment of the present invention. FIG. 9 is a top view showing a configuration of a main part of a magnetoresistive memory device as a second example according to the embodiment of the present invention. FIG. 10 is a circuit diagram showing a configuration of a memory array section of a magnetoresistive storage device as a third example according to the embodiment of the present invention. FIG. 11A is a cross-sectional view showing a configuration of a main part of a magnetoresistive memory device as a third example according to the embodiment of the present invention. FIG. 11B is a cross-sectional view showing a configuration of a main part of a magnetoresistive memory device as a third example according to the embodiment of the present invention. FIG. 12 is a top view showing a configuration of a main part of a magnetoresistive memory device as a third example according to the embodiment of the present invention. FIG. 13 is a circuit diagram showing a configuration of a memory array portion of a magnetoresistive memory device as a fourth example according to the embodiment of the present invention. FIG. 14A is a cross-sectional view showing a configuration of a main part of a magnetoresistive memory device as a fourth example according to the embodiment of the present invention. FIG. 14B is a cross-sectional view showing a configuration of a main part of a magnetoresistive memory device as a fourth example according to the embodiment of the present invention.

Hereinafter, embodiments of the magnetoresistive storage device of the present invention will be described with reference to the accompanying drawings. 3A and 3B are schematic cross-sectional views showing the configuration of the main part of the magnetoresistive memory element in the magnetoresistive memory device according to the embodiment of the present invention.

(Description of configuration)
The magnetoresistive memory device has a plurality of magnetoresistive memory elements. 3A and 3B show only one magnetoresistive memory element. Each magnetoresistive memory element includes a read structure 6, a memory structure 9, a temperature raising means 11, and a magnetization direction setting means 12. The readout structure 6 includes a first magnetic body 1, a first nonmagnetic body 2, a second magnetic body 3, a first terminal 4, and a second terminal 5. The first magnetic body 1 has a fixed magnetization direction. The first nonmagnetic body 2 is provided between the first magnetic body 1 and the second magnetic body 3. The magnetization state of the second magnetic body 3 changes according to data. The first magnetic body 1, the first non-magnetic body 2, and the second magnetic body 3 constitute an MTJ. The first terminal 4 is electrically connected to the first magnetic body 1. The second terminal 5 is electrically connected to the second magnetic body 3. The memory structure 9 includes an antiferromagnetic material 7 and a third magnetic material 8. The third magnetic body 8 is coupled to the antiferromagnetic body 7 by an exchange bias magnetic field. The temperature raising means 11 heats the antiferromagnetic material 7 to the first temperature 10. The magnetization direction setting means 12 sets the magnetization direction of the third magnetic body 8 to a desired direction.

The second magnetic body 3 and the third magnetic body 8 are magnetically coupled via a static magnetic field. The first temperature 10 at the time of heating by the temperature raising means 11 is such that when the magnetic field in a direction different from the initial magnetization direction of the third magnetic body 8 is applied to the third magnetic body 8, The temperature at which the magnetization direction of the magnetic body 8 and the magnetization state of the antiferromagnetic body 7 change. The amount of change due to this change is preferably as high as possible, but is preferably an amount that exceeds 50% as a discriminable range. More preferably, it is 100%. The magnetization directions of the first magnetic body 1 and the second magnetic body 3 are in two parallel planes. The magnetization direction of the third magnetic body 8 may be in the same parallel plane or in another different plane.

The temperature raising means 11 may be provided for each magnetoresistive memory element as shown in the figure, or may be provided for each of a plurality of magnetoresistive memory elements or for the entire magnetoresistive memory device. . Similarly, the magnetization direction setting means 12 may be provided for each magnetoresistive memory element as shown in the figure, or one for each of the plurality of magnetoresistive memory elements or the entire magnetoresistive memory device. Also good. Furthermore, the temperature raising means 11 and the magnetization direction setting means 12 may be integrated.

(Write operation)
Next, the write operation of the magnetoresistive memory device according to this embodiment will be described. The writing operation is performed by heating the antiferromagnetic body 7 to the first temperature 10 by the temperature raising means 11 and setting the magnetization direction of the third magnetic body 8 by the magnetization direction setting means 12.

That is, first, (1) the antiferromagnet 7 is heated to the first temperature 10 by the temperature raising means 11 and a magnetic field corresponding to the data written to the third magnetic body 8 is generated by the magnetization direction setting means 12. Let At this time, either the temperature raising means 11 or the magnetization direction setting means 12 may be started earlier or at the same time. As a result, the magnetization direction of the third magnetic body 8 changes to a direction corresponding to the data to be written. At this time, since the antiferromagnetic body 7 is at the first temperature 10, the magnetization state of the antiferromagnetic body 7 changes according to the magnetization state of the third magnetic body 8. That is, by setting the magnetization direction of the third magnetic body 8 to a direction corresponding to the data to be written, the magnetization state of the antiferromagnetic body 7 is also supported, that is, a state corresponding to the data to be written. Become. As for the heating temperature, the blocking temperature of the antiferromagnetic material (for example, PtMn) is about 250 ° C., and considering that the device can be used at about 150 ° C., the heating temperature is between 200 ° C. and above. It is desirable to be. The reason why the temperature may be lower than the blocking temperature is that, in antiferromagnetic materials, a magnetization change occurs in units of grains (magnetization change occurs from grains with a small energy barrier), and even if all the grains do not change, some degree This is because there is no problem if the grain changes. The upper limit of the temperature is about 400 ° C. due to the limitation of suppressing the deterioration of characteristics of the MTJ tunnel film (first nonmagnetic material 2).

Thereafter, (2) the temperature raising means 11 and the magnetization direction setting means 12 are stopped. At this time, the order of stopping the temperature raising means 11 first and then stopping the magnetization direction setting means 12 is desirable. If the magnetization direction setting means 12 is stopped first when the temperature of the antiferromagnetic body 7 is high to some extent, the magnetization state of the third magnetic body 8 is disturbed by thermal disturbance, and the state of the antiferromagnetic body 7 is also disturbed. This is because it is expected. By stopping the temperature raising means 11, the antiferromagnetic material 7 and the third magnetic material 8 are cooled. After cooling, since the magnetization state of the antiferromagnetic material 7 does not change, the magnetization direction of the third magnetic material 8 is fixed as set by the magnetization direction setting means 12. In this way, data is written by fixing the magnetization direction of the third magnetic body 8 in a desired direction. That is, data is written to the storage structure 9. The magnetization direction of the third magnetic body 8 can be any direction that can be directed as long as the magnetization direction setting means 12 corresponds.

Here, the third magnetic body 8 is coupled to the second magnetic body 3 via a static magnetic field. Therefore, when the magnetization direction of the third magnetic body 8 changes corresponding to the data writing, the magnetization direction of the second magnetic body 3 also changes in a direction corresponding to the written data. That is, data is also written into the read structure 6.

FIG. 3A shows a low resistance state (resistance value: R) in which the magnetization direction of the first magnetic body 1 and the magnetization direction of the second magnetic body 3 are “parallel”. Can be associated. On the other hand, FIG. 3B shows a high resistance state (resistance value: R + ΔR) in which the magnetization direction of the first magnetic body 1 and the magnetization direction of the second magnetic body 3 are “anti-parallel”. 1 ". In addition, since the magnetization direction of the third magnetic body 8 can be any direction as described above, the magnetization direction of the second magnetic body 3 that is magnetically coupled to the third magnetic body 8 is also the same. All directions are possible. Accordingly, the magnetization direction of the second magnetic body 3 can be set to an intermediate state between the “parallel” state in FIG. 3A and the “antiparallel” state in FIG. 3B. By using the intermediate state (s), not only data “0” and “1” but also other data can be stored. That is, multivalue storage can be performed by associating a plurality of data with a plurality of directions.

(Read operation)
Next, the read operation of the magnetoresistive memory device according to this embodiment will be described. In the read operation, the written data is determined by evaluating the resistance value between the first terminal 4 and the second terminal 5 of the read structure 6.

The resistance value is determined by the difference in magnetization direction (eg, angle) between the first magnetic body 1 and the second magnetic body 3. If the magnetization direction of the first magnetic body 1 and the magnetization direction of the second magnetic body 3 are in a “parallel” state (angle 0 degree), a low resistance state (resistance value: R) is obtained. On the other hand, if it is in an “antiparallel” state (angle 180 degrees), it becomes a high resistance state (resistance value: R + ΔR). In the intermediate state, an intermediate resistance state (resistance value: R + Δr, 0 <Δr <ΔR) is obtained. Specifically, since the magnetization direction of the first magnetic body 1 is fixed, it is determined by the magnetization direction of the second magnetic body 3. As described above, since the magnetization direction of the second magnetic body 3 is a direction corresponding to the written data, the resistance value is determined by the written data.

As a specific example of the reading method, first, (1) a constant voltage or a constant current is applied between the first terminal 4 and the second terminal 5. (2) The current generated between the first terminal 4 and the second terminal 5 and the voltage generated by passing the current are compared with the reference value, and the magnetoresistive memory element (reading structure 6) Determine the resistance state. Data can be read out by determining the resistance state.

According to the present embodiment, it is the antiferromagnetic material 7 of the memory structure 9 that is heated in the write operation. The third magnetic body 8 in contact with the antiferromagnetic body 7 is also heated to the same extent. However, since the readout structure 6 is arranged away from these (interlayer insulating film is interposed), the temperature rise is small. For this reason, the temperature rise of the 1st nonmagnetic body 2 (tunnel insulating film) can be made small compared with the structure of the related art described in FIG. 2A and FIG. 2B. Thereby, material diffusion and alteration between the tunnel insulating film and the peripheral material due to thermal diffusion can be significantly suppressed. As a result, it is possible to suppress deterioration in reliability due to variations in element characteristics.

3A and 3B, the positional relationship between the readout structure 6 and the storage structure 9 overlaps. That is, when the surface of the second magnetic body 3 is projected perpendicularly to the surface of the semiconductor substrate onto the surface of the third magnetic body 8, the projection of the surface of the second magnetic body 3 is the same as the surface of the third magnetic body 8. overlapping. However, if the third magnetic body 8 is coupled to the second magnetic body 3 through a static magnetic field, the positional relationship between the readout structure 6 and the storage structure 9 does not overlap at all. Also good. Here, the distance between the antiferromagnetic material 7 and the first non-magnetic material 2 has been about several nanometers in the past (FIGS. 2A and 2B), but is preferably at least wider, for example, 100 nm apart.

Each magnetic body may be a single layer, a structure in which a plurality of magnetic bodies are stacked, or a structure in which a plurality of magnetic bodies are magnetically coupled via a non-magnetic body. Further, the magnetization fixing method of the first magnetic body 1 may be, for example, a method using a laminated structure of the first magnetic body 1 and an antiferromagnetic body that is antiferromagnetically coupled, or a long shape anisotropy that is long in one direction. This is done by giving It is desirable that the magnetization directions of the second magnetic body 3 and the third magnetic body 8 are easily changed by the magnetostatic coupling with the third magnetic body 8 and the magnetization direction setting means 12. For this reason, when using a magnetic body in which magnetization is easily oriented in the in-plane direction, the shape is most preferably a circular shape having no shape anisotropy. In the case of a circular shape, the magnetization direction is easy to be directed in all directions, so that it is excellent in multivalue storage. In addition, since the magnetic material also has magnetocrystalline anisotropy, in order to provide a shape anisotropy that cancels this, it may be desirable to use an elliptical shape. When using a magnetic material whose magnetization is easily oriented in a direction perpendicular to the surface, the magnetization direction is easily changed by a method such as thinning. In addition, both can be realized by a magnetic material or a film configuration. Examples of the magnetoresistive memory device according to the embodiment of the present invention will be described below.

(First embodiment)
Next, a first example according to the embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing the configuration of the memory array portion of the magnetoresistive memory device as a first example according to the embodiment of the present invention. FIG. 5 is a cross-sectional view showing a configuration of a main part of a magnetoresistive memory device as a first example according to the embodiment of the present invention. FIG. 6 is a top view showing a configuration of a main part of the magnetoresistive memory device as a first example according to the embodiment of the present invention.

Referring to FIG. 4, the memory array unit 63 of the magnetoresistive memory device includes a plurality of word lines 50, a plurality of bit lines 51, a plurality of read structures 52, a plurality of memory structures 53, and a plurality of memory structures 53. A selection transistor 54, a word line control circuit 61, and a bit line control circuit 62 are provided. The plurality of word lines 50 extend in one direction (X direction). The plurality of bit lines 51 extend in one direction (Y direction). The plurality of read structures 52 are arranged in an array in the vicinity of a plurality of intersections between the plurality of word lines 50 and the plurality of bit lines 51. The plurality of storage structures 53 are arranged in the vicinity of the plurality of readout structures 52. The plurality of selection transistors 54 are arranged corresponding to the plurality of readout structures 52. One terminal of the read structure 52 is connected to the bit line 51, and the other terminal is connected to the drain of the selection transistor 54. The source of the selection transistor 54 is grounded. The gate of the selection transistor 54 is connected to the corresponding word line 50. The word line control circuit 61 is connected to one end of a plurality of word lines 50 and controls selection of each word line 50 and application of current / voltage. The bit line control circuit 62 is connected to one end of the plurality of bit lines 51 and controls selection of each bit line 51 and application of current / voltage. The memory cell 60 includes the read structure 52, the storage structure 53, and the selection transistor 54 described above. The memory array unit 63 has a plurality of memory cells 60 arranged on the array. The magnetoresistive storage device further includes an electromagnet (not shown: corresponding to the magnetization direction setting means 12) that applies a magnetic field to the entire memory array section 63, and a laser irradiation device (which irradiates a desired storage structure 53 with a laser). (Not shown: corresponding to the temperature raising means 11).

Next, the configuration of the storage structure 53 and the read structure 52 will be described with reference to FIG. An SiO ₂ interlayer insulating film 71 having a thickness of 100 nm is provided on a semiconductor substrate (not shown) on which transistors including the selection transistor 54, wirings, and the like are formed. In the SiO ₂ interlayer insulating film 71, a tungsten plug 70 having a thickness of 100 nm connected to the lower layer wiring is provided. A Ta film 72 having a thickness of 10 nm is provided on the SiO ₂ interlayer insulating film 71 so as to be connected to the tungsten plug 70. On the Ta film 72, an antiferromagnetic PtMn film 73 having a thickness of 20 nm, a lower pinned layer CoFe film 74 having a thickness of 3 nm, a nonmagnetic layer Ru film 75 having a thickness of 3 nm, and an upper pinned layer CoFe film having a thickness of 3 nm. 76, a tunnel insulating layer MgO film 77 having a thickness of 1 nm, a free CoFeB film 78 having a thickness of 2 nm, and a Ta film 79 having a thickness of 50 nm are stacked in this order. The free layer CoFeB film 78 and the Ta film 79 are protected by a SiN film 80 having a thickness of 2 nm. The shape of the readout structure 52 composed of the CoFe film 74, the Ru film 75, the CoFe film 76, the MgO film 77, and the CoFeB film 78 is a circle having a diameter of 1 μm, as shown in FIG. A 400-nm-thick SiO ₂ interlayer insulating film 81 is provided so as to cover the readout structure 52. In the SiO ₂ interlayer insulating film 81, a Cu plug 82 having a thickness of 300 nm connected to the upper portion of the Ta film 79 is provided. An AlCu film 83 having a thickness of 200 nm is provided on the SiO ₂ interlayer insulating film 81 so as to be connected to the Cu plug 82. A 300 nm thick SiO ₂ interlayer insulating film 84 is provided so as to cover the AlCu film 83. Subsequently, a 10 nm thick Ta film 85, a 20 nm thick antiferromagnetic PtMn film 86, a 6 nm thick magnetic CoPt film 87, and a 50 nm thick Ta film 88 are formed on the SiO ₂ interlayer insulating film 84. They are stacked in this order. The shape of the memory structure 53 composed of the PtMn film 86 and the CoPt film 87 is a circle having a diameter of 3 μm, as shown in FIG. The CoPt film 87 and the PtMn film 86 are firmly exchange coupled. The direction in which magnetization is easy is the in-plane direction of the CoFe film 74 and the direction perpendicular to the film surface of the CoPt film 87.

Next, the data write operation will be described with reference to FIG. 4 and FIG. First, the prepared laser irradiation apparatus irradiates the storage structure 53 of the memory cell 60 to be written with a laser based on the word address and bit address to be written, and raises the temperature to a desired temperature (eg, 200 ° C.). Warm up. Further, the prepared electromagnet applies a magnetic field in a desired direction (a direction corresponding to data to be written) in the vertical direction to the entire substrate. Thereby, the magnetization direction of the CoPt film 87 is directed along the applied magnetic field having a direction corresponding to the data to be written. At this time, the PtMn film 86 of the memory structure 53 is at a temperature at which the magnetization state changes according to the magnetization direction of the CoPt film 87. Therefore, the magnetization direction of the PtMn film 86 is oriented in the direction along the applied magnetic field having a direction corresponding to the data to be written. Next, when the laser irradiation apparatus stops the laser irradiation and the temperature of the memory structure 53 is lowered, the PtMn film 86 is in a magnetization state that supports the magnetization direction of the CoPt film 87. For this reason, the magnetization direction of the CoPt film 87 remains fixed even after the electromagnet stops applying the magnetic field. In this way, data can be written by setting the magnetization direction of the CoPt film 87 of the memory structure 53 to a desired direction (direction corresponding to data to be written). At this time, due to magnetostatic coupling between the CoPt film 87 and the CoFeB film 78, the magnetization direction of the CoFeB film 78 is also directed to the direction corresponding to the data to be written.

Next, the data read operation will be described with reference to FIGS. First, the word line control circuit 61 selects the word line 50 of the word address to be read and applies a predetermined voltage. Thereby, the corresponding selection transistor 54 is turned on. Then, the bit line control circuit 62 selects the bit line 51 of the bit address to be read and applies a read current of 20 μA. The CoFeB film 78 of the read structure 52 is set to either the right direction or the left direction by magnetostatic coupling with the CoPt film 87 of the memory structure 53. When the resistance values at this time are 10 kΩ and 20 kΩ, respectively, and the on-resistance of each transistor is 1 kΩ, the potential of the bit line 51 is 0.21 V and 0.41 V, respectively. Therefore, by writing the potential of the bit line 51 to, for example, a differential sense amplifier, written data can be determined.

Next, a method for manufacturing the memory structure 53 and the read structure 52 will be described with reference to FIG. A SiO ₂ interlayer insulating film 71 provided with a tungsten plug 70 connected to a lower layer wiring is formed to 100 nm on a semiconductor substrate (not shown) on which a transistor including the selection transistor 54, wiring, and the like are formed. Next, on the SiO ₂ interlayer insulating film 71, the Ta film 72 is 10 nm, the antiferromagnetic PtMn film 73 is 20 nm, the lower pinned layer CoFe film 74 is 3 nm, the nonmagnetic layer Ru film 75 is 3 nm, and the upper pinned layer. The CoFe film 76 is formed by stacking 3 nm, the tunnel insulating layer MgO film 77 by 1 nm, the free layer CoFeB film 78 by 2 nm, and the Ta film 79 by 50 nm in this order by sputtering. Thereafter, annealing is performed in a magnetic field of about 1 T at 275 ° C. for 2 hours, and the magnetization direction of the pinned layer (the lower pinned layer CoFe film 74 and the upper pinned layer CoFe film 76) is set. Subsequently, the Ta film 79 is processed into a readout structure shape by a photolithography technique and a reactive ion etching technique (hereinafter referred to as RIE). Then, after removing the resist by ashing, the CoFeB film 78 is processed into a readout structure by a milling method using the Ta film 79 as a mask. Next, an SiN film 80 is formed to have a thickness of 30 nm by the CVD method so as to cover the entire surface of the substrate, and the upper side wall of the readout structure 52 is protected. Subsequently, the MgO film 77 to the Ta film 72 are processed by a photolithography technique and a milling method. The shape of the free layer (CoFeB film 78) of this example is a circle having a diameter of 1 μm as shown in FIG. Subsequently, an SiO ₂ interlayer insulating film 81 is formed by a 500 nm CVD method so as to cover the entire surface of the substrate, and then planarized by a chemical mechanical polishing technique (hereinafter referred to as CMP). The SiO ₂ interlayer insulating film 81 on the Ta film 79 is removed by RIE to form vias, and Cu is embedded to form Cu plugs 82. Thereafter, an AlCu film 83 is formed on the entire surface by sputtering, and processed by using the RIE technique to form a wiring (bit line 51). Further, an SiO ₂ interlayer insulating film 84 is formed to a thickness of 400 nm so as to cover the entire surface of the substrate, and is planarized by CMP. Thereafter, the Ta film 85, 10 nm of the antiferromagnetic PtMn film 86, 20 nm of the

magnetic CoPt film

87, and 6 nm of the Ta film 88 are stacked in this order by sputtering. Then, patterning is performed by a photolithography technique and a milling method to form the memory structure 53. As shown in FIG. 6, the memory structure 53 is circular with a diameter of 3 μm. Thereafter, annealing is performed in a magnetic field of about 1 T at 275 ° C. for 2 hours to strengthen the exchange coupling between the CoPt film 87 and the PtMn film 86. At this time, since the CoFe film 74 is in the film surface (xy plane) inward direction and the CoPt film 87 is in the direction perpendicular to the film surface (z direction), the magnetization direction is 45 degrees with respect to the film surface (xy plane). Apply a magnetic field in the tilted direction.

In this embodiment, the distance between the antiferromagnetic material and the tunnel insulating film that requires a temperature increase in the write operation is several nanometers compared to the conventional distance (FIGS. 2A and 2B), which is several nanometers. Can do. In addition, since there is an interlayer insulating film of several hundreds of nanometers between the antiferromagnetic material and the tunnel insulating film, heat conduction is hindered, and it is possible to suppress a temperature rise compared to the conventional (FIGS. 2A and 2B). Become. This improves the reliability of the tunnel insulating film. This magnetic storage device is suitable for storing a capacity of about several tens of bits because of its large size, and has prepared a recording of parameters obtained by evaluating the device itself in a substrate state and a circuit for multiple use. The adopted circuit information can be used to store instead of the fuse.

A structure in which a plurality of nonmagnetic materials that magnetically couple magnetic materials or magnetic materials to each other may be used as a free layer or a pinned layer in the magnetoresistive memory element.

(Second embodiment)
Next, a second example according to the embodiment of the present invention will be described. FIG. 7 is a circuit diagram showing a configuration of a memory array portion of a magnetoresistive memory device as a second example according to the embodiment of the present invention. FIG. 8 is a cross-sectional view showing a configuration of a main part of a magnetoresistive memory device as a second example according to the embodiment of the present invention. FIG. 9 is a top view showing a configuration of a main part of a magnetoresistive memory device as a second example according to the embodiment of the present invention.

Referring to FIG. 7, the memory array unit 63 of the magnetoresistive storage device includes a plurality of word lines 50, a plurality of bit lines 51, a plurality of read structures 52, a plurality of storage structures 53, and a plurality of memory structures 53. A selection transistor 54, a plurality of resistors 55, a plurality of write selection transistors 56, a plurality of write word lines 57, a word line control circuit 61, and a bit line control circuit 62 are provided. The plurality of word lines 50 extend in one direction (X direction). The plurality of bit lines 51 extend in one direction (Y direction). The plurality of read structures 53 are arranged in an array in the vicinity of a plurality of intersections between the plurality of word lines 50 and the plurality of bit lines 51. The plurality of storage structures 53 are arranged in the vicinity of the plurality of readout structures 52. The plurality of resistors 55 are arranged below the corresponding memory structures 53. The plurality of selection transistors 54 are arranged corresponding to the plurality of readout structures 52. The plurality of selection transistors 56 are arranged corresponding to the plurality of resistors 55. The plurality of write word lines 57 extend in one direction (X direction). One terminal of the read structure 52 is connected to the bit line 51, and the other terminal is connected to the drain of the selection transistor 54. The source of the selection transistor 54 is grounded. The gate of the selection transistor 54 is connected to the corresponding word line 50. One terminal of the resistor 55 is connected to the bit line 51 and the other terminal is connected to the drain of the write selection transistor 56. The source of the write selection transistor 56 is grounded. The gate of the write selection transistor 56 is connected to the corresponding write word line 57. The word line control circuit 61 is connected to one end of a plurality of word lines 50 and controls selection of each word line 50 and application of current / voltage. Further, one end of a plurality of write word lines 57 is connected to control selection of each write word line 57 and application of current / voltage. The bit line control circuit 62 is connected to one end of the plurality of bit lines 51 and controls selection of each bit line 51 and application of current / voltage. The memory cell 60 includes the read structure 52, the memory structure 53, the selection transistor 54, the write selection transistor 56, and the resistor 55. The memory array unit 63 has a plurality of memory cells 60 arranged on the array. In this embodiment, the resistor 55 functions as the temperature raising means 11 and the bit line 51 functions as the magnetization direction setting means 12. However, the resistor 55 may also have a function as the magnetization direction setting means 12.

Next, the configuration of the storage structure 53 and the read structure 52 will be described with reference to FIG. A resistor 55 having a thickness of 10 nm is provided over a transistor including the selection transistor 54 and a semiconductor substrate (not shown) on which wirings and the like are formed. A 100 nm thick SiO ₂ interlayer insulating film 71 is provided so as to cover the entire substrate including the resistor 55. In the SiO ₂ interlayer insulating film 71, a tungsten plug 70 having a thickness of 100 nm connected to the lower layer wiring is provided. A Ta film 72 having a thickness of 10 nm is provided on the SiO ₂ interlayer insulating film 71 so as to be connected to the tungsten plug 70. Further, another Ta film 72 a having the same thickness of 10 nm is provided in the vicinity of the Ta film 72. On the Ta film 72, an antiferromagnetic PtMn film 73 having a thickness of 20 nm, a lower pinned layer CoFe film 74 having a thickness of 3 nm, a nonmagnetic layer Ru film 75 having a thickness of 3 nm, and an upper pinned layer CoFe film having a thickness of 3 nm. 76, a tunnel insulating layer MgO film 77 having a thickness of 1 nm, a free CoFeB film 78 having a thickness of 2 nm, and a Ta film 79 having a thickness of 50 nm are stacked in this order. Adjacently, an antiferromagnetic PtMn film 73a having a thickness of 20 nm, a magnetic CoFe film 74a having a thickness of 3 nm, and a nonmagnetic layer Ru film 75a having a thickness of 3 nm are stacked in this order on the Ta film 72a. ing. The free layer CoFeB film 78 and the Ta film 79 are protected by a SiN film 80 having a thickness of 2 nm. The shape of the readout structure 52 composed of the CoFe film 74, the Ru film 75, the CoFe film 76, the MgO film 77, and the CoFeB film 78 is a circle having a diameter of 0.2 μm, as shown in FIG. Similarly, the shape of the memory structure 53 composed of the PtMn film 73a and the CoFe film 74a is a circle having a diameter of 0.2 μm, as shown in FIG. A 40 nm-thickness SiO ₂ interlayer insulating film 81 is provided so as to cover the readout structure 52 and the memory structure 53. In the SiO ₂ interlayer insulating film 81, a Cu plug 82 having a thickness of 300 nm connected to the upper portion of the Ta film 79 is provided. An AlCu film 83 having a thickness of 200 nm is provided on the SiO ₂ interlayer insulating film 81 so as to be connected to the Cu plug 82. The CoFe film 74a and the PtMn film 73a are strongly exchange coupled. The direction in which magnetization is easy is the in-film direction of the CoFe film 74 and the in-film direction of the CoFe film 74a.

Next, the data write operation will be described with reference to FIG. 7 and FIG. First, the word line control circuit 62 selects a write word line 57 of a word address to be written and applies a predetermined voltage. Accordingly, the corresponding write selection transistor 56 is turned on. On the other hand, the bit line control circuit 61 selects a bit line 51 of a bit address to be written and applies a predetermined voltage. As a result, the corresponding resistor 55 generates heat when a current flows through it. Due to the heat generation, the CoFe film 74a of the corresponding memory structure 53 is heated to a desired temperature (eg, 280 ° C.). Here, depending on the direction of the current flowing through the bit line 51, a magnetic field in one of the two magnetic fields (direction corresponding to the data to be written) is generated. Thereby, the magnetization direction of the CoFe film 74a is directed in a direction along the magnetic field having a direction corresponding to the data to be written. At this time, the PtMn film 73a of the memory structure 53 is at a temperature at which the magnetization state changes according to the magnetization direction of the CoFe film 74a. Therefore, the PtMn film 73a faces in the direction along the applied magnetic field having a direction corresponding to the data to be written. Next, when the write selection transistor 56 is turned off, the PtMn film 73a enters a magnetization state that supports the magnetization direction of the CoFe film 74a. For this reason, even if the bit line potential is lowered, the magnetization direction of the CoFe film 74a remains fixed even after the magnetic field is stopped. In this way, data can be written by setting the magnetization direction of the CoFe film 74a of the memory structure 53 to a desired direction (direction corresponding to data to be written). At this time, due to the magnetostatic coupling between the CoFe film 74a and the CoFeB film 78, the magnetization direction of the CoFeB film 78 is also directed to the direction corresponding to the data to be written.

Next, regarding the data read operation, the data read operation according to the present embodiment is the same as that of the first embodiment, and a description thereof will be omitted.

Next, a method for manufacturing the memory structure 53 and the read structure 52 will be described with reference to FIG. SiO ₂ interlayer insulating film in which a tungsten plug 70 connected to a lower layer wiring is provided on a semiconductor substrate (not shown) on which a transistor 55 including a selection transistor 54 and a write selection transistor 56, a wiring, etc., and a resistor 55 are formed. 71 is formed to 100 nm. Next, on the SiO ₂ interlayer insulating film 71, the Ta film 72 is 10 nm, the antiferromagnetic PtMn film 73 is 20 nm, the lower pinned layer CoFe film 74 is 3 nm, the nonmagnetic layer Ru film 75 is 3 nm, and the upper pinned layer. The CoFe film 76 is formed by stacking 3 nm, the tunnel insulating layer MgO film 77 by 1 nm, the free layer CoFeB film 78 by 2 nm, and the Ta film 79 by 50 nm in this order by sputtering. Thereafter, annealing is performed in a magnetic field of about 1 T at 275 ° C. for 2 hours, and the magnetization direction of the pinned layer (the lower pinned layer CoFe film 74 and the upper pinned layer CoFe film 76) is set. Subsequently, the Ta film 79 is processed into a readout structure shape by photolithography and RIE. Then, after removing the resist by ashing, the CoFeB film 78 is processed into a readout structure by a milling method using the Ta film 79 as a mask. Next, an SiN film 80 is formed to have a thickness of 30 nm by the CVD method so as to cover the entire surface of the substrate, and the upper side wall of the readout structure 52 is protected. Subsequently, the MgO film 77 and the upper pinned CoFe film 76 are processed by a photolithography technique and a milling method. Further, the read structure 52 is processed from the Ru film 75 to the Ta film 72 using the Ta film 79 as a mask. At the same time, the Ru structure 75 to the Ta film 72 are processed for the memory structure 53 using the resist as a mask. For the memory structure 53, a subscript “a” is added for distinction to form a Ru film 75a, a CoFe film 74a, a PtMn film 73a, and a Ta film 72a. As a result, the read structure 52 and the storage structure 53 can be formed. As shown in FIG. 9, in this embodiment, both the readout structure 52 and the storage structure 53 are circular with a diameter of 0.2 μm. Thereafter, an SiO ₂ interlayer insulating film 81 is formed by a 500 nm CVD method so as to cover the entire surface of the substrate, and then planarized by a chemical mechanical polishing technique (hereinafter referred to as CMP). The SiO ₂ interlayer insulating film 81 on the Ta film 79 is removed by RIE to form vias, and Cu is embedded to form Cu plugs 82. Thereafter, an AlCu film 83 is formed on the entire surface by sputtering, and processed by using the RIE technique to form a wiring (bit line 51).

In this embodiment, the storage structure 53 and the readout structure 52 are formed simultaneously. This facilitates the manufacturing process. In addition, in this embodiment, the resistor 55 has the function of the temperature raising means 11, and the bit line 51 has the function of the magnetization direction setting means 12, both of which are built in the memory array unit 63. The element configuration of the magnetoresistive memory device can be simplified and miniaturization is facilitated. Furthermore, since this magnetoresistive memory device incorporates the temperature raising means (resistor 55), it can be rewritten on the user side. Further, it can be used to store block selection data of the redundancy memory block by inspection at the time of shipment.

In FIG. 7, the magnetic field applied to the memory structure 53 is a magnetic field generated by the wiring current of the bit line 51. Therefore, the direction of the magnetic field is two directions. However, as an application of the present embodiment, by preparing a separate wiring orthogonal to the bit line 51 and flowing a current, a combined magnetic field of the magnetic field due to the separate wiring current and the magnetic field due to the wiring current of the bit line 51 may be obtained. Is possible. In that case, a magnetic field in any direction can be formed by independently controlling the magnitude of the current flowing through both wirings. Thereby, the magnetization direction of the memory structure 53 having no anisotropy can be set to an arbitrary direction. In this case, multi-value and analog data can be recorded corresponding to the direction.

(Third embodiment)
Next, a third example according to the embodiment of the present invention will be described. FIG. 10 is a circuit diagram showing a configuration of a memory array section of a magnetoresistive storage device as a third example according to the embodiment of the present invention. 11A and 11B are cross-sectional views showing the configuration of the main part of a magnetoresistive memory device as a third example according to the embodiment of the present invention. However, FIG. 11A shows a low resistance state, and FIG. 11B shows a high resistance state. FIG. 12 is a top view showing a configuration of a main part of a magnetoresistive memory device as a third example according to the embodiment of the present invention.

Referring to FIG. 10, the memory array unit 63 of the magnetoresistive storage device includes a plurality of word lines 50, a plurality of bit lines 51, a plurality of read structures 52, a plurality of storage structures 53, and a plurality of memory structures 53. A selection transistor 54, a plurality of write selection transistors 56, a plurality of write word lines 57, a word line control circuit 61, and a bit line control circuit 62 are provided. The plurality of word lines 50 extend in one direction (X direction). The plurality of bit lines 51 extend in one direction (Y direction). The plurality of storage structures 53 are arranged in an array. Each of the plurality of storage structures 53 is arranged in contact with the lower side of the corresponding bit line 51. The plurality of readout structures 52 are arranged in an array. Each of the plurality of read structures 52 is disposed in contact with the opposite side of the corresponding bit line 51 from the memory structure 53. The plurality of selection transistors 54 are arranged corresponding to the plurality of readout structures 52. The plurality of selection transistors 56 are arranged corresponding to the plurality of storage structures 53. The plurality of write word lines 57 extend in one direction (X direction). One terminal of the read structure 52 is connected to the bit line 51, and the other terminal is connected to the drain of the selection transistor 54. The source of the selection transistor 54 is grounded. The gate of the selection transistor 54 is connected to the corresponding word line 50. One terminal of the memory structure 53 is connected to the bit line 51, and a terminal provided on the surface opposite to the bit line 51 is connected to the drain of the write selection transistor 56. The source of the write selection transistor 56 is grounded. The gate of the write selection transistor 56 is connected to the corresponding write word line 57. The word line control circuit 61 is connected to one end of a plurality of word lines 50 and controls selection of each word line 50 and application of current / voltage. Further, one end of a plurality of write word lines 57 is connected to control selection of each write word line 57 and application of current / voltage. The bit line control circuit 62 is connected to one end of the plurality of bit lines 51 and controls selection of each bit line 51 and application of current / voltage. The memory cell 60 includes the read structure 52, the storage structure 53, the selection transistor 54, and the write selection transistor 56 described above. The memory array unit 63 has a plurality of memory cells 60 arranged on the array. In this embodiment, the storage structure 53 functions as the temperature raising means 11, and the bit line 51 functions as the magnetization direction setting means 12.

Next, with reference to FIGS. 11A and 11B, configurations of the storage structure 53 and the read structure 52 will be described. An SiO ₂ interlayer insulating film 71 having a thickness of 100 nm is provided on a semiconductor substrate (not shown) on which a transistor including the selection transistor 54 and the write selection transistor 56, wiring, and the like are formed. In the SiO ₂ interlayer insulating film 71, a tungsten plug 70 having a thickness of 100 nm connected to the lower layer wiring is provided. A Ta film 85 having a thickness of 20 nm is provided on the SiO ₂ interlayer insulating film 71 so as to be connected to the tungsten plug 70. On the Ta film 85, an antiferromagnetic PtMn film 86 having a thickness of 20 nm, a magnetic CoFe film 87 having a thickness of 3 nm, and a Ta film 88 having a thickness of 50 nm are stacked in this order. As shown in FIG. 12, the memory structure 53 including the PtMn film 86 and the CoFe film 87 has a circular shape with a diameter of 0.2 μm. On the Ta film 88, a Cu film 93 as the bit line 51 is provided. On the Cu film 93, a Ta film 79 having a thickness of 10 nm, a free NiFe film 78 having a thickness of 2 nm, a tunnel insulating layer MgO film 77 having a thickness of 1 nm, a pinned CoFe film 76 having a thickness of 3 nm, and a 1 nm thickness. A Ru film 75, a pinned CoFe film 74 having a thickness of 3 nm, an antiferromagnetic PtMn film 73 having a thickness of 20 nm, and a Ta film 72 having a thickness of 50 nm are stacked in this order. As shown in FIG. 12, the readout structure 52 composed of the CoFe film 74, the Ru film 75, the CoFe film 76, the MgO film 77, and the CoFeB film 78 has a circular shape with a diameter of 0.2 μm. The CoPt film 87 and the PtMn film 86 are firmly exchange coupled.

FIG. 11A shows a low resistance state (resistance value: R) where the magnetization direction of the pinned CoFe film 76 and the magnetization direction of the free NiFe film 78 are “parallel”. Can be associated. On the other hand, FIG. 11B shows a high resistance state (resistance value: R + ΔR) in which the magnetization direction of the pinned CoFe film 76 and the magnetization direction of the free NiFe film 78 are “anti-parallel”. For example, data “1” Can be associated.

Next, the data write operation will be described with reference to FIGS. 10, 11A, and 11B. First, the word line control circuit 62 selects a write word line 57 of a word address to be written and applies a predetermined voltage. Accordingly, the corresponding write selection transistor 56 is turned on. On the other hand, the bit line control circuit 61 selects a bit line 51 of a bit address to be written and applies a predetermined voltage. As a result, the corresponding memory structure 53 generates heat when a current flows therethrough. Due to the heat generation, the antiferromagnetic CoFe film 87 of the memory structure 53 is heated to a desired temperature (eg, 290 ° C.). Here, depending on the direction of the current flowing through the bit line 51, a magnetic field in one of the two magnetic fields (direction corresponding to the data to be written) is generated. Thereby, the magnetization direction of the CoFe film 87 is directed along the magnetic field having a direction corresponding to the data to be written. At this time, the PtMn film 86 of the memory structure 53 is at a temperature at which the magnetization state changes according to the magnetization direction of the CoFe film 74. Therefore, the PtMn film 86 is oriented in a direction along the applied magnetic field having a direction corresponding to the data to be written. Next, when the write selection transistor 56 is turned off, the PtMn film 86 enters a magnetization state that supports the magnetization direction of the CoFe film 87. For this reason, even if the bit line potential is lowered, the magnetization direction of the CoFe film 87 remains fixed even after the magnetic field is stopped. In this way, data can be written by setting the magnetization direction of the CoFe film 87 of the memory structure 53 to a desired direction (direction corresponding to the data to be written). At this time, due to magnetostatic coupling between the CoFe film 87 and the CoFeB film 78, the magnetization direction of the CoFeB film 78 is also directed to the direction corresponding to the data to be written.

Next, with reference to FIGS. 11A and 11B, a method for manufacturing the memory structure 53 and the read structure 52 will be described. An SiO ₂ interlayer insulating film 71 provided with a tungsten plug 70 connected to a lower layer wiring is formed to 100 nm on a semiconductor substrate (not shown) on which transistors including the selection transistor 54 and the write selection transistor 56, wirings, and the like are formed. . Next, on the SiO ₂ interlayer insulating film 71, the Ta film 85 is laminated by 20 nm, the antiferromagnetic PtMn film 86 is 20 nm, the magnetic CoFe film 87 is 3 nm, the Ta film 88 is laminated by 50 nm in this order. Form a film. Next, the Ta film 88 is processed into a memory structure shape by photolithography and RIE. Then, after removing the resist by ashing, the Ta film 85 is processed from the CoFe film 87 by the milling method using the Ta film 88 as a mask. Thereby, the memory structure 53 is formed. Next, an SiO ₂ interlayer insulating film (not shown) is formed by a 50 nm CVD method so as to cover the entire surface of the substrate, and then planarized by CMP to expose the surface of the Ta film 88. Subsequently, a SiN film (not shown) is formed with a thickness of 20 nm, and a SiO ₂ interlayer insulating film (not shown) is formed with a thickness of 400 nm. Then, a bit line groove is opened there, and a Cu film 93 (bit line 51) is embedded. Thereafter, the Ta film 79 is 10 nm, the free layer NiFe film 78 is 2 nm, the tunnel insulating layer MgO film 77 is 1 nm, the pinned layer CoFe film 76 is 3 nm, the Ru layer 75 is 1 nm, and the pinned layer CoFe film 74 so as to cover the entire surface of the substrate. 3 nm, the antiferromagnetic PtMn film 73 is 20 nm, and the Ta film 72 is 50 nm, which are stacked in this order by sputtering. Thereafter, annealing is performed in a magnetic field of about 1 T at 275 ° C. for 2 hours to set the magnetization direction of the pinned layer (CoFe film 74, CoFe film 76). Subsequently, the Ta film 72 is processed into a readout structure shape by photolithography and RIE. After removing the resist by ashing, the Ta film 79 is processed from the PtMn film 73 by the milling method using the Ta film 72 as a mask. Thereby, the readout structure 52 can be formed. The free layer shape of the present example is a circle having a diameter of 0.2 μm. Since the subsequent processes are the same as those in the second embodiment, the description thereof is omitted.

In this embodiment, since the antiferromagnetic material itself (memory structure 53 itself) is heated, the resistor 55 used in the second embodiment is not necessary. In addition, the memory structure 53 and the read structure 53 can share the wiring (bit line 51). As a result, the element configuration of the magnetoresistive memory device can be simplified and miniaturization is facilitated.

(Fourth embodiment)
Next, a fourth example according to the embodiment of the present invention will be described. FIG. 13 is a circuit diagram showing a configuration of a memory array portion of a magnetoresistive memory device as a fourth example according to the embodiment of the present invention. 14A and 14B are cross-sectional views showing the configuration of the main part of a magnetoresistive memory device as a fourth example according to the embodiment of the present invention. However, FIG. 14A shows a low resistance state, and FIG. 14B shows a high resistance state.

Referring to FIG. 13, the memory array unit 63 of the magnetoresistive memory device includes a plurality of word lines 50, a plurality of bit lines 51, a plurality of read structures 52, a plurality of memory structures 53, and a plurality of memory structures 53. A selection transistor 54, a plurality of write selection transistors 56, a plurality of write word lines 57, a plurality of write bit lines 94, a word line control circuit 61, and a bit line control circuit 62 are provided. The plurality of word lines 50 extend in one direction (X direction). The plurality of bit lines 51 extend in one direction (Y direction). The plurality of readout structures 52 are arranged in an array. Each of the plurality of read structures 52 is disposed on the corresponding bit line 51. The plurality of storage structures 53 are arranged in an array. Each of the plurality of storage structures 53 is arranged in contact with the lower side of the corresponding write bit line 94. The plurality of selection transistors 54 are arranged corresponding to the plurality of readout structures 52. The plurality of selection transistors 56 are arranged corresponding to the plurality of storage structures 53. The plurality of write word lines 57 extend in one direction (X direction). The plurality of write bit lines 94 extend in one direction (Y direction). One terminal of the read structure 52 is connected to the bit line 51, and the other terminal is connected to the drain of the selection transistor 54. The source of the selection transistor 54 is grounded. The gate of the selection transistor 54 is connected to the corresponding word line 50. One terminal of the memory structure 53 is connected to the write bit line 94, and a terminal provided on the surface opposite to the write bit line 94 is connected to the drain of the write selection transistor 56. The source of the write selection transistor 56 is grounded. The gate of the write selection transistor 56 is connected to the corresponding write word line 57. The word line control circuit 61 is connected to one end of a plurality of word lines 50 and controls selection of each word line 50 and application of current / voltage. Further, one end of a plurality of write word lines 57 is connected to control selection of each write word line 57 and application of current / voltage. The bit line control circuit 62 is connected to one end of the plurality of bit lines 51 and controls selection of each bit line 51 and application of current / voltage. Further, one end of a plurality of write bit lines 94 is connected to control selection of each write bit line 94 and application of current / voltage. The memory cell 60 includes the read structure 52, the storage structure 53, the selection transistor 54, and the write selection transistor 56 described above. The memory array unit 63 has a plurality of memory cells 60 arranged on the array. In this embodiment, the storage structure 53 functions as the temperature raising means 11, and the write bit line 94 functions as the magnetization direction setting means 12.

Next, with reference to FIGS. 14A and 14B, configurations of the storage structure 53 and the read structure 52 will be described. A SiO ₂ interlayer insulating film 71 having a thickness of 100 nm is provided on a semiconductor substrate (not shown) on which a transistor including a write selection transistor, wiring, and the like are formed. In the SiO ₂ interlayer insulating film 71, a tungsten plug 70 having a thickness of 100 nm connected to the lower layer wiring is provided. A Ta film 85 having a thickness of 20 nm is provided on the SiO ₂ interlayer insulating film 71 so as to be connected to the tungsten plug 70. On the Ta film 85, an antiferromagnetic PtMn film 86 having a thickness of 20 nm, a magnetic CoFe film 87 having a thickness of 3 nm, and a Ta film 88 having a thickness of 50 nm are stacked in this order. The memory structure 53 constituted by the PtMn film 86 and the CoFe film 87 is, for example, a circle having a diameter of 0.2 μm. On the Ta film 87, an AlCu film 83 as a write bit line 94 is provided. On the AlCu film 83 (write bit line 94), another AlCu film 83 as the bit line 51 is provided via the SiO ₂ interlayer insulating film 84. On the AlCu film 83, a 10 nm thick Ta film 79, a 2 nm thick free layer NiFe film 78, a 1 nm thick tunnel insulating layer MgO film 77, a 3 nm thick pinned layer CoFe film 76, a 1 nm thick film. A Ru film 75, a pinned CoFe film 74 having a thickness of 3 nm, an antiferromagnetic PtMn film 73 having a thickness of 20 nm, and a Ta film 72 having a thickness of 50 nm are stacked in this order. The shape of the readout structure 52 including the CoFe film 74, the Ru film 75, the CoFe film 76, the MgO film 77, and the CoFeB film 78 is, for example, a circle having a diameter of 0.2 μm. On the Ta film 72, another tungsten plug 70 (100 nm thick) embedded in another SiO ₂ interlayer insulating film 71 (100 nm thick) is provided. On the SiO ₂ interlayer insulating film 71, a transistor including the selection transistor 54, a semiconductor substrate (not shown) on which wiring and the like are formed is provided in the reverse direction (direction in which the mounting surface of the electronic element is directed in the −Z direction). It has been.

FIG. 14A shows a low resistance state (resistance value: R) in which the magnetization direction of the pinned CoFe film 76 and the magnetization direction of the free layer NiFe film 78 are “parallel”. Can be associated. On the other hand, FIG. 14B shows a high resistance state (resistance value: R + ΔR) in which the magnetization direction of the pinned layer CoFe film 76 and the magnetization direction of the free layer NiFe film 78 are “antiparallel”. For example, data “1” Can be associated.

Next, regarding the data write operation and read operation, the data write operation and read operation according to the present embodiment are the same as those of the third embodiment, and the description thereof will be omitted.

Next, with reference to FIGS. 14A and 14B, a method for manufacturing the memory structure 53 and the readout structure 52 will be described. An SiO ₂ interlayer insulating film 71 provided with a tungsten plug 70 connected to a lower layer wiring is formed to 100 nm on a semiconductor substrate (not shown) on which a transistor including the write selection transistor 56, wiring, and the like are formed. Next, on the SiO ₂ interlayer insulating film 71, the Ta film 85 is laminated by 20 nm, the antiferromagnetic PtMn film 86 is 20 nm, the magnetic CoFe film 87 is 3 nm, the Ta film 88 is laminated by 50 nm in this order. Form a film. Next, the Ta film 88 is processed into a memory structure shape by photolithography and RIE. Then, after removing the resist by ashing, the Ta film 85 is processed from the CoFe film 87 by the milling method using the Ta film 88 as a mask. Thereby, the memory structure 53 is formed. Next, an SiO ₂ interlayer insulating film 95 is formed by a 50 nm CVD method so as to cover the entire surface of the substrate, and then flattened by CMP to expose the surface of the Ta film 88. Next, an AlCu film 83 is formed and processed to form a wiring (write bit line 94).
On the other hand, an SiO ₂ interlayer insulating film 71 having a tungsten plug 70 connected to the lower layer wiring is formed to a thickness of 100 nm on a new semiconductor substrate (not shown) on which a transistor including the selection transistor 54, wiring, and the like are formed. Next, on the SiO ₂ interlayer insulating film 71, the Ta film 72 is 20 nm, the antiferromagnetic PtMn film 73 is 20 nm, the pinned layer CoFe film 74 is 3 nm, the Ru film 75 is 1 nm, the pinned layer CoFe film 76 is 3 nm, The tunnel insulating layer MgO film 77 is formed by laminating 1 nm, the free layer NiFe film 78 by 2 nm, and the Ta film 79 by 10 nm in this order by sputtering. Thereafter, annealing is performed in a magnetic field of about 1 T at 275 ° C. for 2 hours, and the magnetization direction of the pinned layer (CoFe film 74, CoFe film 76) is set. Subsequently, the Ta film 79 is processed into a readout structure shape by photolithography and RIE. After removing the resist by ashing, the Ta film 72 is processed from the Ta film 79 by the milling method using the Ta film 79 as a mask. Thereby, the readout structure 52 can be formed. Next, an SiO ₂ interlayer insulating film 81 is formed by a 50 nm CVD method so as to cover the entire surface of the substrate, and then flattened by CMP to expose the surface of the Ta film 79. Next, an AlCu film 83 is formed and processed to form a wiring (bit line 51). The free layer shape of the present example is a circle having a diameter of 0.2 μm. In both semiconductor substrates, after selecting a good magnetoresistive memory device, a good chip which is the good magnetoresistive memory device is cut out and pasted together. The alignment between the two may be performed by using an infrared transmission image, or by detecting a position where the output of the readout structure 52 is good and fixing it at that position. Electrical connection is possible by providing bumps on both substrates. If the connection is made at the control portion on the outer periphery of the memory array section 63, the number of terminals can be reduced, and only the power source may be connected.

In this embodiment, the semiconductor substrate on which the memory structure 53 is formed and the semiconductor substrate on which the reading structure 52 is formed are different semiconductor substrates. Therefore, since each semiconductor substrate has few processes, the yield can be improved. Further, since the selected chips are attached after selecting the good chips, an improvement in the non-defective product rate can be expected.

As described above, according to the present invention, the distance between a portion that requires heating (an antiferromagnetic material of the memory structure) and a portion that is important for the reliability of the element (the nonmagnetic material of the readout structure) is increased. It can be expanded from the conventional several nm to about 100 nm or more. Therefore, reliability deterioration due to heating can be suppressed. In addition, since data is stored in the memory structure using exchange coupling between the antiferromagnetic material and the magnetic material, the data is stochastically resistant to thermal disturbance compared to the conventional MTJ in which data is stochastically destroyed by thermal disturbance. Data is hard to be destroyed. In addition, multilevel storage is possible. Further, since the memory element (memory structure) and the reading element (reading structure) are different from each other, the reading element is hardly affected by heat when writing to the memory element, and the reliability can be improved. Thereby, a highly reliable multi-value magnetoresistive memory device can be realized.

Although the present invention has been described above with reference to the embodiment, the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, as long as there is no technical contradiction, all or part of the techniques of the embodiments can be used in combination with each other.

This application is based on Japanese Patent Application No. 2008-209913 filed on Aug. 18, 2008, claiming the benefit of priority from that application, the disclosure of that application should be cited Is incorporated here as it is.

Claims

A first structure in which a first magnetic body whose magnetization direction is fixed, a first non-magnetic body, and a second magnetic body whose magnetization state changes according to data;
A second structure in which an antiferromagnetic material and a third magnetic material are stacked;
A temperature raising means for raising the temperature of the antiferromagnetic material to a desired temperature;
Magnetization direction setting means for directing the magnetization direction of the third magnetic body in a desired direction,
The antiferromagnetic material and the third magnetic material are exchange coupled,
A magnetoresistive storage device in which the second magnetic body and the third magnetic body are magnetically coupled.
The magnetoresistance according to claim 1, wherein the temperature raising means is provided in or near the second structure and generates heat by a current flowing through the second structure to raise the temperature of the antiferromagnetic material to the desired temperature. Storage device.
The temperature raising means is a resistor provided separately from the second structure,
The magnetoresistive storage device according to claim 2, wherein the resistor generates heat by a current flowing through the resistor to raise the temperature of the antiferromagnetic material to the desired temperature.
The temperature raising means is the second structure itself;
The magnetoresistive storage device according to claim 2, wherein the second structure generates heat by a current flowing through the second structure to raise the temperature of the antiferromagnetic material to the desired temperature.
The magnetization direction setting means is a wiring provided in the vicinity of the second structure;
5. The second structure body according to claim 1, wherein the magnetization direction of the third magnetic body is directed to the desired direction by a magnetic field induced by a current flowing in the wiring. 6. Magnetoresistive memory device.
The magnetoresistive storage device according to any one of claims 1 to 4, wherein the magnetization direction setting unit is a magnetic field generator that applies a magnetic field to the third magnetic body.
The easy magnetization direction of the second magnetic material and the easy magnetization direction of the third magnetic material are both in-plane directions, both directions substantially perpendicular to the surface, and one is in-plane direction and the other is in the surface. The magnetoresistive storage device according to claim 1, wherein the magnetoresistive storage device is in a substantially vertical direction.
Both the easy magnetization direction of the second magnetic body and the easy magnetization direction of the third magnetic body are in-plane directions,
The magnetoresistive storage device according to claim 7, wherein both the shape of the second magnetic body and the shape of the third magnetic body are substantially circular.
The magnetoresistive storage device according to claim 1, wherein the temperature raising unit is disposed for each of the second structures.
The magnetoresistive storage device according to any one of claims 1 to 9, wherein the magnetization direction setting means is arranged for each of the second structures.
The magnetoresistive storage device according to any one of claims 1 to 10, wherein the desired temperature is 200 ° C or higher.
The magnetoresistive storage device according to any one of claims 1 to 11, wherein a shortest distance between the antiferromagnetic material and the first nonmagnetic material is 100 nm or more.
Preparing the magnetoresistive storage device according to any one of claims 1 to 12,
Raising the temperature of the antiferromagnetic material to a desired temperature by the temperature raising means, and setting the magnetization direction of the third magnetic material to a direction corresponding to data to be written by the magnetization direction setting means;
A method of writing to a magnetoresistive storage device comprising: stopping the temperature raising means and the magnetization direction setting means to lower the temperature of the antiferromagnetic material and fixing the magnetization direction of the third magnetic material.
The writing method of the magnetoresistive storage device according to claim 13, wherein the timing of stopping the temperature raising means is before the timing of stopping the magnetization direction setting means.