WO2010012167A1 - Procédé et dispositif d'exécution d'instruction - Google Patents

Procédé et dispositif d'exécution d'instruction Download PDF

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Publication number
WO2010012167A1
WO2010012167A1 PCT/CN2009/071558 CN2009071558W WO2010012167A1 WO 2010012167 A1 WO2010012167 A1 WO 2010012167A1 CN 2009071558 W CN2009071558 W CN 2009071558W WO 2010012167 A1 WO2010012167 A1 WO 2010012167A1
Authority
WO
WIPO (PCT)
Prior art keywords
variable
addend
comparison
instruction
value
Prior art date
Application number
PCT/CN2009/071558
Other languages
English (en)
Chinese (zh)
Inventor
高秋明
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2010012167A1 publication Critical patent/WO2010012167A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to an instruction execution method and apparatus. Background technique
  • multi-core processors are booming and more widely used, but the concurrent design of software is relatively lagging behind the development of hardware, which restricts the advantages of multi-core processors.
  • One of the main reasons behind software lag is that multi-core processors have not been able to provide software with a complete set of standard and efficient concurrent instruction sets to support software concurrent processing and design.
  • Embodiments of the present invention provide an instruction execution method and apparatus, which combines a comparison operation and an addition operation into a new atomic comparison plus operation instruction, which enhances the parallel function and improves the execution efficiency.
  • an embodiment of the present invention provides an instruction execution method, including: reading the addend variable according to an address of an addend variable;
  • an embodiment of the present invention further provides an instruction execution apparatus, including:
  • a reading module configured to read the addend variable according to an address of the addend variable
  • a comparison module configured to compare the addend variable read by the read module with a preset value
  • An execution module configured to perform an add operation on the addend variable when the result of the comparison operation of the comparison module is established, and assign a result of the add operation to the addend variable; The addend variable before returning the comparison operation.
  • the technical solution of the embodiment of the present invention has the following advantages, because the embodiment of the present invention combines the comparison operation and the addition operation into a new atomic comparison plus operation instruction, thereby enhancing the parallel function and improving the execution efficiency.
  • FIG. 1 is a flowchart of an instruction execution method according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of a specific implementation manner of an instruction execution method according to an embodiment of the present invention
  • FIG. 5 is a flowchart of another specific implementation manner of an instruction execution method according to an embodiment of the present invention. Execute the device structure diagram. detailed description
  • Embodiments of the present invention combine a comparison operation with an addition operation to form a new single instruction for atomic operations: an atomic comparison plus instruction, and a method and apparatus for performing the instruction.
  • FIG. 1 it is a flowchart of an instruction execution method in the embodiment of the present invention, that is, an execution flowchart of an atomic comparison plus instruction, which includes the following steps:
  • S 1 0 Reads the value of the addend variable from the memory based on the address of the addend variable.
  • the comparison operation is specifically to compare whether the added variable is greater than the preset value, when the value of the added variable is greater than the preset value, the result of the comparison operation is established, when the value of the added variable is not greater than the preset value The result of the comparison operation is not established.
  • the comparison operation is divided into six types, that is, greater than, less than, greater than or equal to, less than or equal to, equal to, and not equal to.
  • the execution instructions proposed by the embodiments of the present invention are also divided into six comparison and addition operations, that is, greater than plus, less than plus, greater than or equal to plus, less than or equal to plus, equal to plus, not equal to plus.
  • addition operations such as signed addition, unsigned addition, 32-bit addition, and 64-bit addition, which are the same as the actual addition instructions in the system. After the addition operation is performed on the value of the addend variable, the result of the addition operation is assigned to the addend variable.
  • step is directly executed, and the value of the addend variable before the comparison operation is returned; if the result of the comparison operation of S102 is not satisfied, the execution is performed directly after the execution of S102 is completed. Step, return the value of the addend variable before the comparison operation.
  • the value of the addend variable before the comparison operation returned by S105 can be further used for the subsequent instruction. It is judged whether the instruction actually performs the addition operation on the addend variable, that is, the execution result of the instruction is verified.
  • the subsequent instruction may be the repeated execution of the atomic comparison plus instruction, so that the value of the addend variable before the comparison operation returned by S105 is needed to determine whether the previous execution of the atomic comparison plus instruction is completed; or other operation instruction , the referenced variable needs to be referenced. Therefore, it is judged whether or not the above-described atomic comparison plus instruction execution is completed by the value of the addend variable before the comparison operation returned by S105.
  • the subsequent instruction determines whether the instruction actually performs an operation on the addend variable, specifically:
  • the value of the added variable before the comparison operation is compared with the preset value for the comparison of the contents of S102.
  • S105 can be executed at any time after the execution of S101 is completed until the end of the instruction, thereby returning the value of the addend variable before the comparison. That is, the value of the addend variable read in S101 is returned. Therefore, the schematic flow diagram shown in FIG. 1 corresponds to only a preferred embodiment of the present invention, and the change in the position of S 105 does not affect the scope of protection of the present invention.
  • the atomic comparison plus instruction in the embodiment of the present invention is a set of instructions, which is a combination of addition and comparison on the mnemonic. As shown in Figure 2, the most typical is greater than plus, and the addition operation is a 32Bit signed plus instruction description. "gt" is an abbreviation for greater than.
  • the comparison operation is divided into six types, that is, greater than, less than, greater than or equal to, less than or equal to, equal to, and not equal to. As shown in FIG. 3, it is a mnemonic abbreviation for six comparisons in the embodiment of the present invention.
  • addition operations such as signed addition, unsigned addition, 32-bit addition, and 64-bit addition, which are the same as the actual addition instructions in the system.
  • Ra, Rb and Rc are three general-purpose 32-bit registers.
  • FIG. 4 it is a flow chart of a specific implementation manner of the instruction execution method in the embodiment of the present invention, and the instruction operation corresponding to the above format is described by using the most common greater than plus, including the following steps:
  • the value of Ra is the address of the addend variable
  • the instruction executing device extracts the value v of the addend variable from the register Ra according to the address.
  • V is a signed 32-bit data that acts as an addend. 5402.
  • the instruction execution device compares the preset values stored in the values V and Rb of the addend variable, that is, whether the comparison V is greater than the data in the Rb.
  • Pre-set signed 32-bit data is stored in Rb, which is used to compare with the added number read in S401.
  • the specific comparison operation may be one of the foregoing six comparison operations.
  • the comparison operation applied in this embodiment is greater than the comparison, that is, whether the value V of the comparison addend variable is greater than the preset value in Rb.
  • the instruction execution device performs an operation on the added value V.
  • the signed 32-bit data subjected to the addition operation by the value V of the addend variable, and the result represents the result data generated after the addition operation is performed on the data values stored in the values V and Rc of the addend variable.
  • the instruction execution device assigns the result of the addition operation to the addend variable.
  • the memory refers specifically to an external storage device, and the instruction execution device can be accessed through an external address or interface, and the register refers to a temporary data storage unit inside the instruction execution device for storing the generated during the operation of the instruction execution device. Temporary data can be automatically or manually emptied after the run ends.
  • the instruction execution device stores the value V of the addend variable before the comparison operation into Ra.
  • the subsequent instructions may take further steps, and the other device further determines whether the value V of the addend variable in the memory performs the actual addition operation. That is, whether the new value writing operation of the memory is actually performed, as shown in FIG. 5, as follows:
  • Ra Read the value in Ra (When the atomic comparison plus instruction is executed, Ra stores the value of the added V before the comparison operation).
  • the comparison operation in this step may be an instruction execution device or other device that needs to know whether the operation is performed, and the change of the main body of the comparison operation does not affect the present.
  • the scope of protection of the invention is not limited to
  • the embodiment of the present invention combines the comparison operation and the addition operation into a new atomic comparison plus operation instruction, thereby enhancing the parallel function and improving the execution efficiency.
  • Write operation may cause write exception * /
  • FIG. 6 it is a structural diagram of an instruction execution apparatus according to an embodiment of the present invention, including: a reading module 610, configured to read a value of an addend variable according to an address of an addend variable.
  • the comparison module 620 is configured to compare the value of the addend variable read by the reading module 610 with a preset value.
  • the comparison operation is divided into six types, that is, greater than, less than, greater than or equal to, less than or equal to, equal to, and not equal to.
  • the execution module 630 is configured to perform an add operation on the value of the addend variable when the comparison module 620 determines that the result of the comparison operation is established, and assign the result of the add operation to the addend variable.
  • addition operations such as signed addition, unsigned addition, 32-bit addition, and 64-bit addition, which are the same as the actual addition instructions in the system.
  • addition operation After performing the addition operation on the value of the addend variable, the result of the addition operation is assigned to the addend variable, and the value of the addend variable is stored to the original address.
  • the execution module 6 30 specifically includes:
  • the execution sub-module 631 is configured to perform an addition operation on the value of the addend variable.
  • the assignment submodule 632 is configured to assign the result of the addition operation performed by the execution submodule 631 to the addend variable.
  • the storage module 640 is configured to store temporary data during execution of the instruction, including one or more of the following values:
  • the value of the addend variable read by the module 61 0 is read, the execution result of the module 630 is executed, and the data value read from each register, such as the preset value read from Rb, Rc in the foregoing embodiment. .
  • the return module 650 is configured to return the value of the addend variable read by the reading module 61 0 for subsequent instructions to determine whether the instruction performs the adding operation.
  • Subsequent devices (subsequent instructions) following this instruction may return the value of the addend variable before the comparison operation (such as the value of the addend variable V described above) and the preset value according to the return module 650 (as in the foregoing Rb Set value) The same comparison operation as that performed in the comparison module 620 is performed.
  • the above modules may be distributed in one device or distributed in multiple devices.
  • the above modules can be combined into one module or further split into multiple sub-modules.
  • the technical solution of the embodiment of the present invention has the following advantages, because the embodiment of the present invention combines the comparison operation and the addition operation into a new atomic comparison plus operation instruction, thereby enhancing the parallel function and improving the execution efficiency.
  • the present invention can be implemented by means of software plus a necessary general hardware platform, and of course, can also be hard. Pieces, but in many cases the former is a better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium, including a plurality of instructions for making a
  • the terminal device (which may be a cell phone, a personal computer, a server, or a network device, etc.) performs the methods described in various embodiments of the present invention.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)

Abstract

Procédé et dispositif d'exécution d'instruction. Selon ledit procédé une variable cumulateur est lue à partir de l'adresse de ladite variable cumulateur; ladite variable cumulateur est comparée à une valeur prédéterminée; si le résultat de la comparaison est calculé, ladite variable cumulateur est additionnée et le résultat de l'addition est assigné à la variable cumulateur; la valeur de la variable cumulateur avant comparaison est retournée.
PCT/CN2009/071558 2008-07-31 2009-04-29 Procédé et dispositif d'exécution d'instruction WO2010012167A1 (fr)

Applications Claiming Priority (2)

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CN200810144462.5 2008-07-31
CNA2008101444625A CN101324838A (zh) 2008-07-31 2008-07-31 一种指令执行方法和装置

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WO2010012167A1 true WO2010012167A1 (fr) 2010-02-04

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8528967B2 (en) 2010-10-19 2013-09-10 GM Global Technology Operations LLC Rear floor structure for a motor vehicle
WO2020161724A1 (fr) 2019-02-10 2020-08-13 Yeda Research And Development Co. Ltd. Anticorps inhibiteur anti-métalloprotéinase matricielle 7 (mmp-7) et utilisations associées

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101324838A (zh) * 2008-07-31 2008-12-17 华为技术有限公司 一种指令执行方法和装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1346462A (zh) * 1998-12-31 2002-04-24 英特尔公司 用于改进的判定预测的方法与装置
CN1788253A (zh) * 2003-06-05 2006-06-14 Arm有限公司 数据处理系统内的断定指令
WO2006113420A2 (fr) * 2005-04-14 2006-10-26 Qualcomm Incorporated Systeme et procede avec lesquels des instructions conditionnelles fournissent de facon inconditionnelle une sortie
CN101324838A (zh) * 2008-07-31 2008-12-17 华为技术有限公司 一种指令执行方法和装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1346462A (zh) * 1998-12-31 2002-04-24 英特尔公司 用于改进的判定预测的方法与装置
CN1788253A (zh) * 2003-06-05 2006-06-14 Arm有限公司 数据处理系统内的断定指令
WO2006113420A2 (fr) * 2005-04-14 2006-10-26 Qualcomm Incorporated Systeme et procede avec lesquels des instructions conditionnelles fournissent de facon inconditionnelle une sortie
CN101324838A (zh) * 2008-07-31 2008-12-17 华为技术有限公司 一种指令执行方法和装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8528967B2 (en) 2010-10-19 2013-09-10 GM Global Technology Operations LLC Rear floor structure for a motor vehicle
WO2020161724A1 (fr) 2019-02-10 2020-08-13 Yeda Research And Development Co. Ltd. Anticorps inhibiteur anti-métalloprotéinase matricielle 7 (mmp-7) et utilisations associées

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