WO2010011476A4 - Deposition methods and releasing stress buildup - Google Patents

Deposition methods and releasing stress buildup Download PDF

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Publication number
WO2010011476A4
WO2010011476A4 PCT/US2009/049300 US2009049300W WO2010011476A4 WO 2010011476 A4 WO2010011476 A4 WO 2010011476A4 US 2009049300 W US2009049300 W US 2009049300W WO 2010011476 A4 WO2010011476 A4 WO 2010011476A4
Authority
WO
WIPO (PCT)
Prior art keywords
liner layer
feature
stress
over
deposition method
Prior art date
Application number
PCT/US2009/049300
Other languages
French (fr)
Other versions
WO2010011476A3 (en
WO2010011476A2 (en
Inventor
Jing Tang
Nitin K. Ingle
Zheng Yuan
Rossella Mininni
Original Assignee
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to JP2011520071A priority Critical patent/JP2011529271A/en
Priority to CN2009801287646A priority patent/CN102105964B/en
Publication of WO2010011476A2 publication Critical patent/WO2010011476A2/en
Publication of WO2010011476A3 publication Critical patent/WO2010011476A3/en
Publication of WO2010011476A4 publication Critical patent/WO2010011476A4/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material is provided. The feature includes lines separated by a gap. The method includes forming a liner layer over the feature on the semiconductor substrate in a chamber. A stress of the liner layer over the feature is released to substantially reduce bending of the lines of the feature. A dielectric film is deposited over the stress-released liner layer to substantially fill the gap of the feature.

Claims

AMENDED CLAIMS received by the International Bureau on 16 April 2010 (16.04.2010)
1. A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material, the feature including lines separated by a gap, the method comprising: forming a liner layer over the feature on the semiconductor substrate in a chamber; releasing a stress of the liner layer over the feature by idling the liner layer in the chamber at a temperature of between about 4500C to about 5500C to substantially reduce bending of the lines of the feature; and depositing a dielectric film over the stress-released liner layer to substantially fill the gap of the feature.
2. The deposition method of claim 1 wherein releasing the stress of the liner layer includes idling the liner layer in the chamber for a predetermined time.
3. The deposition method of claim 1 wherein releasing the stress of the liner layer includes annealing the liner layer with a temperature from about a room temperature to about 10000C.
4. The deposition method of claim 1 wherein the lines of the feature have a line width of about 40 nm or less.
5. The deposition method of claim 4 wherein the lines of the feature have an aspect ratio of about 10 or more.
6. The deposition method of claim 1 wherein the liner layer is substantially conformal over the feature of the semiconductor substrate.
7. The deposition method of claim 1 wherein the liner layer is solider than the dielectric film.
8. The deposition method of claim 7 wherein the dielectric film is a flowable dielectric material.
9. The deposition method of claim 1 wherein the liner layer has a thickness between about 2 nm and about 10 nm on a sidewall of the lines of the feature.
10. The deposition method of claim 1 wherein the stress is between about 50 MPa and about 500 MPa.
11. A method for preventing a semiconductor structure from bending during a dielectric deposition, the method comprising: forming a liner layer over the semiconductor structure on a semiconductor substrate in a chamber, wherein the semiconductor structure includes lines having a line width of about 40 nm or less and an aspect ratio of about 10 or more; releasing a stress of the liner layer over the semiconductor structure by idling the liner layer in the chamber at a temperature of between about 4500C to about 5500C to substantially reduce bending the lines of the semiconductor structure; and depositing a flowable dielectric film over the stress-released liner layer to substantially fill a gap of the semiconductor structure.
12. The method of claim 11 wherein releasing the stress of the liner layer includes idling the liner layer in the chamber for a predetermined time.
13. The method of claim 11 wherein releasing the stress of the liner layer includes annealing the liner layer with a temperature from about a room temperature to about 10000C.
14. The method of claim 11 wherein the liner layer is substantially conformal over the feature of the semiconductor substrate.
15. The method of claim 11 wherein the liner layer has a thickness between about 2 nm and about 10 nm on a sidewall of the lines of the feature.
16. The method of claim 11 wherein the stress is between about 50 MPa and about 500 MPa.
16
PCT/US2009/049300 2008-07-23 2009-06-30 Deposition methods and releasing stress buildup WO2010011476A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011520071A JP2011529271A (en) 2008-07-23 2009-06-30 Deposition method to relieve stress build-up
CN2009801287646A CN102105964B (en) 2008-07-23 2009-06-30 Deposition methods for releasing stress buildup

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/178,051 US7674684B2 (en) 2008-07-23 2008-07-23 Deposition methods for releasing stress buildup
US12/178,051 2008-07-23

Publications (3)

Publication Number Publication Date
WO2010011476A2 WO2010011476A2 (en) 2010-01-28
WO2010011476A3 WO2010011476A3 (en) 2010-04-15
WO2010011476A4 true WO2010011476A4 (en) 2010-06-24

Family

ID=41569020

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/049300 WO2010011476A2 (en) 2008-07-23 2009-06-30 Deposition methods and releasing stress buildup

Country Status (6)

Country Link
US (1) US7674684B2 (en)
JP (1) JP2011529271A (en)
KR (1) KR20110051195A (en)
CN (1) CN102105964B (en)
TW (1) TW201017754A (en)
WO (1) WO2010011476A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102155119B1 (en) 2013-10-30 2020-09-11 삼성디스플레이 주식회사 Display device and method of manufacturing a display device
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
EP3487248B1 (en) * 2016-07-15 2021-05-19 Sony Corporation Wireless communication device and wireless communication method
KR102606653B1 (en) 2017-03-31 2023-11-24 어플라이드 머티어리얼스, 인코포레이티드 Two-step process for gapfilling high aspect ratio trenches with amorphous silicon films

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4270633B2 (en) * 1999-03-15 2009-06-03 株式会社東芝 Semiconductor device and method for manufacturing nonvolatile semiconductor memory device
JP3344397B2 (en) * 2000-01-21 2002-11-11 日本電気株式会社 Method for manufacturing semiconductor device
JP2001319968A (en) * 2000-05-10 2001-11-16 Nec Corp Method for manufacturing semiconductor device
JP4285899B2 (en) * 2000-10-10 2009-06-24 三菱電機株式会社 Semiconductor device having groove
KR100402392B1 (en) * 2001-11-06 2003-10-17 삼성전자주식회사 Semiconductor device having trench isolation structure and method of fabricating the same
US6576487B1 (en) * 2002-04-19 2003-06-10 Advanced Micro Devices, Inc. Method to distinguish an STI outer edge current component with an STI normal current component
US6825086B2 (en) * 2003-01-17 2004-11-30 Sharp Laboratories Of America, Inc. Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner
US7118987B2 (en) * 2004-01-29 2006-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of achieving improved STI gap fill with reduced stress
KR100602322B1 (en) * 2004-04-20 2006-07-14 에스티마이크로일렉트로닉스 엔.브이. A method for manufacturing a flash memory device and a flash memory device manufactured by the same
JP4594664B2 (en) * 2004-07-07 2010-12-08 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2006140408A (en) * 2004-11-15 2006-06-01 Sharp Corp Trench element isolation method for semiconductor device
JP2006156471A (en) * 2004-11-25 2006-06-15 Toshiba Corp Semiconductor device and its manufacturing method
US7361572B2 (en) * 2005-02-17 2008-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. STI liner modification method
JP2006269882A (en) * 2005-03-25 2006-10-05 Seiko Epson Corp Method for heat treating shallow trench isolation type element isolation layer
DE102005063129B4 (en) * 2005-12-30 2010-09-16 Advanced Micro Devices, Inc., Sunnyvale Method for producing a semiconductor device with isolation trench with reduced sidewall strain
JP2007258266A (en) * 2006-03-20 2007-10-04 Fujitsu Ltd Method of manufacturing semiconductor device
US8232176B2 (en) * 2006-06-22 2012-07-31 Applied Materials, Inc. Dielectric deposition and etch back processes for bottom up gapfill
JP2008010724A (en) * 2006-06-30 2008-01-17 Sharp Corp Semiconductor device, and its manufacturing method
KR100877107B1 (en) * 2007-06-28 2009-01-07 주식회사 하이닉스반도체 Method for fabricating interlayer dielectric in semiconductor device
KR100894101B1 (en) * 2007-09-07 2009-04-20 주식회사 하이닉스반도체 Method for fabricating isolation layer in semiconductor device
KR101002548B1 (en) * 2007-10-10 2010-12-17 주식회사 하이닉스반도체 Method of forming isolation layer in semiconductor device

Also Published As

Publication number Publication date
TW201017754A (en) 2010-05-01
CN102105964B (en) 2013-06-05
US20100022067A1 (en) 2010-01-28
CN102105964A (en) 2011-06-22
JP2011529271A (en) 2011-12-01
WO2010011476A3 (en) 2010-04-15
US7674684B2 (en) 2010-03-09
KR20110051195A (en) 2011-05-17
WO2010011476A2 (en) 2010-01-28

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