WO2009157250A1

WO2009157250A1 - Decode processing device, processor, electronic device, decode processing method, and decode processing program

Info

Publication number: WO2009157250A1
Application number: PCT/JP2009/057832
Authority: WO
Inventors: 希実石原
Original assignee: 日本電気株式会社
Priority date: 2008-06-23
Filing date: 2009-04-20
Publication date: 2009-12-30
Also published as: JP5083579B2; JPWO2009157250A1

Abstract

Provided is a decode processing device capable of reduing the number of cycles required to decode a variable length code as represented by encoding TC or T1s of CAVLC. The decode processing device decodes a variable length code bit stream including a prefix and a suffix following the prefix. The decode processing device includes: a bit-storage control means for holding part of the variable length code bit stream and enabling this holding process operation to be controlled; and a control information and decode address generation control means for generating, based on the prefix of the variable length code bit stream, a decode address used to refer to a decode table, which is necessary for decoding, and generating control information used to update the variable length code bit stream for the bit-storage control means. A process for outputting the decode address is performed simultaneously with a process for updating the variable length code bit stream.

Description

Decoding processing device, processor, electronic device, decoding processing method, and decoding processing program

The present invention relates to a decoding processing device, a processor, an electronic device, a decoding processing method, and a decoding processing program. The present invention relates to a decoding processing apparatus that decodes data encoded based on the H.264 standard and decodes variable-length codes.

In general, in an image and audio compression encoding apparatus, an input time domain signal is converted into a frequency domain coefficient by orthogonal transform, for example, discrete cosine transform (DCT), quantized, and then coded. Assign. In this code allocation, in order to improve compression efficiency, variable length coding is often performed in which the code length is changed in accordance with the probability of occurrence frequency.

As an example of variable length coding, H.264 / AVC (MPEG-4AVC: Moving Picture Expert Group4 Part10 Advanced Video Coding) used in the CAVLC (Context-based Adaptive Variable Code length encoding type such as Context Adaptation)

In CAVLC, a quantized DCT coefficient is encoded for each 4 × 4 block to generate an encoded bit stream. When decoding the encoded bit stream that is the encoded data string, it can be performed by dividing it into the following four processes.
In the first process, the number of non-zero coefficients (TC: Total Coefficient) appearing in the 4 × 4 block and the number of consecutive ± 1 (T1s: Trailing ones) appearing in the 4 × 4 block are performed. .
In the second process, a process for obtaining a value (level value) of a coefficient other than 0 is performed.
In the third process, a process for obtaining the sum of the number of consecutive zero coefficients (runs) is performed.
In the fourth process, a process for obtaining the number of remaining runs when decoding its own run is performed.
Of these four processes, the process that takes time to calculate is the first stage, which is a process for obtaining TC and T1s.

As a related technique of such a decoding calculation processing method by CAVLC, for example, Patent Document 1 shown below can be cited.

In Patent Document 1, processing for obtaining TC and T1s is performed using tables as shown in FIGS. FIG. It is a H.264 NumVLC0 table. The NumVLC0 table is assigned a code using TC and T1s as keys. FIG. 42 is a table constructed based on the table of FIG. 41 disclosed in Patent Document 1.

In the decoding calculation processing method disclosed in Patent Document 1, when decoding TC and T1s encoded by CAVLC, the content is specified by the number of consecutive zeros (prefix length) and the subsequent binary code (suffix). The table shown in FIG. 42 is used. The contents of the table shown in FIG. 42 are a pair of TC and T1s.

At the time of decoding, a computer that performs decoding processing first obtains a prefix length. Next, a suffix following the prefix is obtained, and a table is referenced using the prefix length and the suffix to obtain TC and T1s.
In this series of processing, in order to obtain the prefix length and suffix, an operation (unpacking processing) for cutting out data having a specified bit width from the bit stream is required. An example of an apparatus that performs an unpacking process is described in Patent Document 2.

FIG. 47 is a diagram illustrating a configuration in which a processing device 1032 is incorporated into a processor 1031 of related technology disclosed in Patent Document 2.
This processor 1031 has a five-stage pipeline, an IF stage for fetching instructions, a REG stage for decoding the instructions and fetching data from the core register (Core Reg), an EXE stage by a numerical arithmetic unit (ALU), a bus (BUS) and a MEM stage for inputting / outputting data to / from the memory 1033, and a WB stage for writing data back to the core register (Core Reg).
As a result, instructions and data are sequentially transferred and processed by a numerical operation unit (ALU).
Further, the processor 1031 is provided with a dedicated register (Reg) 1034 at the REG stage and a computing unit 1035 at the EXE stage, respectively, and a processing device 1032 by the dedicated register (Reg) 1034 and the computing unit 1035 is added. .
Corresponding to this additional configuration, the processor 1031 adds an unpacking instruction for cutting out data having a specified bit width from the dedicated register (Reg) 1034.

Further, in Patent Document 3, the CAVLC processing unit in the CAVLC unit issues a get request with a predetermined number of requested bits to a data access circuit having an M-bit buffer storing stream data. After obtaining the data, the number of “0 coefficients” is detected. Then, the CAVLC processing unit returns unnecessary bits to the data access circuit by an unget request.
Similarly, the CAVLC processing unit issues a get request with a predetermined number of requested bits to a data access circuit having an M-bit buffer that stores stream data, acquires data from the data acquisition circuit, The number of consecutive “0 coefficients” is detected. Unnecessary bits are returned to the data access circuit by an unget request (paragraph numbers 0108 to 0114 in Patent Document 3).
As described above, the CAVLC processing unit sequentially obtains and returns data every time it detects the number of “0 coefficients” or the continuous number of “0 coefficients” from the stream data of the data access circuit. Process.
JP 2007-49670 A Japanese Patent No. 3772976 JP 2007-304797 A

However, the processing apparatus disclosed in Patent Document 2 as a related technique has the following problems.

That is, the first problem is that a plurality of cycles are required to determine the cut-out width of the bit specified by the unpacking instruction.
The cause of this problem is that the bit cutout width depends on the bit pattern in the bit stream, so that data must be read from the bit stream and the bit pattern must be examined.

Further, when the decoding process in CAVLC according to Patent Document 1 is performed by the processor of Patent Document 2, the following second problem occurs.
That is, the second problem is that a large number of cycles are required for address calculation necessary for referring to a table for obtaining a decoding result.
The cause of this problem is to calculate the row index from the prefix length and the column index from the suffix in order to obtain the address necessary for the table reference to obtain the decoding result. This is because the address for decoding referring to the table must be calculated.

The first and second problems will be described with reference to FIG. FIG. 48 is a time chart showing a process of decoding TC and T1s created based on the processing apparatus disclosed in Patent Document 2.
First, from the first clock to the fifth clock, the processor performs a process for obtaining a row index and a suffix length.
Specifically, the processor loads data from the memory, calculates a prefix length, obtains an address referring to the row index table and the suffix length table from the obtained prefix length, and obtains the row index and the suffix length by referring to the table.
Next, from the sixth clock to the eighth clock, the processor cuts out the suffix from the read data and performs a process for obtaining a column index. Specifically, the ALU erases the read data by masking the prefix portion, shifts the data, extracts only the suffix, and calculates the column index.
From the ninth clock to the tenth clock, the processor decodes TC and T1s. Specifically, the arithmetic unit (ALU) calculates a decoding address from the row index and the column index obtained by the above processing, and obtains TC and T1s by load processing using the address.
Finally, from the 11th clock to the 13th clock, the processor performs a process of updating the dedicated register (Reg) 1034 in FIG.
Specifically, the arithmetic unit (ALU) adds the prefix length and the suffix length to calculate the amount of bits to be updated, and updates the dedicated register (Reg) 1034 by a bit read instruction.
As described above, in the processing device disclosed in Patent Document 2, more than half of the total number of cycles depends on the calculation of the prefix length and the address.

Also in Patent Document 3, since the CAVLC processing unit needs to sequentially cut out data, the same problem as described above occurs.

An object of the present invention is to provide a decoding processing device, a processor, an electronic device, a decoding processing method, and a decoding processing program capable of reducing the number of cycles necessary for decoding a variable length code represented by TC and T1s encoding of CAVLC Is to provide.

In order to achieve the above object, a decoding processing apparatus of the present invention is a decoding processing apparatus that performs a process of decoding a variable-length code bitstream that is an encoded data sequence including at least a prefix and a suffix that follows the prefix. , Temporarily holding a part of the variable-length code bitstream, and controlling input / output processing for holding, and the variable-length code bitstream input from the first control means Based on the prefix and the suffix, a decoding address used for referring to a decoding table necessary for decoding is generated, and control information for updating the variable-length code bitstream to the first control means is provided. Second control means for supplying, wherein the second control means provides the address for decoding. A process of forming, and characterized by performing a process of updating the variable length code bit stream held in said first control means.

A processor according to the present invention is a processor capable of executing pipeline processing including a decoding processing device that performs processing for decoding a variable-length code bitstream that is an encoded data sequence including at least a prefix and a suffix following the prefix. In the register stage in the processor pipeline process, a part of the variable-length code bitstream is temporarily held, and a first control unit for controlling an input / output process for holding, and in the processor pipeline process, In the execution stage, based on the prefix and the suffix of the variable length code bitstream input from the first control means, a decoding address used for decoding table reference necessary for decoding is generated, and First control Second control means for generating control information for updating the variable-length code bitstream for a stage, wherein the second control means generates the decoding address, and the first control And a process of updating the variable-length code bitstream of the means.

The decoding processing method of the present invention is a decoding processing method for performing processing for decoding a variable-length code bitstream that is an encoded data string including at least a prefix and a suffix following the prefix, and the variable-length code bitstream A first control for performing an input / output process for temporarily holding a part of the bit stream temporarily holding unit, and subsequently, the prefix of the variable length code bit stream input from the bit stream temporary holding unit and Based on the suffix, a decoding address used for referring to a decoding table necessary for decoding is generated, and control information for updating the variable-length code bitstream is supplied to the bitstream temporary holding unit. 2 and when performing the second control, the decoding add And generating a scan, and characterized by performing a process of updating the variable length code bit stream of the bit stream temporary storage unit.

The decoding processing program of the present invention is a decoding processing program capable of realizing various functions by a computer that performs processing for decoding a variable-length code bitstream that is an encoded data sequence including at least a prefix and a suffix following the prefix. A first control function for performing an input / output process for temporarily holding a part of the variable length code bitstream in the bitstream temporary holding unit, and the variable length code bits held in the bitstream temporary holding unit Based on the prefix and the suffix of the stream, a decoding address used for referring to a decoding table necessary for decoding is generated, and control information for updating the variable-length code bitstream of the bitstream temporary holding unit is generated A second control function to In the second control function, the computer implements a function of performing the process of generating the decoding address and the process of updating the variable-length code bitstream of the bitstream temporary holding unit. It is characterized by letting.

According to the present invention, a decoding address generation process based on a prefix and a suffix and a variable-length code bitstream update process can be performed to prepare for the next decoding, and for variable-length code decoding. The number of necessary cycles can be reduced.

Hereinafter, an example of an embodiment of the present invention will be specifically described with reference to the drawings.
[First Embodiment]
(Overall processor configuration)
First, a specific configuration of a processor including a decoding processing apparatus according to the present embodiment will be described from the overall configuration, and then a detailed configuration of each unit will be described. FIG. 1 is a block diagram showing an example of an overall schematic configuration of a processor including a decoding processing device according to the first embodiment of the present invention.

The processor system 1 of the present embodiment shown in FIG. 1 includes a memory 10 and a processor 20 connected to the memory 10 via a bus Bus.

The processor 20 in the present embodiment replaces the processor shown in FIG. 47 with the processing device 1032, and a decoding processing device 50 (variable length) having a bit storage 52, a control information / row index generator 53, and a decoding address generator 54. A coding / decoding device).

The decoding processing device 50 decodes a variable-length code bit stream that is an encoded data sequence including at least a prefix and a suffix subsequent to the prefix.
The decoding processing device 50 stores a bit stream in the REG stage in the processor pipeline process, and stores a bit index 52 and a bit index in the EXE stage in the processor pipeline process. A control information / row index generator 53 for generating information for the buffer 52 to control the buffer, and a decoding address generator 54 for receiving information from the control information / row index generator 53 and generating an address. It is configured to include.

The processor 20 is equipped with a decoding processing device 50 and can execute pipeline processing. In this configuration, the processor 20 has a five-stage pipeline, an IF stage for fetching an instruction into the IF unit 21, and decoding the instruction. REG stage for fetching data from the core register (Core Reg) 22, EXE stage by the numerical operation unit (ALU) 23, MEM stage for inputting / outputting data to / from the memory 10 via the bus (BUS), core register ( (Core Reg) 22 to execute the processing at the WB stage for writing back the data.

Here, the IF stage is an abbreviation for Instruction Fetch stage (instruction fetch stage). In the IF stage, the IF unit (instruction memory) 21 performs processing for fetching an instruction from the memory 10.
The REG stage is an abbreviation for Register stage (register stage). In the REG stage, the numerical operation unit (ALU) 23 performs a process of extracting data from the core register (Core Reg) 22.
The EXE stage is an abbreviation for an execution stage (execution stage), and in the EXE stage, a numerical operation unit (ALU) 23 performs arithmetic processing.
The MEM stage is an abbreviation for a Memory stage (memory stage). In the MEM stage, the Load / Store Unit 24 performs a process of inputting / outputting data to / from the memory 10 via a bus (BUS).
The WB stage is an abbreviation for the Write Back stage (write back stage), and in the WB stage, the core register (Core Reg) 22 performs a process of storing data.
Instructions and data are sequentially transferred to each of the above stages, and processing by the numerical operation unit (ALU) 23 is executed.

Furthermore, the processor 20 has

processor pipeline registers

31A, 31B, 31C, and 31D for each stage boundary.

(Detailed configuration of bit storage)
Details of the bit storage 52 shown in FIG. 1 will be described with reference to FIG.
The bit storage 52 has a bit buffer controller 61 and a bit buffer 62 controlled by the bit buffer controller 61.

The bit buffer controller 61 operates according to an input signal INST_CNTL transferred from the IF stage.
When INST_CNTL is an instruction indicating initialization of the bit buffer 62, the bit buffer controller 61 reads data from the memory 10 using the address indicated in the instruction and stores the read data in the bit buffer 62. To do.

Further, the bit buffer controller 61 advances the address indicated in the instruction by the data read from the memory 10 and stores the bit stream (data) read up to that address in the bit buffer 62.
When INST_CNTL is an instruction to perform variable length code decoding processing, the bit buffer controller 61 outputs the data REG_DATA read from the bit buffer 62 and, at the same time, adds the output bit width BIT_WIDTH to the data REG_DATA.

Also, the bit buffer controller 61 outputs a SEL_TAB signal for selecting a table in the control information / row index generator 53. As the output SEL_TAB, a value read from a register designated by a decoding processing instruction of INST_CNTL is used.

When the bit buffer controller 61 receives the instruction INST_UPD for updating the bit buffer 62, the bit buffer controller 61 shifts the data of the bit stream stored in the bit buffer 62 by the number of bits specified by the INST_UPD. The data of the bit stream stored in is updated.

When the bit buffer controller 61 reads data from the bit buffer 62, the bit buffer controller 61 determines that the number of bits of data stored in the bit buffer 62 is small. A bit replenishment process is performed by replenishing the bit buffer 62 with a number of data.
Here, the case where it is determined that the number of bits is small means a case where the number of bits of data written to the bit buffer 62 is smaller than the number of bits of data to be read. The determination condition is that the number of bits stored in the bit buffer 62 in the specific period is preferably, for example, one third or less of the storable capacity of the bit buffer 62.
More specifically, bit supplementation is performed when the bit buffer is 96 bits or less, for example, 32 bits or less.
When the bit buffer controller 61 performs the bit replenishment process, it is possible to prevent the reading process of data (variable length bit stream) from the bit buffer 62 from being stopped, and to contribute to the speedup in the decoding process.
When performing the bit replenishment process, the bit buffer controller 61 issues an instruction MEM_LOAD using the address held when the instruction for initialization is executed, and acquires new bit data from the memory 10. The bit data read from the memory 10 is input to the bit buffer 62 as MEM_ST shown in FIG.

(Detailed configuration of control information / low index generator)
FIG. 3 shows a detailed configuration of the control information / row index generator 53 of FIG.
As shown in FIG. 3, the control information / row index generator 53 has a four-stage pipeline structure, and the prefix counter 71 that counts the prefix length of the data REG_DATA read from the bit buffer 62, and the count A prefix address generator 72 for generating an address for referring to a table to be described later from the prefix length, a row index table (first table) group 73 composed of a plurality of tables storing row indexes, and a plurality of storing suffix lengths A suffix length table (second table) group 74 consisting of the following tables, an acquisition unit 77 for acquiring a corresponding row index from a selected table of the row index table group 73 based on a prefix address, and a suffix length table An acquisition unit 78 that acquires a corresponding suffix length from a selected table of the group of colors 74 based on a prefix address, an adder 76 that adds the prefix length and the suffix length acquired by the acquisition unit 78, and a prefix The update instruction generator 75 generates an instruction to update the bit buffer 62 shown in FIG. 2 as an example of control information from the length, suffix length, data REG_DATA read from the bit buffer 62, and input BIT_WIDTH. . The row index table (first table) group 73 and the suffix length table (second table) group 74 are stored in the storage unit, and the

acquisition units

77 and 78 access the storage unit respectively. The row index from the row index table (first table) group 73 and the suffix length from the suffix length table (second table) group 74 are respectively acquired. The control information / row index generator 53 generates control information and a row index.

Further, the control information / row index generator 53 has

pipeline registers

81A, 81B, 81C for each boundary of the pipeline stages.

The operation of the apparatus shown in FIG. 3 will be described.
In the control information / row index generator 53, when the data REG_DATA read from the bit buffer 62 is input to the prefix counter 71 in the first pipeline stage, the prefix counter 71 sets the prefix length of the REG_DATA. Count. The prefix counter 71 outputs the counted prefix length of REG_DATA to the pipeline register 81A.

In the second pipeline stage, the control information / low index generator 53 performs the following operation. That is, when the counted prefix length is input to the prefix address generator 72 via the pipeline register 81A, the prefix generator 72 uses the row index table group 73 and the suffix length table group 74 based on the counted prefix length. Calculate the address referring to. The prefix generator 72 outputs the address to the pipeline register 81B.

In the third pipeline stage, the control information / row index generator 53 performs the following operation. That is, when the calculated address information is input to the acquisition unit 77 and the acquisition unit 78 via the pipeline register 81B, the acquisition unit 77 receives the table selection signal SEL_TAB from the bit buffer controller 61 and the address. Based on this, the row index table group 73 is accessed to obtain a row index. Similarly, the acquisition unit 78 obtains a suffix length by accessing the suffix length table group 74 based on the table selection signal SEL_TAB from the bit buffer controller 61 and the address.
The acquisition unit 77 passes the acquired row index through the pipeline register 81C and outputs it as ROW_INDEX.

In the fourth pipeline stage, the control information / low index generator 53 performs the following operation. That is, the adder 76 obtains the prefix length counted by the prefix counter 71 and the suffix length acquired by the acquisition unit 78, adds the prefix length and the suffix length, and decodes the code. The code length COD_WIDTH is obtained.

Next, the control information / low index generator 53 performs the following operation. That is, the update instruction generator 75 includes the suffix length acquired by the acquisition unit 78, the prefix length counted by the prefix counter 71, the data REG_DATA read from the bit buffer 62, and the bit buffer controller 61. And an instruction INST_UPD for updating the bit buffer 62 of FIG. 2 is generated on the basis of the output bit width BIT_WIDTH output from.

The contents of the row index table group 73 are updated by the instruction UPD_ROW. When the instruction UPD_ROW is executed, the register data specified in the instruction is read from the core register (Core Reg) in the REG stage, and the contents to be updated, the table to be updated, and the position to be updated are displayed. Data at the indicated address is obtained.

In the subsequent EXE stage, based on the instruction UPD_ROW, the row index table is updated using the data read in the REG stage.

Also, the suffix length table group 74 is updated in the same manner as the row index table group 73 based on the instruction UPD_SUF.

(Detailed configuration of decoding address generator)
FIG. 4 shows details of the decoding address generator 54 of FIG.
The decoding address generator 54 shown in FIG. 4 receives REG_DATA, COD_WIDTH, and BIT_WIDTH, adjusts the bits of REG_DATA to generate a column index, and generates a column index and input. The adder 92 adds the ROW_INDEX, and generates and outputs a decoding address ADDRESS.

Here, the bit adjustment / column index generator 91 performs the processing described in the flowchart of FIG.
First, in step S101 of FIG. 5, the bit adjustment / column index generator 91 calculates COD_WIDTH (added prefix length and suffix length) and BIT_WIDTH (number of bits of the variable length code bit stream output from the bit buffer). The difference is obtained (difference calculating step or difference calculating function).
Here, the result is X.

Next, the bit adjustment / column index generator 91 right-shifts REG_DATA by X in step S102 (prefix and suffix data extraction step or prefix and suffix data extraction function).
Here, the result is SH_DATA. Thereby, bit adjustment can be performed.

Finally, the bit adjustment / column index generator 91 obtains and outputs the column index COL_INDEX from SH_DATA in step S103 (column index calculation step or column index calculation function).
The bit adjustment / column index generator 91 performs bit adjustment, and in addition to this, the bit adjustment / column index generator 91 generates a column index.

Here, the bit storage 52 of the present embodiment can also be referred to as an example of “first control means”. Furthermore, the control information / row index generator 53, the decoding address generator 54, and the generator pipeline register 55 of the present embodiment may constitute an example of the “second control means 51”.

The bit buffer 62 of the present embodiment can also be referred to as an example of a “bitstream temporary storage unit”. Furthermore, the bit buffer controller 61 of the present embodiment can also be referred to as an example of a “bit control unit”.
Furthermore, the control information / row index generator 53 of the present embodiment can also be said to be an example of a “first generation control unit”. The decoding address generator 54 according to the present embodiment can also be said to be an example of a “second generation control unit”.

Furthermore, an example of a “table information acquisition unit” can be configured by the acquisition unit 77 and the acquisition unit 78 of the present embodiment. Furthermore, the update instruction generator 75 of the present embodiment can also be said to be an example of an “update instruction generator”. Further, the prefix counter 71 of the present embodiment can also be said to be an example of a “prefix counter”. Furthermore, the prefix address generator 72 according to the present embodiment can be said to be an example of a “prefix address calculation unit”.

Furthermore, the bit adjustment / column index generator 91 of the present embodiment can also be referred to as an example of a “column index generation unit”. Further, the adder 92 of the present embodiment can also be referred to as an example of an “adder”.

This “first control means” can temporarily hold a part of the variable-length code bitstream and can control input / output processing for holding it.

Further, the “second control unit” performs decoding based on the prefix and the suffix of the variable-length code bitstream input from the first control unit in the execution stage in the processor pipeline processing. A decoding address used for referring to a necessary decoding table can be generated, and control information for updating the variable-length code bitstream can be supplied to the first control means. In this case, the second control unit can perform a process of generating the decoding address and a process of updating the variable length code bitstream held in the first control unit.

Furthermore, it is preferable that the second control unit simultaneously performs the process of generating the decoding address and the process of updating the variable length code bitstream held in the first control unit.
The reason is that by performing each process simultaneously, the number of cycles is reduced as compared with the case where each process is performed sequentially, and the processing speed can be improved.
Here, “simultaneously performing” a plurality of processes includes a case where a plurality of processes are performed in parallel. Furthermore, a case where a plurality of processes are performed “simultaneously” can include a case where “a process is performed in a pseudo manner” in a process like a computer.
Further, the present invention is not limited to the case where a plurality of processes are performed simultaneously, and a plurality of processes may be started at the same time, and the timings at which each process ends may differ.
Furthermore, the start timing of each process may be different, and the end timing of each process may be different.
Furthermore, each process may be executed sequentially.
Hereinafter, the control that can be performed “simultaneously” in the present specification can include the various control methods described above.

Thus, first, the bit storage 52 of the processor performs a process of holding a part of the variable length code bit stream.

Then, the control information / row index generator 53 (first generation control unit) of the processor sets the decoding address based on the prefix of the variable-length code bitstream in the execution stage in the processor pipeline processing. A row index to be obtained is generated by referring to the row index table, and a suffix length corresponding to the prefix length is generated by referring to the suffix length table.
Further, the control information / row index generator 53 of the processor updates the variable length code bit stream in the bit storage 52 as an example of the control information after generating them in the execution stage in the processor pipeline processing. Generate update instructions.

Next, the decoding address generator 54 (second generation control unit) of the processor generates a column index for obtaining the decoding address from the suffix length in the execution stage in the processor pipeline processing. The decoding address is generated based on the column index and the row index.

Here, the control information / row index generator 53 generates a decoding address in the second generation control unit after generating the row index and the suffix length; The process of updating the variable-length code bitstream can be executed simultaneously (in parallel with the unit clock period).

In the control information / row index generator 53, a first table (row index table) storing a prefix address and a row index according to the prefix length, and a prefix address and a suffix length according to the prefix length are stored. And a second table (suffix length table).

In this case, in the control information / row index generator 53, the prefix counter 71 is in the execution stage in the processor pipeline processing, and the first control means in the first stage in the index generation pipeline processing. The prefix length of the variable-length code bit stream read from is counted.

Then, in the control information / row index generator 53, a prefix address generator 72, in the second stage in the index generation pipeline process, the first table from the prefix length counted by the prefix counting unit, A prefix address for referring to the second table is calculated.

Further, in the control information / row index generator 53, the

acquisition units

77 and 78 use the prefix address obtained by the prefix address calculation unit in the third stage in the index generation pipeline processing, and Each of the first table and the second table is referred to, and the corresponding row index and the suffix length are obtained.

In the control information / row index generator 53, the update instruction generator 75 performs the suffix length and prefix count acquired by the

acquisition units

77 and 78 in the fourth stage of the index generation pipeline processing. Based on the prefix length counted in the unit, the data REG_DATA read from the bit buffer 62, and the output bit width BIT_WIDTH output from the bit buffer controller 61, an update command which is the control information to be updated is generated.

Further, the bit adjustment / column index generator 91 of the decoding address generator 54 generates the column index based on the suffix length, and the adder 92 adds the column index and the row index to decode. Address.

Here, the “first control means” includes a bit stream temporary holding unit that temporarily holds the variable length code bit stream, and bit control that performs input / output control of the variable length code bit stream in the bit stream temporary holding unit. Parts.
In this case, when the bit control unit reads bit data having a predetermined number of bits from the variable-length code bit stream held by the bit stream temporary holding unit, and the remaining number of bits after reading is small, A bit replenishment function for concatenating and storing a part of the variable-length code bitstream holding the correct data, and updating the variable-length code bitstream held based on the update command that is the control information to be updated And an update processing function for performing processing.

Furthermore, the first table and the second table may each include a plurality of tables corresponding to the type of decoding NumVLC table in the context adaptive variable length coding scheme.
In this case, the first control means can generate table selection control information for selecting the type and supply it to the first generation control unit (control information / row index generator). In addition, the table information acquisition unit selects one of the plurality of tables in the first table based on the table selection control information, and the plurality of tables in the second table Any one can be selected.

As described above, according to the present embodiment, the decoding address generation process based on the prefix and the update process of the bit storage control unit can be performed at the same time, and preparation for the next decoding can be performed. Can reduce the number of cycles required.

More specifically, the first effect is that the update of the bit buffer based on the prefix length, the suffix length, and the data REG_DATA read from the bit buffer 62 can be performed simultaneously with the generation of the decoding address to prepare for the next decoding. It can be done.

The reason for this is that by providing an update instruction device for generating an instruction for updating the bit buffer from the prefix length, the suffix length, and the data REG_DATA read from the bit buffer 62 in the variable length decoding device of the present invention, This is because the bit buffer can be updated simultaneously with the generation of the decoding address after the suffix length is known.

The second effect is that the number of cycles required for decoding the variable length code can be reduced, and the decoding processing speed can be increased.

The reason for this is that by providing a circuit that automatically checks the bit pattern of the bit stream to determine the prefix length, suffix, and decoding address, the number of cycles required for checking the bit pattern for reading data is reduced. is there.
In other words, the bit width specified by the unpacking instruction is automatically determined based on the bit pattern in the bit stream, and an address used for table reference for decoding the code code can be generated.

In this way, the bitstream prefix is counted, the row index and suffix length are read from the row index table and suffix length table, respectively, using the prefix as a key, and the prefix length, suffix length, and data REG_DATA read from the bit buffer 62 are stored Then, a suffix is extracted from the bit stream, a column index is obtained, and a row index and a column index are added and output to obtain a decoding address. At the same time, the bit buffer storing the bit stream can be updated based on the prefix length and the suffix length, and the decoding processing speed can be increased.

[Second Embodiment]
Next, a second embodiment according to the present invention will be described with reference to FIGS. In the following, description of the substantially similar configuration of the first embodiment will be omitted, and only different parts will be described. FIG. 6 is a block diagram showing an example of a detailed configuration of the control information / row index generator according to the second embodiment of the present invention.

In the first embodiment described above, the control information / row index generator has a configuration including a row index table group and a suffix length table group made up of a plurality of tables. The generator has a single row index table and a single suffix length table.

Specifically, as shown in FIG. 6, the control information / row index generator 153 of this embodiment includes a single row index table 173, a single suffix length table 174, and each of these tables. It is configured to include

acquisition units

177 and 178 that acquire data.
Accordingly, the control information / row index generator 153 does not require the table selection signal SEL_TAB, and the table selection signal SEL_TAB is deleted from the control information / row index generator 53 of the first embodiment. ing.

FIG. 7 shows a block diagram of a bit storage that is changed in accordance with the control information / row index generator.
The bit storage 152 according to the second embodiment has a configuration in which the table selection signal SEL_TAB is deleted from the same input / output as that of the first embodiment. That is, the bit buffer controller 161 is configured not to output a table selection signal.

Other configurations, other steps or functions, and the effects thereof are the same as those in the above-described embodiment. In the above description, the operation content of each step described above, the constituent elements of each unit, and the functions thereof may be programmed, and the program (software program) may be executed by a computer.

[Third Embodiment]
Next, a third embodiment according to the present invention will be described with reference to FIGS. Here, a more specific example of the first embodiment will be described as a third embodiment.

The bit buffer 62 constituting the bit storage 52 is constituted by a register of 96 bits, for example.
Further, the input INST_CNTL in the bit storage 52 is configured so that, for example, 16 bits can be input.

As shown in FIG. 8, the input INST_UPD is 6 bits, the input MEM_ST is 32 bits, the output REG_DATA is 32 bits, the output SEL_TAB is 2 bits, the output BIT_WIDTH is 6 bits, and the output MEM_LOAD is 40 bits. Is done.
The bit stream read from the memory is stored so that the left end of the bit buffer 62 is the head of the bit stream.
Here, regarding the output SEL_TAB, SEL_TAB values 0, 1, and 2 select the 0th, 1st, and 2nd tables of the row index and suffix length table, respectively.

(About INST_UPD)
The contents of the present embodiment of INST_UPD (bit buffer update instruction) will be described using the example shown in FIG.
As shown in FIG. 11, INST_UPD uses the first 1 bit as control information and uses 5 bits excluding the first 1 bit as bit number data to be updated.
The bit buffer controller updates the bit buffer when the control information is 1, and does nothing when it is 0.
In the example of FIG. 11, since the control information is 1, the bit buffer is updated, and the bit buffer is updated by left shift by 7 bits, which is the number of bits indicated in the subsequent bit number update data.

(About INST_CNTL)
FIG. 13 shows a configuration example in the present embodiment regarding the instruction INST_CNTL from the processor.
The DEC_CODE instruction shown in FIG. 12 and the INITIALIZE instruction shown in FIG. 13 are 16-bit wide instructions.
The DEC_CODE instruction (decoding start instruction) includes an 8-bit operand code OPCODE, a 3-bit REGNUM1 that specifies a register number for storing the generated address, and a 3-bit REGNUM2 that specifies a register that stores a value to be output to SEL_TAB. And 2-bit 0.
This instruction is an instruction to start the variable length decoding process. With this instruction, the bit buffer controller 61 loads 32-bit data from the bit buffer 62 and outputs it to REG_DATA. Output to BIT_WIDTH, and further output to SEL_TAB the value read from the register specified by REGNUM2.
Further, the result of instruction execution is returned with the result address stored in the register designated by REGNUM1.

The INITIALIZE instruction (initialization instruction) is composed of an 8-bit operand code OPCODE, a 3-bit REGNUM that designates a register number in which a memory address is stored, and a 5-bit 0, and performs an operation for initializing the decoding processor. .
When the INITIALIZE instruction is issued, 96 bits of data are loaded from the address stored in the register specified by REGNUM of the memory, and the data is stored in the bit buffer 62.

Also, the bit buffer controller 61 holds an address obtained by advancing the address of the register designated by REGNUM by 96 bits.

(About bit replenishment processing)
A bit replenishment method for the bit buffer 62 in this embodiment will be described.
In the present embodiment, when a DEC_CODE instruction is received and 32-bit data is read from the bit buffer 62, the number of bits obtained by subtracting 32 bits from the number of bits stored in the bit buffer 62 falls below 32 bits. In addition, the bit buffer controller 61 performs bit replenishment processing.

Bit replenishment processing is performed by issuing a bit replenishment instruction MEM_LOAD using the address held by the bit buffer controller 61.

FIG. 14 shows an outline of the MEM_LOAD instruction (bit supplement instruction).
MEM_LOAD has an 8-bit operand code OPCODE indicating a load instruction, and an ADDRESS field indicating an address held by the bit buffer 62.
The 32-bit data read from the memory is transferred to the bit buffer controller through the input MEM_ST.

The bit buffer controller 61 loads 32-bit data using this MEM_LOAD instruction, and advances the address held by the bit buffer controller 61 by the loaded amount.
Further, the bit buffer controller 61 adds the data obtained from the input MEM_ST to the end of the data held in the bit buffer 62.
Therefore, for example, bit supplementation is performed like B1, B2, B3, and B4 shown in FIG.

(About control information and low index generator)
As shown in FIG. 9, the control information / row index generator 53 has an output of the prefix counter 71 of 4 bits and an output of the prefix address generator 72 of 32 bits.
The row index table group 73 has three tables, table 0, table 1, and table 2, and the output is, for example, 32 bits.
The suffix length table group 74 has three tables, table 0, table 1, and table 2, and the output is, for example, 3 bits.
The output COD_WIDTH of the control information / low index generator 53 is 6 bits.

An outline of the prefix counter 71 will be described with reference to FIG. The code shown in FIG. 16 is data read from the bit buffer 62 and input to the prefix counter.
Now, the code shown in FIG. 16 has five consecutive zeros as a prefix.
The prefix counter 71 in this embodiment counts the number of consecutive 0s and outputs the prefix length as 5.
Here, in this embodiment, consecutive 0s are used as prefixes, but consecutive 1s may be used as prefixes.

Regarding the tables in the row index table group 73 and the suffix length table group 74, the configuration method in the present embodiment will be described by taking the configuration of the table 0 shown in FIGS. 17 and 18 as an example.

The row index table 0 in FIG. 17 and the suffix length table 0 in FIG. 18 are configured based on the table in FIG. 40. In the row index table, the prefix length and the row index from 0 to 14 are in the suffix length table. Prefix lengths from 0 to 14 are associated with suffix lengths.

Here, for the table 1 and the table 2 of the row index table group 73 and the suffix length table group 74 in this embodiment, It is assumed that the NumVLC1 table (for example, FIGS. 43 and 44) and the NumVLC2 table (for example, FIGS. 45 and 46) of H.264 are constructed in the same manner as the NumVLC0 table.
In the present embodiment, these three tables are used by appropriately switching as necessary. This is because H.264 CAVLC appropriately selects the NumVLC table and proceeds with decoding.

The UPD_ROW instruction (row index table update instruction) and the UPD_SUF instruction (suffix length table update instruction) for updating the row index table group 73 and the suffix length table group 73 will be described with reference to FIGS.
The UPD_ROW instruction and the UPD_SUF instruction are 32-bit instructions, respectively, REGNUM1 for specifying a register storing an 8-bit OPCODE indicating an operand and an address indicating a position to be updated in the table, and a register storing a content to be updated And a REGNUM3 field indicating a register storing contents for selecting a table.

An address generation method for the prefix address generator 72 that generates an address for referring to the table will be described.
As shown in FIGS. 17 and 18, the address of the table corresponds to the prefix length, and when the prefix increases by 1, the address increases by 4.
Therefore, the prefix address generator of this embodiment generates an address by shifting the input prefix length to the left by 2 bits.

(About decryption address generator)
The configuration of the decoding address generator 54 in this embodiment will be described.
As shown in FIG. 10, the bit adjustment / column index generator 91 is a 32-bit output, and the output column index is added to the input ROW_INDEX and output as a 32-bit decoding address.

Next, the operation of the bit adjustment / column index generator 91 in this embodiment will be described with reference to FIG.
First, in step S101 of FIG. 5, the bit adjustment / column index generator 91 takes the difference between the inputted BIT_WIDTH and COD_WIDTH and sets the result as X (difference calculating step or difference calculating function).

Subsequently, in step S102, the bit adjustment / column index generator 91 right-shifts the input REG_DATA by X and sets the result to SH_DATA (prefix and suffix data extraction step or prefix and suffix data extraction function).

Finally, in step S103, the bit adjustment / column index generator 91 calculates the column index COL_INDEX. Here, in this embodiment, SH_DATA is converted to a 32-bit address by shifting left by 2 bits.
The bit adjustment / column index generator 91 outputs this address as the column index COL_INDEX (column index calculation step or column index calculation function).

(About program example)
An example of a program of the decoding processing apparatus in this embodiment is shown in FIGS. FIG. 21 is a flowchart illustrating an example of a processing procedure for decoding TC and T1s of CAVLC. FIG. 22 shows an example of an assembler code for decoding TC and T1s of CAVLC.

As illustrated in FIG. 21, first, the processor performs a process of selecting any one row index table from among a plurality of types of row index tables corresponding to the type of NumVLC and updating the selected row index table. (Step S210).
Subsequently, the processor selects any one suffix length table from among a plurality of suffix length tables corresponding to the type of NumVLC, and performs a process of updating the selected suffix length table (step S220).
Further, the processor performs processing for initializing the variable-length code decoding device (decoding processing device) (step S230).

Next, the processor performs a process of determining whether or not the decoding process for all 4 × 4 blocks has been completed (step S240).
When the result of this determination process is “Yes”, the processor ends the process. On the other hand, if the result of this determination process is “No”, the processor advances the process to the next step S250.
That is, the processor performs a process of decoding TC and T1s in one 4 × 4 block (step S250).
Then, the processor performs other decoding processing in one 4 × 4 block (step S260). When the decoding process for one 4 × 4 block is completed, the processor returns to step S240, and repeats steps S240 to S260 to perform the decoding process for another 4 × 4 block.

Hereinafter, a more specific processing procedure of the flowchart shown in FIG. 21 will be described with reference to a program code example shown in FIG.
First, instructions used in FIG. 22 will be described.
“Load dp3 ++, r0;” in the first line of the program is a command that the processor accesses the memory using the register dp3 in which the address is stored, acquires the data, stores the acquired data in the register r0, This instruction advances the address stored in the register dp3 by 4 bytes.
Loop r3 is an instruction in which the processor repeats the processing described from the Loop instruction to the repetition end by the value stored in the register r3.
Note that the repetition end is described by an instruction Loop end.

As a premise of this example, a value for selecting a table by the processor is stored in r2.
In the register r3, the processor stores the number of repetitions, that is, the number of 4 × 4 blocks.
The processor stores the start address of the variable-length code bitstream in the register dp1.
In the register dp3, the processor stores an address of data in the memory indicating the update contents of the row index table.
In the register dp4, the processor stores an address of data indicating a position to be updated in the row index table.
In the register dp5, the processor stores an address of data indicating the update contents of the suffix table.
In the register dp6, the processor stores an address of data indicating a position where the suffix table is updated.

Explain the contents of the program.
First, the processor updates the raw index table (step S210). In the first and second instructions for updating, that is, in the first and second lines of the program shown in FIG.
In the instruction on the third line, the processor updates the row index using the UPD_ROW instruction (step S213).
In the instructions on the fourth and fifth lines, the processor reads the contents of the next row index table and the address indicating the update position from the memory (steps S214 and S215).

When the processor repeats these processes and the update of the row index table is completed, the processor next updates the suffix length table in the same processing procedure (step S220).
That is, in the 6th and 7th lines of the program, the processor reads the contents of the suffix length table and the address indicating the update position from the memory (steps S221 and S222).
In the instruction on the eighth line, the processor updates the suffix length using the UPD_SUF instruction (step S223).
In the instructions on the ninth and tenth lines, the processor reads the contents of the next suffix length table and the address indicating the update position from the memory (steps S224 and S225).
When the update of the suffix table is completed, the processor initializes the decoding processing device with the INITIALIZE instruction (step S230).

After initialization, the processor starts decoding.
In the decoding process, first, the processor declares that the instruction below the Loop is repeated by the value stored in the register r3, that is, the number of 4 × 4 blocks, using the Loop instruction shown in the 12th line of the program. (Step S240).
In the next instruction, the processor executes an instruction for decoding the variable length code, calculates a decoding address, and stores the result in the register dp2 (step S251).
Further, the processor loads data using the address stored in the register dp2, obtains TC and T1s from the memory, and stores them in the register r0 (step S252).

After that, the processor The other decoding process in H.264 is performed (step S260), and the repetition process is terminated by the Loop end instruction shown in the 15th line.
At this time, when the processor determines that the process is repeated for the value indicated by r3, the processor exits the loop and proceeds to the next process. On the other hand, if the processor determines that iterative processing has not been performed for the value indicated by r2, the processor returns to the top of the loop and repeats processing.

(About operation)
Next, the operation of the variable length code decoding processing apparatus of the present invention according to the DEC_CODE instruction will be described with reference to the timing chart of FIG. FIG. 23 shows the output of each unit at each clock of the variable-length code decoding processing apparatus operating in synchronization with the clock signal.

First, in the first clock (first period), the processor executes the decoding start instruction DEC_CODE of the variable-length code bitstream (step S11) (decoding start instruction execution processing step or decoding start instruction execution processing function).

In the second clock (second period), the bit buffer controller 61 of the bit storage 52 receives the instruction INST_CNTL from the IF stage, performs bit read processing, and outputs it from the bit buffer 62 to REG_DATA (step S12) (variable). Long code bit stream output processing step or variable length code bit stream output processing function).

In the third clock (third period), the prefix counter 71 of the control information / low index generator 53 counts the prefix included in REG_DATA (step S13) (prefix counting step or prefix counting function).

In the fourth clock (fourth period), the prefix address generator 72 of the control information / row index generator 53 receives an address referring to the row index table group 73 and the suffix length table group 74 with the prefix length as an input. Generate (step S14) (prefix address generation step or prefix address generation function).

In the fifth clock (fifth period), the acquisition unit 77 of the control information / row index generator 53 receives the address calculated by the prefix address generator 72 and a signal for selecting a table (table selection signal) as inputs. The row index corresponding to the prefix address is obtained by referring to the selected row index table (row index obtaining step or row index obtaining function).
At the same time, the acquisition unit 78 of the control information / row index generator 53 refers to the selected suffix length table to acquire the suffix length corresponding to the prefix address (suffix length acquisition step or suffix length acquisition function).

That is, the

acquisition units

77 and 78 of the control information / row index generator 53 acquire the row index and the suffix length at the same time (in parallel with the unit clock period) (step S15) (table information acquisition step or table information acquisition). function).

In the sixth clock (sixth period), the update instruction generator 75 of the control information / row index generator 53 receives the prefix length, suffix length, REG_DATA, and the output bit width output from the bit buffer controller 61. Then, an update instruction for updating the data in the bit buffer 62 is generated (step S16) (bit buffer update instruction generation step or bit buffer update instruction generation function). *

In the seventh clock (seventh period), the bit buffer controller 61 performs an update process on the bit buffer 62 with the update instruction generated from the update instruction generator 75 as an input, and the data in the bit buffer 62 is updated. (Bit buffer update processing step or bit buffer update processing function).
At the same time, the decoding address generator 54 generates a column index, adds the generated column index to the row index, and outputs it (step S17) (column index row index addition step or decoding address calculation step, or column index row). Index addition function or decoding address calculation function).
In this way, the process of generating the decoding address by the control information / row index generator 53 and the process of updating the variable length code bitstream held in the bit buffer 62 are performed simultaneously (in parallel with the unit clock period). )It can be carried out.

In the eighth clock (eighth period), the processor refers to the decoding table with the decoding address generated by the decoding address generator 54 as an input, and variable length encoded TC and T1s are decoded. (Step S18) (TC / T1s decoding processing step or TC / T1s decoding processing function).

Here, “the control information / decoding address generation control step” can be configured by the above steps S13 to S17. Further, the “control information / row index generation step” can be configured by the above steps S13 to S16. Furthermore, the “decoding address generation (output) step” can be configured by step S17. Further, the “bit storage processing step” can be constituted by step S12.

Other configurations, other steps or functions, and the effects thereof are the same as those in the above-described embodiment. In the above description, the operation content of each step described above, the components of each unit, and the functions thereof may be programmed and the program may be executed by a computer.

[Fourth Embodiment]
Next, a fourth embodiment according to the present invention will be described with reference to FIGS. Here, a more specific example of the second embodiment will be described as a fourth embodiment. Further, the description of the same configuration as in the first embodiment is omitted.

In the control information / row index generator 153 of this embodiment, as shown in FIG. 24, the row index table 173 consists of one table. Similarly, the suffix length table 174 consists of one table.
With this change, the signal SEL_TAB for selecting the table becomes unnecessary.
Further, as shown in FIG. 25, the signal SEL_TAB for selecting the table is not required for the output of the bit buffer controller 161 in the bit storage 152.

Here, FIG. 26 shows a DEC_CODE instruction defined in the present embodiment.
In the DEC_CODE instruction of the present embodiment, the part REG_NUM2 designating a register including a signal for selecting a table is erased from the configuration of the DEC_CODE instruction in the third embodiment, and a 0 value is stored instead. It has become.

Furthermore, UPD_ROW and UPD_SUF instructions defined in the second embodiment are shown in FIGS.
The UPD_ROW and UPD_SUF instructions of this embodiment are 16-bit instructions, an 8-bit operand OPCODE, a REGNUM1 that specifies a register that stores an address indicating a table update position, and a register that stores the contents to be updated And REGNUM2 indicating 2 and 0 of 2 bits.

(Example program)
An example of a program of the decoding processing apparatus in the present embodiment is shown in FIGS. FIG. 29 is a flowchart illustrating an example of a processing procedure for decoding TC and T1s of CAVLC. FIG. 30 shows an example of an assembler code for decoding TC and T1s of CAVLC.
The difference between this program and the program shown in the third embodiment is that it is not necessary to select any one of the plurality of row index tables. Further, it is not necessary to select any one suffix length table from among a plurality of types of suffix length tables.

As shown in FIG. 29, first, the processor performs a process of updating the row index table (step S310).
Subsequently, the processor performs a process of updating the suffix length table (step S320).
Further, the processor performs processing for initializing the variable-length code decoding device (decoding processing device) (step S330).

Next, the processor performs a process of determining whether or not the decoding process for all 4 × 4 blocks has been completed (step S340).
When the result of this determination process is “Yes”, the processor ends the process. On the other hand, if the result of this determination process is “No”, the processor advances the process to the next step S350.
That is, the processor performs a process of decoding TC and T1s in one 4 × 4 block (step S350).
Then, the processor performs other decoding processing in one 4 × 4 block (step S360). When the decoding process for one 4 × 4 block is completed, the processor returns to step S340, and repeats steps S340 to S360 to perform the decoding process for another 4 × 4 block.

Hereinafter, a more specific processing procedure of the flowchart shown in FIG. 29 will be described with reference to a program code example shown in FIG.
In this example, as a premise, the processor stores the number of repetitions, that is, the number of 4 × 4 blocks, in the register r3.
The processor stores the start address of the variable-length code bitstream in the register dp1.
In the register dp3, the processor stores an address of data in the memory indicating the update contents of the row index table.
In the register dp4, the processor stores an address of data indicating a position to be updated in the row index table.
In the register dp5, the processor stores an address of data indicating the update contents of the suffix table.
In the register dp6, the processor stores an address of data indicating a position where the suffix table is updated.

The difference between this program and the program shown in the third embodiment will be described.
First, for the UPD_ROW and UPD_SUF instructions that update the row index table, the suffix length table, the registers specified by the instructions are two registers that store the update position and the value used for the update (step S313, step S323). .
Similarly, the decoding instruction DEC_CODE is obtained by removing the signal for selecting a table from the DEC_CODE instruction of the third embodiment (step S351).
The other steps S311, S312, S314, S315, S321, S322, S324, S325, S330, S340, S352, and S360 are the same as S211, S212, S214, S215, S221, S222, S224, and the like in the third embodiment. This is the same as S225, S230, S240, S252, and S260.

[Other variations]
Also, although the apparatus and method according to the present invention have been described according to some specific embodiments thereof, the embodiments described in the text of the present invention can be used without departing from the spirit and scope of the present invention. Various modifications are possible.

Here, other embodiments will be described.
(Modification 1)
First, with regard to prefix counting, in the third and fourth embodiments, a prefix counter is provided in the control information / row index generator, and counting is performed using this, but the bit buffer controller performs this. You can also.

That is, as shown in FIG. 31, the bit buffer controller 261 of the bit storage 252 has a prefix counting function (prefix counting unit) in addition to the bit replenishment function and the update processing function.
In this case, the prefix length of the bit data stored in the bit buffer 262 is counted in advance by the bit buffer controller 261, and the bit data is read from the bit buffer 262 by execution of the decoding processing instruction ( For example, 4 bits) are output.

In this configuration, as shown in FIG. 32, the control information / low index generator 253 does not require a prefix counter.
In addition, the control information / row index generator 253 may have a three-stage pipeline configuration, and may include only the generator pipeline registers 281B and 281C.
The prefix address generator 272, the row index table group 273, the suffix length table group 274, the acquisition unit 277, the acquisition unit 278, the adder 276, and the update instruction generator 275, which are other configurations, are the same as those in the above embodiment. It has become.

(Modification 2)
Furthermore, it is possible to refer to the table using the counted prefix length as it is. In the case of this configuration, as shown in FIG. 33, the control information / row index generator 353 does not require a prefix address generator.

The acquisition unit 377 of the control information / row index generator 353 acquires the corresponding row index from the selected table in the row index table group 373 based on the prefix length.
Further, the acquisition unit 378 of the control information / row index generator 353 acquires the corresponding suffix length from the selected table in the suffix length table group 374 based on the prefix length.
The adder 376 and the update instruction generator 375 which are other configurations are the same as those in the above embodiment.

Further, in this case, as shown in FIG. 34, the period for generating the prefix address (step S14 in FIG. 22) is also unnecessary, and S11, S12, S13, S15, S16, S17, and the like in the third embodiment. S21, S22, S23, S25, S26, S27, and S28, which are the same as S18, are sufficient.

(Modification 3)
Furthermore, the address generation for decoding, which has been performed by the address generator for decoding, can be performed simultaneously with the generation of the fourth pipeline stage of the control information / row index generator, that is, the update instruction.
In this case, as shown in FIG. 35, the decoding address generator 453 can be mounted in the control information / row index generator 453.
Other configurations are a prefix counter 471, a prefix address generator 472, a row index table group 473, a suffix length table group 474, an acquisition unit 477, an acquisition unit 478, an adder 476, an update instruction generator 475, and a generator pipeline. The

registers

481A, 481B, 481C are the same as those in the above embodiment.

(Modification 4)
The processing of each unit in the decoding processing apparatus having the above-described configuration can also be realized as a method, and various processing procedures as the decoding processing method will be described with reference to FIG. FIG. 36 is a flowchart illustrating an example of a processing procedure in the decoding processing device according to another embodiment of the present invention.

The decoding processing method according to the present embodiment is intended for a method in which a computer (for example, a processor or the like) performs processing for decoding a variable-length code bitstream that is an encoded data sequence including at least a prefix and a suffix that follows the prefix. It is what.
In this decoding processing method, for example, it can also be said to be an example of a detailed processing procedure of step S251 in FIG. 22 of the above-described embodiment.

In this decoding processing method, as a basic procedure, first, the computer performs first control for performing input / output processing for temporarily storing a part of the variable-length code bitstream in the bitstream temporary storage unit (for example, The bit storage control step of step S401 shown in FIG. 36).
That is, the computer performs a process of temporarily holding a part of the variable-length code bitstream in the bitstream temporary holding unit.
Next, after the computer generates a row index for obtaining the decoding address based on the prefix of the variable-length code bitstream, generates a suffix length corresponding to the prefix length, and generates these First generation control for generating the control information is performed (for example, the control information / raw index generation step in step S402 shown in FIG. 36).
Subsequently, the computer generates a column index for obtaining the decoding address from the suffix length, and performs second generation control for generating the decoding address based on the column index and the row index ( For example, a decoding address generation step in step S403 shown in FIG. 36).

Here, in the control information / row index generation step (when the first generation control is performed), a process of generating a decoding address in the second generation control after the generation of the row index and the suffix length And the process of updating the variable-length code bit stream in the first control can be executed simultaneously (in parallel with the unit clock period).

<Control information / raw index generation step>
An example of the detailed processing procedure of the control information / row index generation step S402 shown in FIG. 36 is shown in FIG. FIG. 37 is a flowchart illustrating an example of a processing procedure in the decoding processing device according to another embodiment of the present invention.

First, a first table storing a row index corresponding to the prefix length and a second table storing a suffix length corresponding to the prefix length are provided.
Then, the computer counts the prefix length of the previous variable-length code bitstream (step S501) (prefix counting step or prefix counting function).

Subsequently, the computer calculates a prefix address for referring to the first table and the second table from the prefix length counted in the prefix counting step of the previous step S501 (step S502) (prefix address calculating step) Or prefix address calculation function). *

Next, the computer refers to the first table and the second table, respectively, using the prefix address obtained in the prefix address calculation step of the previous step S502, and determines the corresponding row index and suffix length. Obtain (step S503) (table information obtaining step or table information obtaining function).

Further, the computer stores the bit length of the bit storage control means based on the suffix length acquired in the table information acquisition step in the previous step S503, the prefix length counted in the prefix counting step in the step S501, and REG_DATA. An update command that is control information for updating the variable-length code bitstream is generated (step S504) (update command generation step or update command generation function).

<Decryption address generation step>
FIG. 38 shows an example of the detailed processing procedure of the decryption address generation step S403 shown in FIG. FIG. 38 is a flowchart illustrating an example of a processing procedure in the decoding processing device according to another embodiment of the present invention.

First, the computer generates a column index for obtaining the decoding address based on the prefix length, the suffix length, the number of bits of the variable length code bit stream of the bit storage control means, and the bit stream ( Step S601) (column index generation step or column index generation function).
In this specific example, the processing shown in FIG. 5 of the above embodiment is performed.

Then, the computer adds the column index in the previous step S601 and the row index in step S503 to generate a decoding address (step S602) (column index row index addition step or column index row index addition function) ).

On the other hand, in parallel (simultaneously) with these steps S601 and S602, the computer executes a process of updating the variable length code bitstream of the bit storage control means based on the update command in step S504 (step S504). S603) (bit storage update processing step or bit storage update processing function).

Here, the “second control step” can be configured by the above steps S402 and S403.
In this “second control step”, the computer uses the decoding table reference necessary for decoding based on the prefix and the suffix of the variable-length code bitstream input from the bitstream temporary storage unit. While generating a decoding address, second control for supplying control information for updating the variable-length code bitstream to the bitstream temporary storage unit can be performed.
In addition, when performing the second control, the process of generating the decoding address and the process of updating the variable length code bitstream of the bitstream temporary storage unit can be performed simultaneously.

(Modification 5)
In the above-described embodiment, the configuration example in which the decoding processing device is mounted on the processor has been shown. However, as shown in FIG. 39, a configuration by the decoding processing device alone is also possible.
That is, the decoding processing device 550 temporarily holds a part of the variable-length code bitstream and also controls first input / output processing for holding the first control means (for example, a bit storage unit 552 shown in FIG. 39). And the like, and a decoding address used for reference to a decoding table necessary for decoding, based on the prefix and the suffix of the variable-length code bitstream input from the first control unit, and Second control means (for example, reference numeral 551 shown in FIG. 39) for supplying control information for updating the variable-length code bitstream to the first control means is adopted.
The second control unit 551 simultaneously performs the process of generating the decoding address and the process of updating the variable length code bitstream held in the first control unit (for example, in parallel with a unit clock period). Can do).

In the decoding processing apparatus having such a configuration, the decoding address generation process based on the prefix and the suffix and the update process of the first control unit can be performed simultaneously, and the variable length code can be prepared for the next decoding. The number of cycles required for decoding can be reduced.

The second control unit 551 generates a raw index for obtaining the decoding address based on the prefix of the variable-length code bitstream, and generates a suffix length corresponding to the prefix length. And a control information / row index generator 553 (first generation control unit) for controlling the processing operation for generating the control information after generating the column information, and generating a column index for obtaining the decoding address from the suffix length And a decoding address generator 554 (second generation control unit) for controlling a processing operation for generating the decoding address based on the column index and the row index.

In this case, the control information / row index generator 553 generates the decoding address after generating the row index and the suffix length, and the variable length code bit held in the first control means. The process of updating the stream can be performed simultaneously (for example, in parallel with the unit clock period).

(Modification 6)
Furthermore, the decoding processing device and the processor in the above-described embodiment can be configured separately.
In this case, as shown in FIG. 40, the processor control unit 625 in the processor 620 includes a decoding start instruction (DEC_CODE) generation function 625a, a bit buffer update instruction (INST_UPD) generation function 625b, and a bit supplement instruction (MEM_LOAD) generation function 625c. , A row index table update instruction (UPD_ROW) generation function 625d, a suffix length table update instruction (UPD_SUF) generation function 625e, an initialization instruction (INITIALIZE) generation function, and the like.

Similarly to the above-described embodiment, the decoding processing device 650 includes a bit storage 652 (first control means), a control information / row index generator 653 (first generation control unit), and a decoding address generator 654 ( A second generation control unit). The control information / row index generator 653 and the decoding address generator 654 can constitute the second control means 651. The decoding processing device 650 starts the decoding process when the decoding start instruction (DEC_CODE) of the processor 620 is input to the bit storage 652. Also, when the decryption processing device 650 executes various processes based on other various instructions of the processor 620, the process can be performed in the same manner as in the above embodiment.

Here, for example, a part of each block in the block diagram shown in FIG. 39 has a software module configuration showing a state functionalized by a computer by executing various programs stored in an appropriate memory. There may be.

That is, although the physical configuration is, for example, one or a plurality of CPUs (or one or a plurality of CPUs and one or a plurality of memories), the configuration shown in FIG. 39 is realized on software by causing the CPU to execute a program. You may do it.

The description of each unit (means) described above can be interpreted as a computer functionalized by a program together with the functions of the program, or a plurality of functions permanently functioning by specific hardware. It can also be interpreted that the device comprising the electronic circuit block is described. Therefore, these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one.

Further, each unit may be configured as a device including a dedicated computer capable of communication, and the system may be configured by each of these devices. Conversely, a system in which each unit is configured as a single device may be used.

Furthermore, when each part is configured as a circuit, it may be configured by various integrated circuits such as a semiconductor integrated circuit, an optical integrated circuit, or a combination thereof.

In a processor according to an embodiment of the present invention, a bit storage unit having means for holding and controlling a part of a bit stream, and a variable length code according to a bit stream prefix using the bit stream as an input A control information / row index generator having means for generating an address used for table reference necessary for decoding, that is, a row index and a suffix length corresponding to the prefix length, and generating information for controlling the bit storage And a decoding address generator having means for generating an address referring to a table necessary for decoding from the prefix length and the suffix.

The bit storage device reads bit data of a predetermined number of bits from the held bit stream, and when the remaining number of bits after the reading is small, newly reads data from the memory, and a part of the held bit stream And a means for updating the stored bit stream based on information for controlling the bit storage.

The control information / row index generator stores an address used for table reference necessary for decoding of a variable length code corresponding to a prefix length, that is, a table storing a row index and a suffix length corresponding to the prefix length. A table, and means for counting the prefix of the bitstream read from the bit storage, means for calculating the address of the table from the counted prefix, and using the address obtained from the prefix length, Means for obtaining the row index and suffix length by referring to the table storing the row index and the table storing the suffix length; and means for generating control information for updating the bit storage unit from the prefix length and the suffix length Have Sea urchin may be configured.

The decoding address generator obtains a suffix of data read from the bit storage and calculates an address used for table reference necessary for decoding a variable length code calculated from the suffix, that is, a column index. And means for adding the row index and the column index.

Furthermore, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to a suitable number, position, shape, and the like in practicing the present invention.
That is, in the above-described embodiment, the case where one decoding processor is provided in one processor has been described, but the present invention does not limit the number of these devices. For example, a configuration in which one decoding processing device is processed by a plurality of processors or a configuration in which a plurality of decoding processing devices are processed by one processor may be employed.
Furthermore, although a pipeline processor is used in the case of one processor, a processor other than the pipeline processor may be used in the case of a plurality of processors.
Further, the pipeline processor may be any of the case where there is no parallel processing and the case where there is parallel processing with a parallel degree k (superscaler).

In the above embodiment, the case where the decoding process is performed in units of 4 × 4 block sizes has been described as an example. However, the decoding process may be performed in units of other various block sizes.
For example, H.M. It may be a 2 × 2 size block used in H.264. In the decoding process of the 2 × 2 size block, decoding is performed using the NumVLC table for 2 × 2 size, and the decoding process of the 4 × 4 size block is performed except for the number of repetitions necessary for decoding the block coefficient. The processing is equivalent.
Furthermore, if the encoding process conforms to the CAVLC method, the method of the above embodiment can be used regardless of the block size.

In addition, examples of the electronic device including a decoder on which the processor as described above is mounted include a digital moving image reproducing device such as an HDD recorder and a DVD player, and other various communication devices. In addition, it may be mounted on any computer such as a desktop, laptop computer, other information device having wireless / wired communication function, information home appliance (TV / portable music player / game machine), or similar computer.・ Any fixed type.
Various communication devices are not limited to personal computers, but various servers, EWS (engineering workstations), medium-sized computers, mainframes, portable information terminals, various mobile terminals, PDAs, mobile phones, wearable information terminals, various televisions, It may be a DVD recorder, various audio devices, a home appliance equipped with various information communication functions, a game device having a network function, or the like.

(Decryption processing program)
In addition, the decoding processing program of the present invention that realizes the functions of the above-described embodiments is a program corresponding to the processing unit (processing means), functions, and the like shown in the various block diagrams in each of the above-described embodiments, and a flowchart. Programs corresponding to the processing procedures, processing means, functions, etc. shown in the above, each processing program processed in a program using various tables, etc., a method (step) generally described in this specification, Includes the described process, the whole data or each part.

Specifically, in the decoding processing program according to the embodiment of the present invention, a computer that performs processing for decoding a variable-length code bitstream that is an encoded data sequence including at least a prefix and a suffix that follows the prefix has various functions. Can be realized.

The decoding processing program includes a first control function for performing input / output processing for temporarily holding a part of the variable length code bitstream in the bitstream temporary holding unit, and the bitstream temporary holding unit Based on the prefix and the suffix of the variable-length code bitstream, a decoding address used for referring to a decoding table necessary for decoding is generated, and the variable-length code bitstream of the bitstream temporary storage unit is updated A function including a second control function (control information / decoding address generation control function) for generating control information can be realized by the computer.

In this case, in the second control function (control information / decoding address generation control function), a process of generating the decoding address, and a process of updating the variable-length code bitstream of the bitstream temporary storage unit The computer can realize the function of performing the above simultaneously or sequentially.

In the control information / decoding address generation control function, the decoding processing program generates a raw index for obtaining the decoding address based on the prefix of the variable-length code bitstream, and also adds a prefix length. A column for generating a control information / row index generation function (first generation control function) for generating the control information after generating the suffix length corresponding to, and for determining the decoding address from the suffix length A function including a decoding address generation function (second generation control function) for controlling a processing operation for generating an index and generating the decoding address based on the column index and the row index is realized in the computer. Can be made.

In this case, the control information / row index generation function (first generation control function) outputs the decoding address after the generation of the row index and the suffix length, and the bitstream temporary storage unit It is possible to cause the computer to realize a control function for simultaneously or sequentially performing processing for updating the variable-length code bitstream.

Furthermore, in this decryption processing program, a first table storing a row index corresponding to the prefix length and a second table storing a suffix length corresponding to the prefix length can be provided.

In this case, in the decoding processing program, in the control information / low index generation function (first generation control function), a prefix counting function for counting the prefix length of the variable-length code bitstream, and the prefix counting function The prefix address calculation function for calculating a prefix address for referring to the first table and the second table from the prefix length counted in the above, and the prefix address obtained by the prefix address calculation function, A table information acquisition function that refers to each of the one table and the second table and acquires the corresponding row index and the suffix length; and the suffix length and the prefix meter acquired by the table information acquisition function Based on said prefix length counted in function, the function including the update instruction generating function for generating an update command is control information for the update can be achieved in the computer. *

The program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language as required. In any case, the language may be a compiler type or an interpreter type, regardless of the form of the program.

As a method of supplying the program, it is also possible to provide the program from an external device that is communicably connected to the computer via a telecommunication line (whether wired or wireless).

According to the decoding processing program of the present invention, if the decoding processing program is read from a storage medium such as a ROM storing the decoding processing program into a computer (CPU) and executed, or the decoding processing program is communicated If it is executed after being downloaded to a computer via the means, the above-described apparatus according to the present invention can be realized relatively easily. When the software of the apparatus is embodied as an embodiment of the idea of the invention, it naturally exists and is used on a storage medium storing such software.

In addition, the program does not have any problem regarding the replication stage such as the primary replica and the secondary replica. If the program is supplied using a communication line, the communication line becomes a transmission medium and the present invention is used. Furthermore, the dependent claims in the apparatus may be configured to correspond to the dependent claims in the method and the program.

(Information recording medium)
Moreover, the structure which recorded the above-mentioned program on the information recording medium may be sufficient. The information recording medium stores an application program including the above-described program, and the computer can read the application program from the information recording medium and install the application program on the hard disk. Thus, the program can be provided by being recorded on an information recording medium such as a magnetic recording medium, an optical recording medium, or a ROM. Use of an information recording medium in which such a program is recorded in a computer constitutes a convenient information processing apparatus.

As an information recording medium for supplying the program, for example, ROM, RAM, semiconductor memory such as flash memory and SRAM, and an integrated circuit, or a USB memory, memory card, optical disk, magneto-optical disk, magnetic recording medium and the like including them. Furthermore, flexible disk, CD-ROM, CD-R, CD-RW, FD, DVDROM, HDDVD (HDDVD-R-SL <single layer>, HDDVD-R-DL <double layer>, HDDVD-RW) -SL, HDDVD-RW-DL, HDDVD-RAM-SL), DVD ± R-SL, DVD ± R-DL, DVD ± RW-SL, DVD ± RW-DL, DVD-RAM, Blu-Ray Disk <registration Trademarks> (BD-R-SL, BD-R-DL, BD-RE-SL, BD-RE-DL), O, ZIP, magnetic card, magnetic tape, SD card, memory stick, non-volatile memory card, IC card, and other portable media, recording devices such as hard disks built into computer systems, etc. May be used.

Furthermore, the “information recording medium” is a medium that dynamically holds a program for a short time (transmission medium), such as a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. Or a transmission wave), a volatile memory inside a computer system serving as a server or a client in that case, and those holding a program for a certain period of time.

Further, the processor and the decoding processing device of the above-described embodiment may be configured as a system. This “system” may be integrated with other “systems”, and the entire system may be configured as the “system” of the present invention.

In this case, the “system” refers to a logical collection of a plurality of devices, and it does not matter whether the devices of each configuration are in the same housing. In such a case, the present invention may be applied to a system composed of a plurality of devices, or may be applied to an apparatus composed of one device.

Further, in the present specification, the steps shown in the flowchart include processes that are executed in parallel or individually even if they are not necessarily processed in time series, as well as processes that are executed in time series according to the described procedure. It is a waste. In the implementation, the order in which the program procedures (steps) are executed can be changed. Further, certain procedures (steps) described herein can be implemented, removed, added, or rearranged as a combined procedure (step) as needed for implementation.

Furthermore, the functions of the program such as each means of the apparatus, each function, and the procedure function of each step may be achieved by dedicated hardware (for example, a dedicated semiconductor circuit, etc.). Some of the functions may be processed by hardware, and other functions among all functions may be processed by software. In the case of dedicated hardware, each unit may be formed by an integrated circuit such as an LSI. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them. The LSI may include other functional blocks. Further, the method of circuit integration is not limited to LSI, and implementation with a dedicated circuit or a general-purpose processor is also possible. Further, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using this technology.

Further, the method for controlling the process of outputting the decoding address and the process of updating the variable-length code bitstream of the bit storage control means to be performed simultaneously is not necessarily limited to a substantial apparatus. It can be easily understood that this also functions as a method. For this reason, the invention relating to the method is not necessarily limited to a substantial apparatus, and there is no difference that the method is also effective. In this case, a decoding processing device, a processor, and the like can be included as an example for realizing the method.

By the way, such a decoding processing device and processor may exist alone, or are incorporated in a certain device (for example, a processor including the decoding processing device is incorporated as a function of a decoder or an electronic device). The idea of the invention is not limited to this and includes various aspects. Therefore, it can be changed as appropriate, such as software or hardware. When the software of the apparatus is embodied as an embodiment of the idea of the invention, it naturally exists on the storage medium storing the software and is used.

Furthermore, it may be a case where a part is software and a part is realized by hardware, and a part is stored on a storage medium and is read as needed. It may be as a thing. When the present invention is implemented by software, a configuration using hardware or an operating system may be used, or may be implemented separately from these.

The scope of the invention is not limited to the illustrated example.
Further, the above embodiments include various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. That is, examples include combinations of the above-described embodiments, or any of them and any of the modifications. In this case, even if not specifically described in the present embodiment, the obvious effects from the respective configurations disclosed in the embodiments and their modifications are naturally included as the effects of the embodiments. it can. On the contrary, the configuration capable of exhibiting all the effects described in the present embodiment is not necessarily an essential component of the essential features of the present invention. In addition, an embodiment based on a configuration in which some of the configuration requirements are deleted from all the configuration requirements shown in the embodiment, and a technical scope based on the configuration may be an invention.

In addition, the description so far including each of the embodiments and the modifications thereof is intended to facilitate the understanding of the present invention. The embodiments of the invention are merely shown as examples of implementation, are illustrative, not limiting, and can be modified and / or modified as appropriate. The present invention can be implemented in various forms based on its technical idea or its main features, and the technical scope of the present invention should not be construed in a limited manner by each embodiment and its modifications. It will not be.
Therefore, each element disclosed above is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

This application claims priority based on Japanese Patent Application No. 2008-163161 filed on June 23, 2008, the entire disclosure of which is incorporated herein.

The present invention can be applied to all decoding processing apparatuses, and more specifically, can be applied to applications such as a processor such as a digital video reproducing apparatus.

It is a block diagram which shows an example of the whole structure of the processor provided with the decoding processing apparatus in the 1st Embodiment of this invention. It is a block diagram which shows an example of a detailed structure of the bit storage in the decoding processing apparatus of the 1st Embodiment of this invention. It is a block diagram which shows an example of the detailed structure of the control information and raw index generator in the decoding processing apparatus of the 1st Embodiment of this invention. It is a block diagram which shows an example of a detailed structure of the address generator in the decoding processing apparatus of the 1st Embodiment of this invention. It is a flowchart which shows an example of the processing operation of the bit adjustment and the column index generator in the decoding processing apparatus of the 1st Embodiment of this invention. It is a block diagram which shows an example of the control information and raw index generator in the decoding processing apparatus of the 2nd Embodiment of this invention. It is a block diagram which shows an example of a detailed structure of the bit storage in the decoding processing apparatus of the 2nd Embodiment of this invention. It is a block diagram which shows an example of a detailed structure of the bit storage in the decoding processing apparatus of the 3rd Embodiment of this invention. It is a block diagram which shows an example of the detailed structure of the control information and raw index generator in the decoding processing apparatus of the 3rd Embodiment of this invention. It is a block diagram which shows an example of a detailed structure of the address generator in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the content of INST_UPD (update command) in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the content of DEC_CODE which is one of the instructions added in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the content of INITIALIZE which is one of the instructions added in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the content of MEM_LOAD in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the outline | summary of the bit supplement process of the bit buffer in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the process outline | summary of the prefix counter in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the row index table in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the suffix length table in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the content of the instruction | indication which updates a row index table in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the content of the command which updates the suffix length table in the decoding processing apparatus of the 3rd Embodiment of this invention. It is a flowchart which shows an example of the whole process sequence of the decoding process of the variable-length code in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the whole process sequence of the decoding process of the variable-length code in the decoding processing apparatus of the 3rd Embodiment of this invention. It is a timing chart which shows an example of the detailed procedure of the operation | movement in the decoding processing apparatus of the 3rd Embodiment of this invention. It is a block diagram which shows an example of the detailed structure of the control information and raw index generator in the decoding processing apparatus of the 3rd Embodiment of this invention. It is a block diagram which shows an example of a detailed structure of the bit storage in the decoding processing apparatus of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the command added in the decoding processing apparatus of the 4th Embodiment of this invention. It is explanatory drawing which shows an example of the content of the command which updates a row index table in the decoding processing apparatus of the 4th Embodiment of this invention. It is explanatory drawing which shows an example of the content of the command which updates the suffix length table in the decoding processing apparatus of the 4th Embodiment of this invention. It is explanatory drawing which shows an example of the whole process sequence of the decoding process of the variable-length code in the decoding processing apparatus of the 4th Embodiment of this invention. It is explanatory drawing which shows an example of the whole process sequence of the decoding process of the variable-length code in the decoding processing apparatus of the 4th Embodiment of this invention. It is a block diagram which shows an example of a detailed structure of the bit storage in the decoding processing apparatus of other embodiment of this invention. It is a block diagram which shows an example of the detailed structure of the control information and raw index generator in the decoding processing apparatus of other embodiment of this invention. It is a block diagram which shows an example of the detailed structure of the control information and raw index generator in the decoding processing apparatus of other embodiment of this invention. It is a timing chart which shows an example of the detailed procedure of the operation | movement in the decoding processing apparatus of other embodiment of this invention. It is a block diagram which shows an example of the detailed structure of the control information and raw index generator in the decoding processing apparatus of other embodiment of this invention. It is a flowchart which shows an example of the process sequence in the decoding processing apparatus of other embodiment of this invention. It is a flowchart which shows an example of the process sequence in the decoding processing apparatus of other embodiment of this invention. It is a flowchart which shows an example of the process sequence in the decoding processing apparatus of other embodiment of this invention. It is a block diagram which shows an example of a structure of the decoding processing apparatus of other embodiment of this invention. It is a block diagram which shows an example of a structure of the processor provided with the decoding processing apparatus of other embodiment of this invention. H. It is explanatory drawing which shows an example of H.264 NumVLC0 table. It is explanatory drawing which shows an example of the table used when decoding TC of related technology, and T1s. H. It is explanatory drawing which shows an example of H.264 NumVLC1 table. It is explanatory drawing which shows an example of the table used when decoding TC of related technology, and T1s. H. It is explanatory drawing which shows an example of H.264 NumVLC2 table. It is explanatory drawing which shows an example of the table used when decoding TC of related technology, and T1s. It is a block diagram which shows an example of a structure of the processor provided with the processing apparatus of related technology. It is a timing chart which shows an example of the decoding process of TC and T1s when the processor provided with the processing apparatus of related technology is used.

DESCRIPTION OF SYMBOLS 10 Memory 20 Processor 50 Decoding processing apparatus 51 2nd control means 52 Bit storage (1st control means)
53 Control Information / Row Index Generator (First Generation Control Unit)
54 Decoding Address Generator (Second Generation Control Unit)
55 Pipeline Register for Generator 61 Bit Buffer Controller (Bit Control Unit)
62-bit buffer (bitstream temporary storage)
71 Prefix counter (prefix counter)
72 Prefix Address Generator (Prefix Address Calculator)
73 Row index table (first table) group 74 Suffix length table (second table) group 75 Update instruction generator (update instruction generation unit)
76 Adder (adder)
77, 78 Acquisition unit (table information acquisition unit)
91 bit adjustment / column index generator (column index generator)
92 Adder (adder)

Claims

A decoding processing device that performs a process of decoding a variable-length code bitstream that is an encoded data string including at least a prefix and a suffix following the prefix,
A first control means for temporarily holding a part of the variable-length code bitstream and controlling an input / output process for holding;
Based on the prefix and the suffix of the variable length code bitstream input from the first control means, a decoding address used for reference to a decoding table necessary for decoding is generated, and the first control is performed. Second control means for supplying control information for updating said variable length code bitstream to said means;
Including
The second control means comprises:
The decoding processing apparatus characterized by performing the process which produces | generates the said address for a decoding, and the process which updates the said variable length code bit stream hold | maintained at a said 1st control means.
The decoding processing device according to claim 1,
The second control means includes
Based on the prefix of the variable-length code bitstream, a row index for obtaining the decoding address is generated, a suffix length corresponding to the prefix length is generated, and after generating these, the control information is generated A first generation control unit;
A second generation control unit that generates a column index for obtaining the decoding address from the suffix length, and generates the decoding address based on the column index and the row index;
Including
The first generation control unit
After the generation of the row index and the suffix length, a process of generating a decoding address in the second generation control unit and a process of updating the variable length code bitstream in the first control unit are executed. A decoding processing device characterized by the above.
The decoding processing device according to claim 1,
The first control means includes
A bitstream temporary storage unit for temporarily storing the variable length code bitstream;
A bit control unit that performs processing to input and output the variable-length code bitstream in the bitstream temporary storage unit;
Including
The bit control unit
Read the bit data of a predetermined number of bits from the variable length code bit stream held in the bit stream temporary holding unit, and when the remaining number of bits after reading is small, the variable length code holding new data The ability to concatenate and store at the end of part of the bitstream;
A function of performing processing for updating the variable-length code bitstream held based on an update command that is the control information to be updated;
A decryption processing apparatus.
The decoding processing apparatus according to claim 2, wherein
The first generation control unit includes:
A first table storing a row index according to the prefix length;
A second table storing a suffix length corresponding to the prefix length;
A table information acquisition unit that refers to each of the first table and the second table using the prefix length and acquires the corresponding row index and the suffix length;
Including
The decoding processing device, wherein the table information acquisition unit acquires the row index and the suffix length.
The decoding processing apparatus according to claim 2, wherein
The first generation control unit includes:
A first table storing a row index according to the prefix length;
A second table storing a suffix length corresponding to the prefix length;
A prefix counting unit that counts the prefix length of the variable-length code bit stream read from the first control means;
A prefix address calculation unit for calculating a prefix address for referring to the first table and the second table from the prefix length counted by the prefix counting unit;
A table information acquisition unit that refers to each of the first table and the second table using the prefix address obtained by the prefix address calculation unit, and acquires the corresponding row index and the suffix length;
Based on the suffix length acquired by the table information acquisition unit, the prefix length counted by the prefix counting unit, and the variable-length code bitstream read from the first control unit, An update command generation unit for generating an update command which is the control information to be updated;
A decryption processing apparatus.
The decoding processing apparatus according to claim 2, wherein
The second generation control unit
A column index generator for generating the column index based on the suffix length;
An adder for adding the column index and the row index;
A decryption processing apparatus.
The decryption processing device according to claim 3,
The bit control unit
A decoding processing apparatus comprising: a prefix counting unit that counts the prefix length of the variable-length code bitstream.
The decoding processing device according to claim 5, wherein
The first table and the second table are:
Each having a plurality of tables according to the type of NumVLC table for decoding in the context-adaptive variable-length coding scheme;
The first control means comprises:
Generating table selection control information for selecting the type and supplying it to the first generation control unit;
The table information acquisition unit
Based on the table selection control information, one of the plurality of tables in the first table is selected and one of the plurality of tables in the second table is selected. A decoding processing device characterized by:
A processor capable of executing a pipeline process equipped with a decoding processing device that performs a process of decoding a variable-length code bitstream that is an encoded data sequence including at least a prefix and a suffix following the prefix;
A first control means for temporarily holding a part of the variable-length code bitstream and controlling an input / output process for holding at a register stage in processor pipeline processing;
A decoding address used for referring to a decoding table necessary for decoding based on the prefix and the suffix of the variable-length code bitstream input from the first control means in the execution stage in the processor pipeline processing And second control means for generating control information for updating the variable length code bitstream to the first control means,
Including
The second control means comprises:
A processor characterized by performing a process of generating the decoding address and a process of updating the variable length code bitstream of the first control means.
The processor of claim 9, wherein
The second control means includes
In the execution stage in the processor pipeline processing, based on the prefix of the variable-length code bitstream, a row index for obtaining the decoding address is generated, and a suffix length corresponding to the prefix length is generated, A first generation control unit that generates the control information after generating
Second generation for generating a column index for obtaining the decoding address from the suffix length in the execution stage in the processor pipeline processing, and generating the decoding address based on the column index and the row index A control unit;
Including
The first generation control unit
After the generation of the row index and the suffix length, a process of generating a decoding address in the second generation control unit and a process of updating the variable length code bitstream in the first control unit are executed. Processor.
The processor of claim 10, wherein
The first generation control unit includes:
A first table storing a row index according to the prefix length;
A second table storing a suffix length corresponding to the prefix length;
Prefix count for counting the prefix length of the variable-length code bit stream read from the first control means in the execution stage in the processor pipeline processing and in the first stage in the index generation pipeline processing And
A prefix address calculation unit that calculates a prefix address for referring to the first table and the second table from the prefix length counted by the prefix counting unit in a second stage in the index generation pipeline processing;
In the third stage of the index generation pipeline process, the first address and the second table are respectively referred to using the prefix address obtained by the prefix address calculation unit, and the corresponding row index A table information acquisition unit for acquiring the suffix length;
In the fourth stage of the index generation pipeline process, the suffix length acquired by the table information acquisition unit, the prefix length counted by the prefix counting unit, and the first control unit are read. An update command generation unit that generates an update command that is the control information to be updated based on the variable-length code bitstream;
A processor comprising:
An electronic device comprising the processor according to any one of claims 9 to 11.
A decoding processing method for performing a process of decoding a variable length code bitstream that is an encoded data string including at least a prefix and a suffix following the prefix,
A first control for performing input / output processing for temporarily storing a part of the variable-length code bitstream in the bitstream temporary storage unit;
Subsequently, based on the prefix and the suffix of the variable length code bitstream input from the bitstream temporary storage unit, a decoding address used for decoding table reference necessary for decoding is generated, and the bit A second control for supplying control information for updating the variable-length code bitstream to the stream temporary storage unit;
When performing the second control,
The decoding processing method characterized by performing the process which produces | generates the said address for a decoding, and the process which updates the said variable length code bit stream of the said bit stream temporary holding part.
The decoding processing method according to claim 13,
When performing the second control,
Based on the prefix of the variable-length code bitstream, a row index for obtaining the decoding address is generated, a suffix length corresponding to the prefix length is generated, and after generating these, the control information is generated The first generation control,
Subsequently, a column index for obtaining the decoding address from the suffix length is generated, and second generation control for generating the decoding address based on the column index and the row index is performed.
When performing the first generation control,
After the generation of the row index and the suffix length, a process of generating a decoding address in the second generation control and a process of updating the variable-length code bitstream in the first control are executed. Decoding processing method.
The decoding processing method according to claim 14, wherein
A first table storing a row index corresponding to the prefix length, and a second table storing a suffix length corresponding to the prefix length;
When performing the first generation control,
Counting the prefix length of the variable length code bitstream;
Subsequently, a prefix address for referring to the first table and the second table is calculated from the counted prefix length,
Next, the corresponding row index and the suffix length are obtained by referring to the first table and the second table, respectively, using the calculated prefix address,
Thereafter, an update command that is the control information to be updated is generated based on the acquired suffix length and the counted prefix length.
A decoding processing program capable of realizing various functions by a computer that performs processing for decoding a variable-length code bitstream that is an encoded data sequence including at least a prefix and a suffix following the prefix,
A first control function for performing input / output processing for temporarily storing a part of the variable-length code bitstream in a bitstream temporary storage unit;
Based on the prefix and the suffix of the variable-length code bitstream held in the bitstream temporary holding unit, a decoding address used for decoding table reference necessary for decoding is generated, and the bitstream temporary holding is performed. A second control function for generating control information for updating the variable-length code bitstream of a unit;
The computer includes a function including:
In the second control function,
A decoding processing program that causes the computer to realize a function of performing a process of generating the decoding address and a process of updating the variable-length code bitstream of the bitstream temporary storage unit.