WO2009157134A1 - Semiconductor integrated circuit and i/o drive capacity adjustment method - Google Patents

Semiconductor integrated circuit and i/o drive capacity adjustment method Download PDF

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Publication number
WO2009157134A1
WO2009157134A1 PCT/JP2009/002373 JP2009002373W WO2009157134A1 WO 2009157134 A1 WO2009157134 A1 WO 2009157134A1 JP 2009002373 W JP2009002373 W JP 2009002373W WO 2009157134 A1 WO2009157134 A1 WO 2009157134A1
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Prior art keywords
circuit
semiconductor integrated
integrated circuit
input
output
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PCT/JP2009/002373
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French (fr)
Japanese (ja)
Inventor
阿部新一
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パナソニック株式会社
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Publication of WO2009157134A1 publication Critical patent/WO2009157134A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

Definitions

  • the present invention relates to a semiconductor integrated circuit, and more particularly to a technique capable of relaxing various conditions in an environment requiring a high-speed interface between semiconductor devices.
  • FIG. 5 is a plan view showing a semiconductor integrated circuit 1 for explaining a conventional technique and a tester 2 for inspecting the semiconductor integrated circuit 1.
  • the semiconductor integrated circuit 1 includes an I / O (Input / Output) circuit 3, a CPU (Central Processing Unit) 4, a drive capability control circuit 5, a register 6, a DC test output generation circuit 7, A selector 8, selectors 9, 10, 11, 12, 13 and a DC test mode setting circuit 14 are included.
  • I / O Input / Output
  • CPU Central Processing Unit
  • the I / O circuit 3 serves as an interface for ensuring the exchange of information between the semiconductor integrated circuit 1 and various external devices such as the tester 2.
  • the CPU 4 controls the entire semiconductor integrated circuit 1.
  • the drive capability control circuit 5 controls the drive capability of the output buffer of the I / O circuit 3 according to the set value of the register 6.
  • the selector 8 performs input / output control of the I / O circuit 3.
  • the selectors 9, 10, 11, 12 and 13 select the output value of the I / O circuit 3.
  • the DC test mode setting circuit 14 sets the semiconductor integrated circuit 1 to the DC test measurement mode.
  • each terminal of the tester 2 is connected to each terminal of the I / O circuit 3, and each drive current is measured.
  • the drive capability control circuit 5 controls the drive capability of the output buffer of the I / O circuit 3 according to the set value of the register 6.
  • the semiconductor integrated circuit 1 is set to the DC test measurement mode by the DC test mode setting circuit 14.
  • the DC test mode setting circuit 14 forcibly controls the I / O circuit 3 in the output direction by the selector 8.
  • the output of the DC test output generation circuit 7 is selected as the output of each terminal.
  • the tester 2 measures the output drive current value of the I / O circuit 3 based on the output pattern of the DC test output generation circuit 7, and grasps the actual value of the solid. Based on the measured capability value (output drive current value), the actual drive capability setting value is determined so as to suppress the individual difference variation due to the AC timing drive capability.
  • the drive current is measured according to the power supply status and the terminal load status different from those at the time of actual use, and there is inevitably a problem of error between the actual use condition and the tester measurement condition. It was.
  • the present invention self-measures the timing capability when setting the output buffer drive capability of an I / O circuit, particularly in an environment where a high-speed interface between semiconductor devices is required.
  • the present invention relates to a technique for correcting variations due to environmental differences and relaxing AC timing and drive peak current.
  • a semiconductor integrated circuit includes an output buffer and an input buffer, and a plurality of input / output elements for exchanging data with an external device, and through a logic element in a test mode, A test mode setting circuit for connecting the plurality of input / output elements in a chain; and a delay measurement circuit for measuring a total delay value of the plurality of input / output elements connected in a chain in the test mode.
  • the propagation delay can be self-diagnosed assuming the conditions at the time when the chip of the semiconductor integrated circuit is mounted on the substrate, so that more accurate inspection can be performed.
  • a drive capability control circuit that changes the drive capability in stages for the output buffers of a plurality of input / output elements connected in a chain may be provided.
  • an arithmetic unit for reading the total delay value measured by the delay measurement circuit based on a predetermined program may be provided.
  • a hardware circuit that reads the total delay value measured by the delay measurement circuit may be provided.
  • the variation in the drive capability of the output buffer may be corrected based on the total delay value measured by the delay measurement circuit.
  • the total delay value of a plurality of input / output elements connected in a chain shape under the actual use environment conditions in which the wiring on the substrate and the semiconductor integrated circuit are connected I / O drive for measuring the delay using the delay measurement circuit, adjusting the drive capability of the output buffer based on the measured total delay value, and adjusting the communication timing between the input / output element and an external device.
  • a capability adjustment method is further provided.
  • the semiconductor integrated circuit of the present invention since a plurality of input / output elements are connected in a chain shape, the total sum of delay amounts is measured, and the absolute value of the delay amount can be increased. Therefore, in the delay measurement circuit that operates at the clock frequency used inside the semiconductor integrated circuit, sufficient resolution can be obtained and a certain measurement accuracy can be obtained.
  • the propagation delay can be self-diagnosed under the conditions at the time of mounting the semiconductor integrated circuit chip on the substrate, the drive capability adjustment can be performed while assuming the actual operating environment conditions of the semiconductor integrated circuit, such as including the impedance of the substrate wiring. I can plan.
  • the top view which shows the 1st Embodiment of this invention Circuit diagram showing an example of output buffer
  • the figure which shows the example of the specific control procedure on the software in 1st Embodiment The top view which shows the 2nd Embodiment of this invention Diagram showing a general technique based on conventional technology
  • FIG. 1 is a plan view showing a semiconductor integrated circuit 21 and a memory device 22 for inspecting the semiconductor integrated circuit 21 according to the first embodiment of the present invention.
  • the semiconductor integrated circuit 21 includes an I / O circuit 23, a CPU 24, a drive capability adjustment circuit 25, a setting register 26, a delay measurement circuit 27, selectors 28, 29, 30, 31, 32, and 33, and a delay measurement.
  • a test mode setting circuit 34 is included.
  • the I / O circuit 23 serves as an interface that ensures the exchange of information between the semiconductor integrated circuit 1 and various external devices such as the memory device 22.
  • the I / O circuit 23 includes I / O cells 37, 38, 39, 40, 41 as independent input / output elements, and input / output external terminals 52, 53, 54, 55, corresponding to the respective I / O cells. 56.
  • the input / output external terminals 52, 53, 54, 55, and 56 are connected to the memory device 22 via external wirings D0, D1, D2, D3,.
  • Each I / O cell includes an output buffer and an input buffer, and exchanges data with an external device such as the memory device 22.
  • the number of I / O cells in the I / O circuit 23 is arbitrary, the I / O cell 37 is the first cell, the I / O cell 38 is the second cell, the I / O cell 39 is the third cell, The I / O cell 40 is the fourth cell, and the I / O cell 41 is the last cell.
  • a plurality of I / O cells are set between the I / O cell 40 and the I / O cell 41, and similarly, between the input / output external terminal 55 and the input / output external terminal 56.
  • a plurality of input / output external terminals are set, and a plurality of external wirings are set between the external wiring D3 and the external wiring Dn.
  • the selector 28 is a selector that selects an input / output control signal of the I / O circuit 23.
  • the selectors 29, 30, 31, 32, and 33 are selectors that select output signals from the I / O cells 37, 38, 39, 40, and 41, respectively. Further, each of the selectors 29, 30, 31, 32, 33 has normal mode selection signal input lines 42, 43, for inputting a normal mode selection signal which is a signal selected in the normal mode of each I / O cell. 44, 45, 46 are connected.
  • the CPU 24 controls the entire semiconductor integrated circuit 21, but in particular controls the setting register 26 and the delay measurement circuit 27 through the control bus.
  • the CPU 24 functions as an arithmetic unit that reads out the total delay value measured by the delay measurement circuit 27 based on a predetermined program.
  • the setting register 26 determines the drive capability value of the drive capability control circuit 25 that controls the drive capability of the output buffer of the I / O circuit 23 according to the set value.
  • Each I / O cell 37, 38, 39, 40, 41 has a drive capability through control signal output lines 57, 58, 59, 60, 61 for outputting a control signal that is an output from the drive capability control circuit 25.
  • the actual drive capability is determined based on the control signal connected to the control circuit 25.
  • FIG. 2 is a circuit diagram showing a configuration example of an output buffer included in each I / O cell of the I / O circuit 23.
  • the output buffer includes a transistor group 101 and a logic element group 102.
  • the transistor group 101 outputs a signal to an output terminal OUT connected to each input / output external terminal 52, 53, 54, 55, 56.
  • Each combination of TP1-TN1, TP2-TN2, TP3-TN3, and TP4-TN4 which is a combination of P-channel transistor TP and N-channel transistor TN, constitutes an inverter, and four such inverters are connected in parallel.
  • a transistor group 101 is formed.
  • the logic element group 102 constitutes a logic that determines how many sets of the inverters are switched simultaneously.
  • the logic element group 102 is connected to an input terminal IN serving as an input terminal for drive logic.
  • the input terminal IN corresponds to the input lines 62, 63, 64, 65, 66 connected to the selectors 29, 30, 31, 32, 33, and is used for inputting a normal mode selection signal.
  • On / off control on the P channel transistor TP side is performed by control signals from the input terminals of DP1 to DP4, and on / off control on the N channel transistor TN side is performed by control signals from the input terminals of DN1 to DN4.
  • the control signal output lines 57, 58, 59, 60, 61 connected to the drive capability control circuit 25 are connected to the input terminals DP1 to DP4, DN1 to DN4, and the output from the drive capability control circuit 25 is output. Is a control signal that controls the P-channel transistor TP and the N-channel transistor TN.
  • the individual drive capacities of the P channel transistors TP1, TP2, TP3, and TP4 are set to a ratio of 1: 2: 4: 8, respectively.
  • the individual drive capacities of the N-channel transistors TN1, TN2, TN3, and TN4 are set to a ratio of 1: 2: 4: 8, respectively.
  • the P channel transistor TP and the N channel transistor TN of each inverter are enabled (enabled). Can be.
  • the corresponding DP1 to DP4 and DN1 to DN4 terminals are set to “0”.
  • the sum of the drive capacities of the selected transistors is the overall drive capacity of the output buffer.
  • control signals at the DP1 to DP4 and DN1 to DN4 terminals determine how many combinations (inverters) of the P-channel transistor TP and N-channel transistor TN are to be switched simultaneously, and drive the output buffer based on the combination. Capabilities can be set.
  • the output terminal OUT is switched by the drive capability set by the drive logic input from the input terminal IN. Through such control of the output buffer by the drive capability control circuit, it becomes possible to set the drive capability step by step.
  • the output buffer in FIG. 2 is merely an example, and the circuit configuration of the output buffer is not limited to this.
  • the delay measurement test mode setting circuit 34 sets the semiconductor integrated circuit to a test mode for inspecting the semiconductor integrated circuit 21.
  • the selector 28 When the test mode is activated by the delay measurement test mode setting circuit 34, the selector 28 outputs a control signal for fixing the I / O circuit to the output mode to the I / O circuit 23.
  • the delay measurement test mode setting circuit 34 connects a plurality of I / O cells in a chain through a logic element such as a selector.
  • the delay measurement circuit 27 is a circuit for measuring a predetermined delay time as will be described later.
  • the delay measurement circuit 27 is connected to the CPU 24 through an interrupt signal line 68 that outputs an interrupt signal for notifying the CPU 24 of the completion of measurement by the delay measurement circuit 27.
  • the delay measurement circuit 27 is connected to an operation clock line 67 for inputting an operation clock serving as the resolution of the delay measurement circuit 27. As will be described later, in the test mode, the delay measurement circuit 27 measures the total delay value of a plurality of I / O cells connected in a chain.
  • the delay measurement circuit 27 is connected to a start point line 35 and an end point line 36 serving as an output start point and an end point.
  • the input line 62 of the selector 29 connected to the first I / O cell 37 and the start point line 35 of the delay measurement circuit 27 are connected.
  • the I / O cell internal output signals 47, 48, 49, 50 and the endpoint line 36 connected to each I / O cell are transmitted from the I / O cells 37, 38, 39, 40, 41 to the semiconductor integrated circuit 21. This is a line for outputting an I / O cell internal output signal to be output to the inside.
  • the delay measurement circuit 27 issues a test trigger through the start point line 35.
  • An internal output signal as a test trigger input to the selector 29 through the start point line 35 is transmitted to the I / O cell 37 through the input line 62 connected to the first I / O cell 37.
  • a chain connection capable of transmitting an internal output signal is established as follows.
  • Selector 30 ⁇ input line 63 ⁇ I / O cell 38 ⁇ selector 31 ⁇ input line 64 ⁇ I / O cell 39 ⁇ selector 32 ⁇ input line 65 ⁇ I / O cell 40 ⁇ selector 33 ⁇ input line 66 ⁇ I / O cell 41
  • the internal output signal (test trigger) of the final I / O cell 41 is input to the delay measurement circuit 27 through the endpoint line 36 as the end of the chain connection.
  • the test trigger generated from the delay measurement circuit 27 propagates on the chain connection while being influenced by the external wiring load, and finally reaches the input from the endpoint line 36 of the delay measurement circuit 27.
  • the delay measurement circuit 27 performs delay measurement that counts the time from the time when the test trigger is issued through the start point line 35 to the time when the test trigger returns through the end point line 36 within the limit of the resolution of the operation clock 67.
  • the measurement result is notified to the CPU 26 as a count value.
  • step S21 the CPU 24 sets the set value of the setting register 26 corresponding to the drive capability of the drive capability control circuit 25 to a standard value (initial value) (step S21).
  • step S22 the CPU 24 issues a delay measurement command to the delay measurement circuit 27 (step S22).
  • step S23 the delay measurement circuit 27 notifies the CPU 24 with an interrupt (step S23). At this time, it is also possible to receive the end of the delay measurement by polling the flag of the delay measurement circuit 27 by the CPU 24 instead of the interrupt notification.
  • the CPU 24 reads out a delay measurement result (count value) from the delay measurement circuit 27 (step S24). Then, the count value is compared with a preset standard value of the setting register 26. For example, when the standard value of the setting register 26 set in step S21 is 5, the CPU 24 determines whether or not the count value loaded from the delay measurement circuit 27 is greater than 5 (step S25). If the count value is greater than 5 (step S25; Yes), the CPU 24 increases the setting value of the setting register 26 and increases the drive capacity of the drive capacity control circuit 25 by one level (step S26). After that, returning to step S22, the CPU 24 issues a delay measurement command to the delay measurement circuit 27 again.
  • step S25; No and step S27; Yes the CPU 24 lowers the setting value of the setting register 26 and lowers the driving capability of the driving capability control circuit 25 by one step (step S28). After that, returning to step S22, the CPU 24 issues a delay measurement command to the delay measurement circuit 27 again.
  • step S27; No since the count value is 5 which is the same as the set value, the CPU 24 ends the series of drive capability control.
  • the delay measuring circuit 27 measures the total delay amount of the input / output elements. Therefore, the absolute value of the delay amount can be increased. Therefore, in the delay measurement circuit 27 that operates at the clock frequency used in the semiconductor integrated circuit, a sufficient resolution can be obtained and a certain measurement accuracy can be obtained.
  • the drive capability adjustment can be performed while assuming the actual operating environment conditions of the semiconductor integrated circuit, such as including the impedance of the substrate wiring. I can plan.
  • FIG. 4 is a plan view showing a semiconductor integrated circuit 51 and a memory device 52 for inspecting the semiconductor integrated circuit 51 according to the second embodiment of the present invention.
  • the semiconductor integrated circuit 21 includes an I / O circuit 53, a drive capability control circuit 55, a drive capability determination circuit 98, a delay measurement circuit 57, selectors 58, 59, 60, 61, 22, 63, and a delay measurement test.
  • a mode setting circuit 64 is included.
  • the I / O circuit 53 serves as an interface that ensures the exchange of information between the semiconductor integrated circuit 51 and various external devices such as the memory device 52.
  • the I / O circuit 53 includes I / O cells 67, 68, 69, 70, 71 as independent input / output elements, and input / output external terminals 82, 83, 84, 85, corresponding to each I / O cell. 86.
  • Each input / output external terminal 82, 83, 84, 85, 86 is connected to the memory device 52 via external wirings D0, D1, D2, D3,.
  • Each I / O cell includes an output buffer and an input buffer, and exchanges data with an external device such as the memory device 52.
  • the number of I / O cells in the I / O circuit 53 is arbitrary, the I / O cell 67 is the first cell, the I / O cell 68 is the second cell, the I / O cell 69 is the third cell, The I / O cell 70 is the fourth cell, and the I / O cell 71 is the last cell.
  • a plurality of I / O cells are set between the I / O cell 70 and the I / O cell 71, and similarly, between the input / output external terminal 85 and the input / output external terminal 86.
  • a plurality of input / output external terminals are set, and a plurality of external wirings are set between the external wiring D3 and the external wiring Dn.
  • the selector 58 is a selector that selects an input / output control signal of the I / O circuit 53.
  • the selectors 59, 60, 61, 62, and 63 are selectors that select output signals from the I / O cells 67, 68, 69, 70, and 71, respectively.
  • each of the selectors 59, 60, 61, 62, 63 has normal mode selection signal input lines 72, 73 for inputting a normal mode selection signal which is a signal selected in the normal mode of each I / O cell. 74, 75, 76 are connected.
  • the drive capability determination circuit 98 determines the drive capability of each I / O cell based on the delay measurement result from the delay measurement circuit 57 instead of the CPU 24 in the first embodiment.
  • the drive capability determination circuit 98 functions as a hardware circuit that reads the total delay value measured by the delay measurement circuit 57.
  • the drive capability determination circuit 98 receives reference parameters that are fixed values from external register information, terminal setting information, and the like. Based on the determination, the drive capability determination circuit 98 determines the drive capability value of the drive capability control circuit 55 that controls the drive capability of the output buffer of the I / O circuit 53, and outputs it to the drive capability control circuit 55.
  • Each I / O cell 67, 68, 69, 70, 71 has a drive capability through control signal output lines 87, 88, 89, 90, 91 for outputting a control signal that is an output from the drive capability control circuit 55.
  • the actual drive capability is determined based on the control signal connected to the control circuit 55.
  • the delay measurement test mode setting circuit 64 sets the semiconductor integrated circuit in a test mode for inspecting the semiconductor integrated circuit 51.
  • the selector 58 outputs a control signal for fixing the I / O circuit to the output mode to the I / O circuit 53.
  • the delay measurement test mode setting circuit 64 connects a plurality of I / O cells in a chain through a logic element such as a selector.
  • the delay measurement circuit 57 is a circuit for measuring a predetermined delay time as will be described later.
  • the delay measurement circuit 57 is connected to the drive determination circuit 98 through a signal line that outputs a notification signal for notifying the drive capability determination circuit 98 of the completion of the measurement of the delay measurement circuit 57.
  • the delay measurement circuit 57 is connected to an operation clock line 97 for inputting an operation clock serving as the resolution of the delay measurement circuit 57. As will be described later, in the test mode, the delay measurement circuit 57 measures the total delay value of a plurality of I / O cells connected in a chain.
  • the delay measurement circuit 57 is connected to a start point line 65 and an end point line 66 serving as a start point and an end point of the output.
  • the input line 92 of the selector 59 connected to the first I / O cell 67 and the start point line 65 of the delay measurement circuit 57 are connected.
  • the I / O cell internal output signals 77, 78, 79, 80 and the endpoint line 66 connected to each I / O cell are transmitted from the I / O cells 67, 68, 69, 70, 71 to the semiconductor integrated circuit 51. This is a line for outputting an I / O cell internal output signal to be output to the inside.
  • the delay measurement circuit 57 when the test mode is activated by the delay measurement test mode setting circuit 64, the delay measurement circuit 57 generates a test trigger through the start point line 65.
  • An internal output signal as a test trigger input to the selector 59 through the start point line 65 is transmitted to the I / O cell 67 through the input line 92 connected to the first I / O cell 67.
  • a chain connection capable of transmitting an internal output signal is established as follows.
  • Selector 60 ⁇ input line 93 ⁇ I / O cell 68 ⁇ selector 61 ⁇ input line 94 ⁇ I / O cell 69 ⁇ selector 62 ⁇ input line 95 ⁇ I / O cell 70 ⁇ selector 63 ⁇ input line 96 ⁇ I / O cell 71
  • the internal output signal (test trigger) of the final I / O cell 71 is input to the delay measurement circuit 57 through the endpoint line 66 as the end of the chain connection.
  • the test trigger generated from the delay measurement circuit 57 propagates on the chain connection while being influenced by the external wiring load, and finally reaches the input from the endpoint line 66 of the delay measurement circuit 57.
  • the delay measurement circuit 57 performs delay measurement that counts the time from when the test trigger is issued through the start point line 65 to when the test trigger is fed back through the end point line 96 within the limit of the resolution of the operation clock 97.
  • the measurement result is notified to the drive capability determination circuit 98 as a count value.
  • the delay measurement circuit 57 issues a test trigger to the selector 59 through the start point line 65 in response to the activation trigger from the drive capability determination circuit 98.
  • the drive capability determination circuit 98 compares a reference parameter (reference value) given in advance with a measurement result (count value) by the delay measurement circuit 57. When the measurement result is larger than the reference value, the drive capability determination circuit 98 increases the drive capability setting of the drive capability control circuit 55 by one step. On the other hand, when the measurement result is smaller than the reference value, the drive capability determination circuit 98 lowers the drive capability setting of the drive capability control circuit 55 by one step.
  • the drive capability determination circuit 98 restarts the delay measurement circuit 57 by a start trigger, waits for the end of delay measurement, and compares again. Such a comparison operation is repeated, and when the difference between the reference value and the measurement result is finally minimized, the adjustment operation is terminated.
  • a series of adjustment control can be performed consistently only by control by a hardware circuit without depending on CPU software as in the first embodiment.
  • the semiconductor integrated circuit of the present invention a plurality of I / O cells are connected in a chain shape in the test mode. Therefore, not the delay amount of one I / O cell but the total sum of delay amounts of all I / O cells is measured, and the absolute value of the delay amount can be increased. Therefore, in the delay measurement circuit that operates at the clock frequency used inside the semiconductor integrated circuit, sufficient resolution can be obtained and a certain measurement accuracy can be obtained. In addition, since the propagation delay can be self-diagnosed under the conditions at the time when the semiconductor integrated circuit chip is mounted on the substrate, it is possible to adjust the driving ability including the impedance of the base wiring.
  • the semiconductor integrated circuit of the present invention does not rely on the individual difference variation of the driving ability at the time of mass production inspection, and even after mounting on the substrate, it grasps its own ability position by self-check, corrects the variation, This is useful in that the drive capacity value can be set.

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Abstract

The drive capacity of a semiconductor integrated circuit is adjusted without relying on the inspection during mass production shipping. A semiconductor integrated circuit (21) includes an output buffer and an input buffer, and comprises a plurality of I/O cells (37,38,39,40,41) which exchange data with external devices, a test mode setting circuit (34) which connects the plurality of I/O cells in the chain state through logic elements during the test mode, and a delay measurement circuit (27) which measures the total delay of the plurality of I/O cells connected in a chain during the test mode.

Description

半導体集積回路およびＩ／Ｏドライブ能力調整方法Semiconductor integrated circuit and I / O drive capability adjustment method
　本発明は、半導体集積回路に関するものであり、特に半導体デバイス間における高速なインターフェースを要する環境下において、種々の条件を緩和することのできる技術に関する。 The present invention relates to a semiconductor integrated circuit, and more particularly to a technique capable of relaxing various conditions in an environment requiring a high-speed interface between semiconductor devices.
　図５は、従来の技術を説明する半導体集積回路１と、当該半導体集積回路１を検査するテスター２を示す平面図である。半導体集積回路１は、Ｉ／Ｏ（Input/Output；入出力）回路３と、ＣＰＵ（Central Processing Unit）４と、ドライブ能力制御回路５と、レジスタ６と、ＤＣテスト用出力発生回路７と、セレクタ８と、セレクタ９，１０，１１，１２，１３と、ＤＣテストモード設定回路１４とを含む。 FIG. 5 is a plan view showing a semiconductor integrated circuit 1 for explaining a conventional technique and a tester 2 for inspecting the semiconductor integrated circuit 1. The semiconductor integrated circuit 1 includes an I / O (Input / Output) circuit 3, a CPU (Central Processing Unit) 4, a drive capability control circuit 5, a register 6, a DC test output generation circuit 7, A selector 8, selectors 9, 10, 11, 12, 13 and a DC test mode setting circuit 14 are included.
　Ｉ／Ｏ回路３は、半導体集積回路１と、テスター２の如き外部の種々の装置との間の情報のやり取りを確保するインターフェースの役割を果たす。ＣＰＵ４が半導体集積回路１の全体を制御する。レジスタ６の設定値によって、ドライブ能力制御回路５が、Ｉ／Ｏ回路３の出力バッファのドライブ能力を制御する。 The I / O circuit 3 serves as an interface for ensuring the exchange of information between the semiconductor integrated circuit 1 and various external devices such as the tester 2. The CPU 4 controls the entire semiconductor integrated circuit 1. The drive capability control circuit 5 controls the drive capability of the output buffer of the I / O circuit 3 according to the set value of the register 6.
　セレクタ８は、Ｉ／Ｏ回路３の入出力制御を行う。セレクタ９，１０，１１，１２，１３は、Ｉ／Ｏ回路３の出力値を選択する。ＤＣテストモード設定回路１４は、半導体集積回路１をＤＣテスト測定モードに設定する。 The selector 8 performs input / output control of the I / O circuit 3. The selectors 9, 10, 11, 12 and 13 select the output value of the I / O circuit 3. The DC test mode setting circuit 14 sets the semiconductor integrated circuit 1 to the DC test measurement mode.
　検査時において、テスター２の各端子はＩ／Ｏ回路３の各端子に接続され、それぞれのドライブ電流を測定する。レジスタ６の設定値によって、ドライブ能力制御回路５が、Ｉ／Ｏ回路３の出力バッファのドライブ能力を制御する。テスター２におけるＩ／Ｏ回路３のドライブ能力測定時、半導体集積回路１は、ＤＣテストモード設定回路１４によってＤＣテスト測定モードに設定される。ＤＣテストモード設定回路１４は、セレクタ８によって強制的にＩ／Ｏ回路３を出力方向に制御する。ここで、各端子の出力として、ＤＣテスト用出力発生回路７の出力を選択する。 At the time of inspection, each terminal of the tester 2 is connected to each terminal of the I / O circuit 3, and each drive current is measured. The drive capability control circuit 5 controls the drive capability of the output buffer of the I / O circuit 3 according to the set value of the register 6. When measuring the drive capability of the I / O circuit 3 in the tester 2, the semiconductor integrated circuit 1 is set to the DC test measurement mode by the DC test mode setting circuit 14. The DC test mode setting circuit 14 forcibly controls the I / O circuit 3 in the output direction by the selector 8. Here, the output of the DC test output generation circuit 7 is selected as the output of each terminal.
　ＤＣテスト用出力発生回路７の出力パターンに基づき、テスター２は、Ｉ／Ｏ回路３の出力ドライブ電流値を測定し、その固体の実力値を把握する。測定された実力値（出力ドライブ電流値）に基づき、ＡＣタイミングのドライブ能力による個体差ばらつきを抑え込むように、実際のドライブ能力設定値が決定される。 The tester 2 measures the output drive current value of the I / O circuit 3 based on the output pattern of the DC test output generation circuit 7, and grasps the actual value of the solid. Based on the measured capability value (output drive current value), the actual drive capability setting value is determined so as to suppress the individual difference variation due to the AC timing drive capability.
　しかしながら、従来の手法によれば、実使用時とは異なる電源状況や端子負荷状況によるドライブ電流の測定がなされることとなり、実使用条件とテスター測定条件間の誤差の問題が必然的に存在していた。また、測定は半導体集積回路チップ単体の出荷前の検査時でしかできないという制約があった。また、実際に基板へ実装された後で、実装基板の外部環境や配線負荷状況を合わせたタイミング的な個体実力が把握しにくいという課題があった。 However, according to the conventional method, the drive current is measured according to the power supply status and the terminal load status different from those at the time of actual use, and there is inevitably a problem of error between the actual use condition and the tester measurement condition. It was. In addition, there is a restriction that measurement can be performed only at the time of inspection before shipment of the semiconductor integrated circuit chip alone. In addition, there is a problem that it is difficult to grasp the individual ability in terms of timing in accordance with the external environment of the mounting board and the wiring load situation after actually mounting on the board.
　また、Ｉ／Ｏ回路の端子個々のドライブ能力を信号伝搬遅延値としてフィードバックループでセルフチェックしようとした場合、一つの遅延値の絶対量が小さく、半導体集積回路が持つ最大のクロック周波数を使用しても、有効な分解能が得られない問題があった。 Also, when trying to self-check the feedback capability of each I / O circuit terminal drive capability as a signal propagation delay value, the absolute amount of one delay value is small and the maximum clock frequency of the semiconductor integrated circuit is used. However, there is a problem that an effective resolution cannot be obtained.
　本発明は、特に半導体デバイス間における高速なインターフェースを要する環境下において、Ｉ／Ｏ回路の出力バッファドライブ能力設定をする際、タイミング的な実力を自己測定し、配線基板を含めた実力個体差や環境差によるばらつきを補正するとともに、ＡＣタイミングの緩和やドライブピーク電流を緩和する技術に関するものである。 The present invention self-measures the timing capability when setting the output buffer drive capability of an I / O circuit, particularly in an environment where a high-speed interface between semiconductor devices is required. The present invention relates to a technique for correcting variations due to environmental differences and relaxing AC timing and drive peak current.
　上記課題を解決するため、本発明の半導体集積回路は、各々出力バッファと入力バッファを含み、外部の装置との間でデータのやり取りを行う複数の入出力要素と、テストモード時に論理素子を通じて、前記複数の入出力要素をチェーン状に接続するテストモード設定回路と、前記テストモード時に、チェーン状に接続された前記複数の入出力要素の総遅延値を測定する遅延測定回路とを備える。 In order to solve the above problems, a semiconductor integrated circuit according to the present invention includes an output buffer and an input buffer, and a plurality of input / output elements for exchanging data with an external device, and through a logic element in a test mode, A test mode setting circuit for connecting the plurality of input / output elements in a chain; and a delay measurement circuit for measuring a total delay value of the plurality of input / output elements connected in a chain in the test mode.
　上記構成によれば、半導体集積回路のチップを基板上に実装した時点の条件を想定して伝搬遅延を自己診断することができるため、より正確な検査が可能となる。 According to the above configuration, the propagation delay can be self-diagnosed assuming the conditions at the time when the chip of the semiconductor integrated circuit is mounted on the substrate, so that more accurate inspection can be performed.
　本発明の半導体集積回路においては、チェーン状に接続された複数の入出力要素の出力バッファについて、段階的にドライブ能力を変更するドライブ能力制御回路を設けてもよい。 In the semiconductor integrated circuit of the present invention, a drive capability control circuit that changes the drive capability in stages for the output buffers of a plurality of input / output elements connected in a chain may be provided.
　上記構成によれば、入出力要素のドライブ能力の差によるばらつきを調整することが可能となる。 According to the above configuration, it is possible to adjust the variation due to the difference in drive capability of the input / output elements.
　本発明の半導体集積回路においては、所定のプログラムに基づき、前記遅延測定回路により測定した総遅延値を読み出す演算装置を設けてもよい。または、前記遅延測定回路により測定した総遅延値を読み出すハードウェア回路を設けてもよい。 In the semiconductor integrated circuit of the present invention, an arithmetic unit for reading the total delay value measured by the delay measurement circuit based on a predetermined program may be provided. Alternatively, a hardware circuit that reads the total delay value measured by the delay measurement circuit may be provided.
　本発明の半導体集積回路においては、前記遅延測定回路により測定した総遅延値に基づき、前記出力バッファのドライブ能力のばらつき補正を行うようにしてもよい。 In the semiconductor integrated circuit of the present invention, the variation in the drive capability of the output buffer may be corrected based on the total delay value measured by the delay measurement circuit.
　さらに、本発明の半導体集積回路を基板上に実装後、前記基板上の配線と当該半導体集積回路を接続した実際の使用環境条件において、チェーン状に接続された複数の入出力要素の総遅延値を前記遅延測定回路を用いて測定し、測定された総遅延値に基づき、前記出力バッファのドライブ能力を調整し、前記入出力要素と外部の装置との通信タイミング調整をする、Ｉ／Ｏドライブ能力調整方法がさらに提供される。 Further, after mounting the semiconductor integrated circuit of the present invention on a substrate, the total delay value of a plurality of input / output elements connected in a chain shape under the actual use environment conditions in which the wiring on the substrate and the semiconductor integrated circuit are connected I / O drive for measuring the delay using the delay measurement circuit, adjusting the drive capability of the output buffer based on the measured total delay value, and adjusting the communication timing between the input / output element and an external device. A capability adjustment method is further provided.
　本発明の半導体集積回路によれば、複数の入出力要素をチェーン状に接続するため、遅延量の総和が計測され、遅延量の絶対値を大きく取ることが可能となる。したがって、半導体集積回路内部で使用するクロック周波数で動作する遅延測定回路において、十分な分解能が得られるようになり、一定の測定精度が得られるようになる。また、半導体集積回路チップを基板実装した時点の条件で伝搬遅延が自己診断できるため、基板配線のインピーダンスを包括するといった如く、実際の半導体集積回路の使用環境条件を想定しつつ、ドライブ能力調整が図れる。 According to the semiconductor integrated circuit of the present invention, since a plurality of input / output elements are connected in a chain shape, the total sum of delay amounts is measured, and the absolute value of the delay amount can be increased. Therefore, in the delay measurement circuit that operates at the clock frequency used inside the semiconductor integrated circuit, sufficient resolution can be obtained and a certain measurement accuracy can be obtained. In addition, since the propagation delay can be self-diagnosed under the conditions at the time of mounting the semiconductor integrated circuit chip on the substrate, the drive capability adjustment can be performed while assuming the actual operating environment conditions of the semiconductor integrated circuit, such as including the impedance of the substrate wiring. I can plan.
本発明の第１の実施形態を示す平面図The top view which shows the 1st Embodiment of this invention 出力バッファの一例を示す回路図Circuit diagram showing an example of output buffer 第１の実施形態におけるソフトウェア上の具体的制御手順例を示す図The figure which shows the example of the specific control procedure on the software in 1st Embodiment 本発明の第２の実施形態を示す平面図The top view which shows the 2nd Embodiment of this invention 従来の技術に基づく一般的な手法を示す図Diagram showing a general technique based on conventional technology
　以下、本発明の実施形態を、図面を参照しながら詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
（実施形態１）
　図１は本発明の第１の実施形態に係る半導体集積回路２１と、当該半導体集積回路２１を検査するメモリデバイス２２を示す平面図である。 (Embodiment 1)
FIG. 1 is a plan view showing a semiconductor integrated circuit 21 and a memory device 22 for inspecting the semiconductor integrated circuit 21 according to the first embodiment of the present invention.
　半導体集積回路２１は、Ｉ／Ｏ回路２３と、ＣＰＵ２４と、ドライブ能力調整回路２５と、設定レジスタ２６と、遅延測定回路２７と、セレクタ２８，２９，３０，３１，３２，３３と、遅延測定テストモード設定回路３４を含む。 The semiconductor integrated circuit 21 includes an I / O circuit 23, a CPU 24, a drive capability adjustment circuit 25, a setting register 26, a delay measurement circuit 27, selectors 28, 29, 30, 31, 32, and 33, and a delay measurement. A test mode setting circuit 34 is included.
　Ｉ／Ｏ回路２３は、半導体集積回路１と、メモリデバイス２２の如き外部の種々の装置との間の情報のやり取りを確保するインターフェースの役割を果たす。Ｉ／Ｏ回路２３は、各々独立した入出力要素としてのＩ／Ｏセル３７，３８，３９，４０，４１と、各Ｉ／Ｏセルに対応した入出力外部端子５２，５３，５４，５５，５６を含む。各入出力外部端子５２，５３，５４，５５，５６は、それぞれ基板上の外部配線Ｄ０，Ｄ１，Ｄ２，Ｄ３，・・・，Ｄｎを介し、メモリデバイス２２に接続される。 The I / O circuit 23 serves as an interface that ensures the exchange of information between the semiconductor integrated circuit 1 and various external devices such as the memory device 22. The I / O circuit 23 includes I / O cells 37, 38, 39, 40, 41 as independent input / output elements, and input / output external terminals 52, 53, 54, 55, corresponding to the respective I / O cells. 56. The input / output external terminals 52, 53, 54, 55, and 56 are connected to the memory device 22 via external wirings D0, D1, D2, D3,.
　各Ｉ／Ｏセルは、出力バッファと入力バッファを含み、メモリデバイス２２のごとき外部の装置との間でデータのやり取りを行う。Ｉ／Ｏ回路２３のＩ／Ｏセルの個数は任意であり、Ｉ／Ｏセル３７が1番目のセル、Ｉ／Ｏセル３８が２番目のセル、Ｉ／Ｏセル３９が３番目のセル、Ｉ／Ｏセル４０が４番目のセルであり、Ｉ／Ｏセル４１は最終のセルである。図に示すように、Ｉ／Ｏセル４０とＩ／Ｏセル４１の間には、複数のＩ／Ｏセルが設定されており、同様に、入出力外部端子５５と入出力外部端子５６の間には、複数の入出力外部端子が設定されており、外部配線Ｄ３と外部配線Ｄｎの間には複数の外部配線が設定される。 Each I / O cell includes an output buffer and an input buffer, and exchanges data with an external device such as the memory device 22. The number of I / O cells in the I / O circuit 23 is arbitrary, the I / O cell 37 is the first cell, the I / O cell 38 is the second cell, the I / O cell 39 is the third cell, The I / O cell 40 is the fourth cell, and the I / O cell 41 is the last cell. As shown in the figure, a plurality of I / O cells are set between the I / O cell 40 and the I / O cell 41, and similarly, between the input / output external terminal 55 and the input / output external terminal 56. A plurality of input / output external terminals are set, and a plurality of external wirings are set between the external wiring D3 and the external wiring Dn.
　セレクタ２８は、Ｉ／Ｏ回路２３の入出力制御信号を選択するセレクタである。セレクタ２９，３０，３１，３２，３３は、それぞれＩ／Ｏセル３７，３８，３９，４０，４１の出力信号を選択するセレクタである。また、セレクタ２９，３０，３１，３２，３３各々には、各Ｉ／Ｏセルの通常モード時に選択される信号である通常モード選択信号を入力するための通常モード選択信号入力線４２，４３，４４，４５，４６が接続されている。 The selector 28 is a selector that selects an input / output control signal of the I / O circuit 23. The selectors 29, 30, 31, 32, and 33 are selectors that select output signals from the I / O cells 37, 38, 39, 40, and 41, respectively. Further, each of the selectors 29, 30, 31, 32, 33 has normal mode selection signal input lines 42, 43, for inputting a normal mode selection signal which is a signal selected in the normal mode of each I / O cell. 44, 45, 46 are connected.
　ＣＰＵ２４は、半導体集積回路２１の全体を制御するが、特に制御バス通じて設定レジスタ２６と、遅延測定回路２７を制御する。そして、ＣＰＵ２４は、所定のプログラムに基づき、遅延測定回路２７により測定した総遅延値を読み出す演算装置として機能する。設定レジスタ２６は、設定された設定値により、Ｉ／Ｏ回路２３の出力バッファのドライブ能力を制御するドライブ能力制御回路２５のドライブ能力値を決定する。 The CPU 24 controls the entire semiconductor integrated circuit 21, but in particular controls the setting register 26 and the delay measurement circuit 27 through the control bus. The CPU 24 functions as an arithmetic unit that reads out the total delay value measured by the delay measurement circuit 27 based on a predetermined program. The setting register 26 determines the drive capability value of the drive capability control circuit 25 that controls the drive capability of the output buffer of the I / O circuit 23 according to the set value.
　各Ｉ／Ｏセル３７，３８，３９，４０，４１は、それぞれドライブ能力制御回路２５からの出力である制御信号を出力するための制御信号出力線５７，５８，５９，６０，６１を通じてドライブ能力制御回路２５と接続され、当該制御信号に基づき、実際のドライブ能力が決定される。 Each I / O cell 37, 38, 39, 40, 41 has a drive capability through control signal output lines 57, 58, 59, 60, 61 for outputting a control signal that is an output from the drive capability control circuit 25. The actual drive capability is determined based on the control signal connected to the control circuit 25.
　図２は、Ｉ／Ｏ回路２３の各Ｉ／Ｏセルに含まれる出力バッファの構成例を示す回路図である。出力バッファは、トランジスタ群１０１と論理素子群１０２とから構成される。トランジスタ群１０１は、各入出力外部端子５２，５３，５４，５５，５６に接続される出力端子ＯＵＴへ信号を出力する。また、ＰチャンネルトランジスタＴＰとＮチャンネルトランジスタＴＮの組み合わせである、ＴＰ１－ＴＮ１、ＴＰ２－ＴＮ２、ＴＰ３－ＴＮ３、ＴＰ４－ＴＮ４各々の組み合わせはインバータを構成し、当該インバータが４つ並列に接続されて、トランジスタ群１０１が構成される。論理素子群１０２は、当該インバータを何組まで同時にスイッチングさせるかを決定するロジックを構成する。論理素子群１０２はドライブ論理の入力端となる入力端子ＩＮに接続されている。入力端子ＩＮは、セレクタ２９，３０，３１，３２，３３に接続された入力線６２，６３，６４，６５，６６に対応し、通常モード選択信号の入力に使用されるものである。 FIG. 2 is a circuit diagram showing a configuration example of an output buffer included in each I / O cell of the I / O circuit 23. The output buffer includes a transistor group 101 and a logic element group 102. The transistor group 101 outputs a signal to an output terminal OUT connected to each input / output external terminal 52, 53, 54, 55, 56. Each combination of TP1-TN1, TP2-TN2, TP3-TN3, and TP4-TN4, which is a combination of P-channel transistor TP and N-channel transistor TN, constitutes an inverter, and four such inverters are connected in parallel. A transistor group 101 is formed. The logic element group 102 constitutes a logic that determines how many sets of the inverters are switched simultaneously. The logic element group 102 is connected to an input terminal IN serving as an input terminal for drive logic. The input terminal IN corresponds to the input lines 62, 63, 64, 65, 66 connected to the selectors 29, 30, 31, 32, 33, and is used for inputting a normal mode selection signal.
　ＰチャンネルトランジスタＴＰ側のオン・オフ制御は、ＤＰ１～ＤＰ４の各入力端子からの制御信号、ＮチャンネルトランジスタＴＮ側のオン・オフ制御は、ＤＮ１～ＤＮ４の各入力端子からの制御信号により行われる。ここで、ドライブ能力制御回路２５に接続された制御信号出力線５７，５８，５９，６０，６１が、入力端子ＤＰ１～ＤＰ４、ＤＮ１～ＤＮ４に接続されており、ドライブ能力制御回路２５からの出力である制御信号が、ＰチャンネルトランジスタＴＰ、ＮチャンネルトランジスタＴＮを制御する上記した制御信号に該当する。 On / off control on the P channel transistor TP side is performed by control signals from the input terminals of DP1 to DP4, and on / off control on the N channel transistor TN side is performed by control signals from the input terminals of DN1 to DN4. . Here, the control signal output lines 57, 58, 59, 60, 61 connected to the drive capability control circuit 25 are connected to the input terminals DP1 to DP4, DN1 to DN4, and the output from the drive capability control circuit 25 is output. Is a control signal that controls the P-channel transistor TP and the N-channel transistor TN.
　ＰチャンネルトランジスタＴＰ１，ＴＰ２，ＴＰ３，ＴＰ４個別のドライブ能力は、それぞれ１：２：４：８の比に設定されている。同様に、ＮチャンネルトランジスタＴＮ１，ＴＮ２，ＴＮ３，ＴＮ４個別のドライブ能力も、それぞれ１：２：４：８の比に設定されている。 The individual drive capacities of the P channel transistors TP1, TP2, TP3, and TP4 are set to a ratio of 1: 2: 4: 8, respectively. Similarly, the individual drive capacities of the N-channel transistors TN1, TN2, TN3, and TN4 are set to a ratio of 1: 2: 4: 8, respectively.
　ドライブ能力制御回路２５からの制御信号により、ＤＰ１～ＤＰ４、ＤＮ１～ＤＮ４端子を選択的に“１”に設定することにより、各インバータのＰチャンネルトランジスタＴＰ、ＮチャンネルトランジスタＴＮをそれぞれ有効（イネーブル）にすることができる。一方、所定のインバータのトランジスタＴＰ、ＴＮを無効（ディセーブル）にしたい場合は、対応するＤＰ１～ＤＰ４、ＤＮ１～ＤＮ４端子を“０”に設定する。その結果、選択されたトランジスタ（入力端子ＤＰ、ＤＮが“１”）のドライブ能力の合算が、出力バッファの全体のドライブ能力となる。 By selectively setting the DP1 to DP4 and DN1 to DN4 terminals to “1” by the control signal from the drive capability control circuit 25, the P channel transistor TP and the N channel transistor TN of each inverter are enabled (enabled). Can be. On the other hand, when it is desired to disable (disable) the transistors TP and TN of a predetermined inverter, the corresponding DP1 to DP4 and DN1 to DN4 terminals are set to “0”. As a result, the sum of the drive capacities of the selected transistors (input terminals DP and DN are “1”) is the overall drive capacity of the output buffer.
　すなわち、ＤＰ１～ＤＰ４、ＤＮ１～ＤＮ４端子での制御信号で、それぞれＰチャンネルトランジスタＴＰ、ＮチャンネルトランジスタＴＮの組み合わせ（インバータ）の何組を同時にスイッチングするかを決定し、その組み合わせで出力バッファのドライブ能力を設定することが可能となる。入力端子ＩＮから入力されるドライブ論理を設定されたドライブ能力により出力端子ＯＵＴをスイッチングする。このようなドライブ能力制御回路による出力バッファの制御を経て、段階的にドライブ能力を設定することが可能になる。 That is, the control signals at the DP1 to DP4 and DN1 to DN4 terminals determine how many combinations (inverters) of the P-channel transistor TP and N-channel transistor TN are to be switched simultaneously, and drive the output buffer based on the combination. Capabilities can be set. The output terminal OUT is switched by the drive capability set by the drive logic input from the input terminal IN. Through such control of the output buffer by the drive capability control circuit, it becomes possible to set the drive capability step by step.
　図２の出力バッファは単なる一例であり、出力バッファの回路構成はこれに限定はされない。 The output buffer in FIG. 2 is merely an example, and the circuit configuration of the output buffer is not limited to this.
　遅延測定テストモード設定回路３４は、半導体集積回路２１検査するためのテストモードに半導体集積回路を設定する。遅延測定テストモード設定回路３４により当該のテストモードがアクティブになると、セレクタ２８は、Ｉ／Ｏ回路２３に対し、Ｉ　／Ｏ回路を出力モードに固定する制御信号を出力する。本発明においては、後述するように、テストモード時において、遅延測定テストモード設定回路３４は、セレクタのごとき論理素子を通じて、複数のＩ／Ｏセルをチェーン状に接続する。 The delay measurement test mode setting circuit 34 sets the semiconductor integrated circuit to a test mode for inspecting the semiconductor integrated circuit 21. When the test mode is activated by the delay measurement test mode setting circuit 34, the selector 28 outputs a control signal for fixing the I / O circuit to the output mode to the I / O circuit 23. In the present invention, as will be described later, in the test mode, the delay measurement test mode setting circuit 34 connects a plurality of I / O cells in a chain through a logic element such as a selector.
　遅延測定回路２７は、後述するように所定の遅延時間を測定するための回路である。遅延測定回路２７は、遅延測定回路２７の測定終了をＣＰＵ２４へ通知するための割込み信号を出力する割込み信号線６８を通じてＣＰＵ２４と接続されている。また、遅延測定回路２７には、遅延測定回路２７の分解能となる動作クロックを入力する動作クロック線６７が接続されている。後述するように、テストモード時において、遅延測定回路２７は、チェーン状に接続された複数のＩ／Ｏセルの総遅延値を測定する。 The delay measurement circuit 27 is a circuit for measuring a predetermined delay time as will be described later. The delay measurement circuit 27 is connected to the CPU 24 through an interrupt signal line 68 that outputs an interrupt signal for notifying the CPU 24 of the completion of measurement by the delay measurement circuit 27. The delay measurement circuit 27 is connected to an operation clock line 67 for inputting an operation clock serving as the resolution of the delay measurement circuit 27. As will be described later, in the test mode, the delay measurement circuit 27 measures the total delay value of a plurality of I / O cells connected in a chain.
　さらに、遅延測定回路２７には、その出力のスタートポイント、エンドポイントとなるスタートポイント線３５、エンドポイント線３６が接続されている。テストモード時に、１番目のＩ／Ｏセル３７に接続されたセレクタ２９の入力線６２と遅延測定回路２７のスタートポイント線３５が接続される。また、各Ｉ／Ｏセルに接続されたＩ／Ｏセル内部出力信号４７，４８，４９，５０およびエンドポイント線３６は、Ｉ／Ｏセル３７，３８，３９，４０，４１から半導体集積回路２１の内部へ出力されるＩ／Ｏセル内部出力信号を出力するための線である。 Furthermore, the delay measurement circuit 27 is connected to a start point line 35 and an end point line 36 serving as an output start point and an end point. In the test mode, the input line 62 of the selector 29 connected to the first I / O cell 37 and the start point line 35 of the delay measurement circuit 27 are connected. Also, the I / O cell internal output signals 47, 48, 49, 50 and the endpoint line 36 connected to each I / O cell are transmitted from the I / O cells 37, 38, 39, 40, 41 to the semiconductor integrated circuit 21. This is a line for outputting an I / O cell internal output signal to be output to the inside.
　上述したように、遅延測定テストモード設定回路３４によりテストモードがアクティブになると、遅延測定回路２７は、スタートポイント線３５を通じて、テストトリガを発する。スタートポイント線３５を通じてセレクタ２９に入力されたテストトリガとしての内部出力信号は、１番目のＩ／Ｏセル３７に接続された入力線６２を通じて、Ｉ／Ｏセル３７に伝えられる。以下、次のように内部出力信号が伝達可能なチェーン接続が成立する。 As described above, when the test mode is activated by the delay measurement test mode setting circuit 34, the delay measurement circuit 27 issues a test trigger through the start point line 35. An internal output signal as a test trigger input to the selector 29 through the start point line 35 is transmitted to the I / O cell 37 through the input line 62 connected to the first I / O cell 37. Hereinafter, a chain connection capable of transmitting an internal output signal is established as follows.
　セレクタ３０→入力線６３→Ｉ／Ｏセル３８→セレクタ３１→入力線６４→Ｉ／Ｏセル３９→セレクタ３２→入力線６５→Ｉ／Ｏセル４０→セレクタ３３→入力線６６→Ｉ／Ｏセル４１ Selector 30 → input line 63 → I / O cell 38 → selector 31 → input line 64 → I / O cell 39 → selector 32 → input line 65 → I / O cell 40 → selector 33 → input line 66 → I / O cell 41
　最終のＩ／Ｏセル４１の内部出力信号（テストトリガ）は、チェーン接続の末尾として、エンドポイント線３６を通じて遅延測定回路２７に入力される。遅延測定回路２７から発せられたテストトリガは、外部配線負荷の影響を受けながらチェーン接続上を伝搬し、最後に遅延測定回路２７のエンドポイント線３６からの入力へ到達する。遅延測定回路２７は、動作クロック６７の分解能の限度で、スタートポイント線３５を通じてテストトリガが発せられた時刻から、エンドポイント線３６を通じてテストトリガが帰還してくるまでの時間をカウントする遅延測定を行い、その測定結果をカウント値としてＣＰＵ２６へ通知する。 The internal output signal (test trigger) of the final I / O cell 41 is input to the delay measurement circuit 27 through the endpoint line 36 as the end of the chain connection. The test trigger generated from the delay measurement circuit 27 propagates on the chain connection while being influenced by the external wiring load, and finally reaches the input from the endpoint line 36 of the delay measurement circuit 27. The delay measurement circuit 27 performs delay measurement that counts the time from the time when the test trigger is issued through the start point line 35 to the time when the test trigger returns through the end point line 36 within the limit of the resolution of the operation clock 67. The measurement result is notified to the CPU 26 as a count value.
　次に、実施形態１における半導体集積回路の検査用ソフトウェア（プログラム）を用いたＣＰＵ２４による半導体集積回路２１の具体的制御手順（ドライブ能力制御手順）の例を、図３のフローチャートに示す。まず、ＣＰＵ２４は、ドライブ能力制御回路２５のドライブ能力に相当する設定レジスタ２６の設定値を標準値（初期値）に設定する（ステップＳ２１）。次にＣＰＵ２４は、上述したように、遅延測定回路２７へ遅延測定命令を発する（ステップＳ２２）。遅延測定回路２７は、上述したチェーン接続に基づく遅延測定を終了すると、割込みにてＣＰＵ２４へ通知する（ステップＳ２３）。この際、割込み通知ではなく、ＣＰＵ２４が遅延測定回路２７のフラグをポーリングすることにより、遅延測定の終了を受信することも可能である。 Next, an example of a specific control procedure (drive capability control procedure) of the semiconductor integrated circuit 21 by the CPU 24 using the semiconductor integrated circuit inspection software (program) in the first embodiment is shown in the flowchart of FIG. First, the CPU 24 sets the set value of the setting register 26 corresponding to the drive capability of the drive capability control circuit 25 to a standard value (initial value) (step S21). Next, as described above, the CPU 24 issues a delay measurement command to the delay measurement circuit 27 (step S22). When the delay measurement circuit 27 completes the delay measurement based on the chain connection described above, the delay measurement circuit 27 notifies the CPU 24 with an interrupt (step S23). At this time, it is also possible to receive the end of the delay measurement by polling the flag of the delay measurement circuit 27 by the CPU 24 instead of the interrupt notification.
　続いてＣＰＵ２４は、遅延測定回路２７から遅延測定結果（カウント値）を読み出す（ステップＳ２４）。そして、当該カウント値と予め設定された設定レジスタ２６の標準値とを比較する。例えば、ステップＳ２１で設定された設定レジスタ２６の標準値が５であった場合、ＣＰＵ２４は、遅延測定回路２７からロードされたカウント値が５より大きいか否かを判定する（ステップＳ２５）。カウント値が５より大きい場合（ステップＳ２５；Ｙｅｓ）、ＣＰＵ２４は、設定レジスタ２６の設定値を引き上げ、ドライブ能力制御回路２５のドライブ能力を１段階引き上げる（ステップＳ２６）。その後、ステップＳ２２に戻り、ＣＰＵ２４は再び遅延測定回路２７へ遅延測定命令を発行する。 Subsequently, the CPU 24 reads out a delay measurement result (count value) from the delay measurement circuit 27 (step S24). Then, the count value is compared with a preset standard value of the setting register 26. For example, when the standard value of the setting register 26 set in step S21 is 5, the CPU 24 determines whether or not the count value loaded from the delay measurement circuit 27 is greater than 5 (step S25). If the count value is greater than 5 (step S25; Yes), the CPU 24 increases the setting value of the setting register 26 and increases the drive capacity of the drive capacity control circuit 25 by one level (step S26). After that, returning to step S22, the CPU 24 issues a delay measurement command to the delay measurement circuit 27 again.
　一方、カウント値が５より小さい場合（ステップＳ２５；ＮｏかつステップＳ２７；Ｙｅｓ）、ＣＰＵ２４は、設定レジスタ２６の設定値を引き下げ、ドライブ能力制御回路２５のドライブ能力を１段階引き下げる（ステップＳ２８）。その後、ステップＳ２２に戻り、ＣＰＵ２４は再び遅延測定回路２７へ遅延測定命令を発行する。カウント値が５より大きくもなく小さくもない場合は（ステップＳ２７；Ｎｏ）、カウント値は設定値と同じ５であるため、ＣＰＵ２４は一連のドライブ能力制御を終了する。 On the other hand, when the count value is smaller than 5 (step S25; No and step S27; Yes), the CPU 24 lowers the setting value of the setting register 26 and lowers the driving capability of the driving capability control circuit 25 by one step (step S28). After that, returning to step S22, the CPU 24 issues a delay measurement command to the delay measurement circuit 27 again. When the count value is neither larger nor smaller than 5 (step S27; No), since the count value is 5 which is the same as the set value, the CPU 24 ends the series of drive capability control.
　上述したように、本発明の半導体集積回路によれば、複数のＩ／Ｏセルの如く入出力要素をチェーン状に接続されており、遅延測定回路２７は入出力要素の遅延量の総和を計測するので、遅延量の絶対値を大きく取ることが可能となる。したがって、半導体集積回路内部で使用するクロック周波数で動作する遅延測定回路２７において、十分な分解能が得られるようになり、一定の測定精度が得られるようになる。また、半導体集積回路チップを基板実装した時点の条件で伝搬遅延が自己診断できるため、基板配線のインピーダンスを包括するといった如く、実際の半導体集積回路の使用環境条件を想定しつつ、ドライブ能力調整が図れる。そして、本発明のドライブ能力制御を行うことにより、Ｉ／Ｏ回路２３の各Ｉ／Ｏセルのドライブ能力に個体差があった場合でも、ばらつきを抑制する方向へ調整することができる。 As described above, according to the semiconductor integrated circuit of the present invention, input / output elements are connected in a chain like a plurality of I / O cells, and the delay measuring circuit 27 measures the total delay amount of the input / output elements. Therefore, the absolute value of the delay amount can be increased. Therefore, in the delay measurement circuit 27 that operates at the clock frequency used in the semiconductor integrated circuit, a sufficient resolution can be obtained and a certain measurement accuracy can be obtained. In addition, since the propagation delay can be self-diagnosed under the conditions at the time of mounting the semiconductor integrated circuit chip on the substrate, the drive capability adjustment can be performed while assuming the actual operating environment conditions of the semiconductor integrated circuit, such as including the impedance of the substrate wiring. I can plan. By performing the drive capability control according to the present invention, even if there is an individual difference in the drive capability of each I / O cell of the I / O circuit 23, it is possible to adjust the direction so as to suppress variation.
（実施形態２）
　図４は本発明の第２の実施形態に係る半導体集積回路５１と、当該半導体集積回路５１を検査するメモリデバイス５２を示す平面図である。 (Embodiment 2)
FIG. 4 is a plan view showing a semiconductor integrated circuit 51 and a memory device 52 for inspecting the semiconductor integrated circuit 51 according to the second embodiment of the present invention.
　半導体集積回路２１は、Ｉ／Ｏ回路５３と、ドライブ能力制御回路５５と、ドライブ能力判定回路９８と、遅延測定回路５７と、セレクタ５８，５９，６０，６１，２２，６３と、遅延測定テストモード設定回路６４を含む。 The semiconductor integrated circuit 21 includes an I / O circuit 53, a drive capability control circuit 55, a drive capability determination circuit 98, a delay measurement circuit 57, selectors 58, 59, 60, 61, 22, 63, and a delay measurement test. A mode setting circuit 64 is included.
　Ｉ／Ｏ回路５３は、半導体集積回路５１と、メモリデバイス５２の如き外部の種々の装置との間の情報のやり取りを確保するインターフェースの役割を果たす。Ｉ／Ｏ回路５３は、各々独立した入出力要素としてのＩ／Ｏセル６７，６８，６９，７０，７１と、各Ｉ／Ｏセルに対応した入出力外部端子８２，８３，８４，８５，８６を含む。各入出力外部端子８２，８３，８４，８５，８６は、それぞれ基板上の外部配線Ｄ０，Ｄ１，Ｄ２，Ｄ３，・・・，Ｄｎを介し、メモリデバイス５２に接続される。 The I / O circuit 53 serves as an interface that ensures the exchange of information between the semiconductor integrated circuit 51 and various external devices such as the memory device 52. The I / O circuit 53 includes I / O cells 67, 68, 69, 70, 71 as independent input / output elements, and input / output external terminals 82, 83, 84, 85, corresponding to each I / O cell. 86. Each input / output external terminal 82, 83, 84, 85, 86 is connected to the memory device 52 via external wirings D0, D1, D2, D3,.
　各Ｉ／Ｏセルは、出力バッファと入力バッファを含み、メモリデバイス５２のごとき外部の装置との間でデータのやり取りを行う。Ｉ／Ｏ回路５３のＩ／Ｏセルの個数は任意であり、Ｉ／Ｏセル６７が1番目のセル、Ｉ／Ｏセル６８が２番目のセル、Ｉ／Ｏセル６９が３番目のセル、Ｉ／Ｏセル７０が４番目のセルであり、Ｉ／Ｏセル７１は最終のセルである。図に示すように、Ｉ／Ｏセル７０とＩ／Ｏセル７１の間には、複数のＩ／Ｏセルが設定されており、同様に、入出力外部端子８５と入出力外部端子８６の間には、複数の入出力外部端子が設定されており、外部配線Ｄ３と外部配線Ｄｎの間には複数の外部配線が設定される。 Each I / O cell includes an output buffer and an input buffer, and exchanges data with an external device such as the memory device 52. The number of I / O cells in the I / O circuit 53 is arbitrary, the I / O cell 67 is the first cell, the I / O cell 68 is the second cell, the I / O cell 69 is the third cell, The I / O cell 70 is the fourth cell, and the I / O cell 71 is the last cell. As shown in the figure, a plurality of I / O cells are set between the I / O cell 70 and the I / O cell 71, and similarly, between the input / output external terminal 85 and the input / output external terminal 86. A plurality of input / output external terminals are set, and a plurality of external wirings are set between the external wiring D3 and the external wiring Dn.
　セレクタ５８は、Ｉ／Ｏ回路５３の入出力制御信号を選択するセレクタである。セレクタ５９，６０，６１，６２，６３は、それぞれＩ／Ｏセル６７，６８，６９，７０，７１の出力信号を選択するセレクタである。また、セレクタ５９，６０，６１，６２，６３各々には、各Ｉ／Ｏセルの通常モード時に選択される信号である通常モード選択信号を入力するための通常モード選択信号入力線７２，７３，７４，７５，７６が接続されている。 The selector 58 is a selector that selects an input / output control signal of the I / O circuit 53. The selectors 59, 60, 61, 62, and 63 are selectors that select output signals from the I / O cells 67, 68, 69, 70, and 71, respectively. In addition, each of the selectors 59, 60, 61, 62, 63 has normal mode selection signal input lines 72, 73 for inputting a normal mode selection signal which is a signal selected in the normal mode of each I / O cell. 74, 75, 76 are connected.
　ドライブ能力判定回路９８は、第１の実施形態におけるＣＰＵ２４に代わって、遅延測定回路５７からの遅延測定結果に基づき、各Ｉ／Ｏセルのドライブ能力を判定するものである。ドライブ能力判定回路９８は、遅延測定回路５７により測定した総遅延値を読み出すハードウェア回路として機能する。また、ドライブ能力判定回路９８には、外部のレジスタ情報や、端子設定情報等から固定値化された基準パラメータが入力される。ドライブ能力判定回路９８は、判断に基づき、Ｉ／Ｏ回路５３の出力バッファのドライブ能力を制御するドライブ能力制御回路５５のドライブ能力値を決定し、ドライブ能力制御回路５５に出力する。 The drive capability determination circuit 98 determines the drive capability of each I / O cell based on the delay measurement result from the delay measurement circuit 57 instead of the CPU 24 in the first embodiment. The drive capability determination circuit 98 functions as a hardware circuit that reads the total delay value measured by the delay measurement circuit 57. In addition, the drive capability determination circuit 98 receives reference parameters that are fixed values from external register information, terminal setting information, and the like. Based on the determination, the drive capability determination circuit 98 determines the drive capability value of the drive capability control circuit 55 that controls the drive capability of the output buffer of the I / O circuit 53, and outputs it to the drive capability control circuit 55.
　各Ｉ／Ｏセル６７，６８，６９，７０，７１は、それぞれドライブ能力制御回路５５からの出力である制御信号を出力するための制御信号出力線８７，８８，８９，９０，９１を通じてドライブ能力制御回路５５と接続され、当該制御信号に基づき、実際のドライブ能力が決定される。 Each I / O cell 67, 68, 69, 70, 71 has a drive capability through control signal output lines 87, 88, 89, 90, 91 for outputting a control signal that is an output from the drive capability control circuit 55. The actual drive capability is determined based on the control signal connected to the control circuit 55.
　遅延測定テストモード設定回路６４は、半導体集積回路５１を検査するためのテストモードに半導体集積回路を設定する。遅延測定テストモード設定回路６４により当該のテストモードがアクティブになると、セレクタ５８は、Ｉ／Ｏ回路５３に対し、Ｉ　／Ｏ回路を出力モードに固定する制御信号を出力する。本発明においては、後述するように、テストモード時において、遅延測定テストモード設定回路６４は、セレクタのごとき論理素子を通じて、複数のＩ／Ｏセルをチェーン状に接続する。 The delay measurement test mode setting circuit 64 sets the semiconductor integrated circuit in a test mode for inspecting the semiconductor integrated circuit 51. When the test mode is activated by the delay measurement test mode setting circuit 64, the selector 58 outputs a control signal for fixing the I / O circuit to the output mode to the I / O circuit 53. In the present invention, as will be described later, in the test mode, the delay measurement test mode setting circuit 64 connects a plurality of I / O cells in a chain through a logic element such as a selector.
　遅延測定回路５７は、後述するように所定の遅延時間を測定するための回路である。遅延測定回路５７は、遅延測定回路５７の測定終了をドライブ能力判定回路９８へ通知するための通知信号を出力する信号線を通じてドライブ判定回路９８と接続されている。また、遅延測定回路５７には、遅延測定回路５７の分解能となる動作クロックを入力する動作クロック線９７が接続されている。後述するように、テストモード時において、遅延測定回路５７は、チェーン状に接続された複数のＩ／Ｏセルの総遅延値を測定する。 The delay measurement circuit 57 is a circuit for measuring a predetermined delay time as will be described later. The delay measurement circuit 57 is connected to the drive determination circuit 98 through a signal line that outputs a notification signal for notifying the drive capability determination circuit 98 of the completion of the measurement of the delay measurement circuit 57. The delay measurement circuit 57 is connected to an operation clock line 97 for inputting an operation clock serving as the resolution of the delay measurement circuit 57. As will be described later, in the test mode, the delay measurement circuit 57 measures the total delay value of a plurality of I / O cells connected in a chain.
　さらに、遅延測定回路５７には、その出力のスタートポイント、エンドポイントとなるスタートポイント線６５、エンドポイント線６６が接続されている。テストモード時に、１番目のＩ／Ｏセル６７に接続されたセレクタ５９の入力線９２と遅延測定回路５７のスタートポイント線６５が接続される。また、各Ｉ／Ｏセルに接続されたＩ／Ｏセル内部出力信号７７，７８，７９，８０およびエンドポイント線６６は、Ｉ／Ｏセル６７，６８，６９，７０，７１から半導体集積回路５１の内部へ出力されるＩ／Ｏセル内部出力信号を出力するための線である。 Furthermore, the delay measurement circuit 57 is connected to a start point line 65 and an end point line 66 serving as a start point and an end point of the output. In the test mode, the input line 92 of the selector 59 connected to the first I / O cell 67 and the start point line 65 of the delay measurement circuit 57 are connected. Also, the I / O cell internal output signals 77, 78, 79, 80 and the endpoint line 66 connected to each I / O cell are transmitted from the I / O cells 67, 68, 69, 70, 71 to the semiconductor integrated circuit 51. This is a line for outputting an I / O cell internal output signal to be output to the inside.
　上述したように、遅延測定テストモード設定回路６４によりテストモードがアクティブになると、遅延測定回路５７は、スタートポイント線６５を通じて、テストトリガを発する。スタートポイント線６５を通じてセレクタ５９に入力されたテストトリガとしての内部出力信号は、１番目のＩ／Ｏセル６７に接続された入力線９２を通じて、Ｉ／Ｏセル６７に伝えられる。以下、次のように内部出力信号が伝達可能なチェーン接続が成立する。 As described above, when the test mode is activated by the delay measurement test mode setting circuit 64, the delay measurement circuit 57 generates a test trigger through the start point line 65. An internal output signal as a test trigger input to the selector 59 through the start point line 65 is transmitted to the I / O cell 67 through the input line 92 connected to the first I / O cell 67. Hereinafter, a chain connection capable of transmitting an internal output signal is established as follows.
　セレクタ６０→入力線９３→Ｉ／Ｏセル６８→セレクタ６１→入力線９４→Ｉ／Ｏセル６９→セレクタ６２→入力線９５→Ｉ／Ｏセル７０→セレクタ６３→入力線９６→Ｉ／Ｏセル７１ Selector 60 → input line 93 → I / O cell 68 → selector 61 → input line 94 → I / O cell 69 → selector 62 → input line 95 → I / O cell 70 → selector 63 → input line 96 → I / O cell 71
　最終のＩ／Ｏセル７１の内部出力信号（テストトリガ）は、チェーン接続の末尾として、エンドポイント線６６を通じて遅延測定回路５７に入力される。遅延測定回路５７から発せられたテストトリガは、外部配線負荷の影響を受けながらチェーン接続上を伝搬し、最後に遅延測定回路５７のエンドポイント線６６からの入力へ到達する。遅延測定回路５７は、動作クロック９７の分解能の限度で、スタートポイント線６５を通じてテストトリガが発せられた時刻から、エンドポイント線９６を通じてテストトリガが帰還してくるまでの時間をカウントする遅延測定を行い、その測定結果をカウント値としてドライブ能力判定回路９８へ通知する。尚、遅延測定回路５７は、ドライブ能力判定回路９８からの起動トリガによって、テストトリガをスタートポイント線６５を通じてセレクタ５９へ発する。 The internal output signal (test trigger) of the final I / O cell 71 is input to the delay measurement circuit 57 through the endpoint line 66 as the end of the chain connection. The test trigger generated from the delay measurement circuit 57 propagates on the chain connection while being influenced by the external wiring load, and finally reaches the input from the endpoint line 66 of the delay measurement circuit 57. The delay measurement circuit 57 performs delay measurement that counts the time from when the test trigger is issued through the start point line 65 to when the test trigger is fed back through the end point line 96 within the limit of the resolution of the operation clock 97. The measurement result is notified to the drive capability determination circuit 98 as a count value. The delay measurement circuit 57 issues a test trigger to the selector 59 through the start point line 65 in response to the activation trigger from the drive capability determination circuit 98.
　本実施形態において、ドライブ能力判定回路９８は、予め与えられた基準パラメータ（基準値）と、遅延測定回路５７による測定結果（カウント値）とを比較する。そして、測定結果が基準値より大きい場合、ドライブ能力判定回路９８は、ドライブ能力制御回路５５のドライブ能力設定を１段階高く引き上げる。一方、測定結果が基準値より小さい場合は、ドライブ能力判定回路９８は、ドライブ能力制御回路５５のドライブ能力設定を１段階引き下げる。 In this embodiment, the drive capability determination circuit 98 compares a reference parameter (reference value) given in advance with a measurement result (count value) by the delay measurement circuit 57. When the measurement result is larger than the reference value, the drive capability determination circuit 98 increases the drive capability setting of the drive capability control circuit 55 by one step. On the other hand, when the measurement result is smaller than the reference value, the drive capability determination circuit 98 lowers the drive capability setting of the drive capability control circuit 55 by one step.
　そして、ドライブ能力判定回路９８は、所定時間経過後、起動トリガにより遅延測定回路５７を再起動し、遅延の測定終了を待ち、再度比較する。このような比較動作を繰り返し、最終的に基準値と測定結果の差が最小になった場合、調整動作を終了する。 Then, after a predetermined time elapses, the drive capability determination circuit 98 restarts the delay measurement circuit 57 by a start trigger, waits for the end of delay measurement, and compares again. Such a comparison operation is repeated, and when the difference between the reference value and the measurement result is finally minimized, the adjustment operation is terminated.
　第２の実施形態によれば、一連の調整制御を、第１実施形態のようなＣＰＵのソフトウェアに依存することなく、ハードウェア回路による制御のみで一貫して行うことが可能となる。 According to the second embodiment, a series of adjustment control can be performed consistently only by control by a hardware circuit without depending on CPU software as in the first embodiment.
　上述したように、本発明の半導体集積回路によれば、テストモード時において、複数のＩ／Ｏセルがチェーン状に接続される。したがって、Ｉ／Ｏセル一つ分の遅延量ではなく、全Ｉ／Ｏセルの遅延量の総和が計測され、遅延量の絶対値を大きく取ることが可能となる。したがって、半導体集積回路内部で使用するクロック周波数で動作する遅延測定回路において、十分な分解能が得られるようになり、一定の測定精度が得られるようになる。また、半導体集積回路チップを基板実装した時点の条件で伝搬遅延が自己診断できるため、基盤配線のインピーダンスを包括したドライブ能力調整が図れる。 As described above, according to the semiconductor integrated circuit of the present invention, a plurality of I / O cells are connected in a chain shape in the test mode. Therefore, not the delay amount of one I / O cell but the total sum of delay amounts of all I / O cells is measured, and the absolute value of the delay amount can be increased. Therefore, in the delay measurement circuit that operates at the clock frequency used inside the semiconductor integrated circuit, sufficient resolution can be obtained and a certain measurement accuracy can be obtained. In addition, since the propagation delay can be self-diagnosed under the conditions at the time when the semiconductor integrated circuit chip is mounted on the substrate, it is possible to adjust the driving ability including the impedance of the base wiring.
　以上、本発明の各種実施形態を説明したが、本発明は前記実施形態において示された事項に限定されず、明細書の記載、並びに周知の技術に基づいて、当業者がその変更・応用することも本発明の予定するところであり、保護を求める範囲に含まれる。 Although various embodiments of the present invention have been described above, the present invention is not limited to the matters shown in the above-described embodiments, and those skilled in the art can make modifications and applications based on the description and well-known techniques. This is also the scope of the present invention, and is included in the scope for which protection is sought.
　本出願は、２００８年６月２５日出願の日本特許出願、特願２００８－１６５９６３に基づくものであり、その内容はここに参照として取り込まれる。 This application is based on Japanese Patent Application No. 2008-165963 filed on June 25, 2008, the contents of which are incorporated herein by reference.
　本発明の半導体集積回路は、ドライブ能力の個体差ばらつきを量産検査時の選別に頼らず、基板上に実装した後でも、セルフチェックで自身の実力位置を把握し、ばらつきを補正し、最適なドライブ能力値を設定できる点で有用である。 The semiconductor integrated circuit of the present invention does not rely on the individual difference variation of the driving ability at the time of mass production inspection, and even after mounting on the substrate, it grasps its own ability position by self-check, corrects the variation, This is useful in that the drive capacity value can be set.
２１，５１　　半導体集積回路
２２，５２　　メモリデバイス
２３，５３　　Ｉ／Ｏ回路
２４　　　　　ＣＰＵ
２５，５５　　ドライブ能力制御回路
２６　　　　　設定レジスタ
２７，５７　　遅延測定回路
３４，６４　　遅延測定テストモード設定回路 21, 51 Semiconductor integrated circuit 22, 52 Memory device 23, 53 I / O circuit 24 CPU
25, 55 Drive capability control circuit 26 Setting register 27, 57 Delay measurement circuit 34, 64 Delay measurement test mode setting circuit

Claims (6)

  1. 　各々出力バッファと入力バッファを含み、外部の装置との間でデータのやり取りを行う複数の入出力要素と、
    　テストモード時に論理素子を通じて、前記複数の入出力要素をチェーン状に接続するテストモード設定回路と、
    　前記テストモード時に、チェーン状に接続された前記複数の入出力要素の総遅延値を測定する遅延測定回路と、
    　を備える半導体集積回路。     A plurality of input / output elements each including an output buffer and an input buffer for exchanging data with an external device;
    A test mode setting circuit for connecting the plurality of input / output elements in a chain through a logic element in a test mode;
    A delay measuring circuit for measuring a total delay value of the plurality of input / output elements connected in a chain in the test mode;
    A semiconductor integrated circuit comprising:
  2. 　請求項１に記載の半導体集積回路であって、
    　チェーン状に接続された複数の入出力要素の出力バッファについて、段階的にドライブ能力を変更するドライブ能力制御回路を備える半導体集積回路。     The semiconductor integrated circuit according to claim 1,
    A semiconductor integrated circuit comprising a drive capability control circuit that changes the drive capability in stages for output buffers of a plurality of input / output elements connected in a chain.
  3. 　請求項１または２に記載した半導体集積回路であって、
    　所定のプログラムに基づき、前記遅延測定回路により測定した総遅延値を読み出す演算装置を備える半導体集積回路。     A semiconductor integrated circuit according to claim 1 or 2,
    A semiconductor integrated circuit comprising an arithmetic unit that reads out a total delay value measured by the delay measurement circuit based on a predetermined program.
  4. 　請求項１または２に記載した半導体集積回路であって、
    　前記遅延測定回路により測定した総遅延値を読み出すハードウェア回路を備える半導体集積回路。     A semiconductor integrated circuit according to claim 1 or 2,
    A semiconductor integrated circuit comprising a hardware circuit for reading a total delay value measured by the delay measurement circuit.
  5. 　請求項２に記載した半導体集積回路であって、
    　前記遅延測定回路により測定した総遅延値に基づき、前記出力バッファのドライブ能力のばらつき補正を行う半導体集積回路。     A semiconductor integrated circuit according to claim 2, wherein
    A semiconductor integrated circuit that corrects variation in drive capability of the output buffer based on a total delay value measured by the delay measurement circuit.
  6. 　請求項２または５に記載した半導体集積回路を基板上に実装後、前記基板上の配線と当該半導体集積回路を接続した実際の使用環境条件において、チェーン状に接続された複数の入出力要素の総遅延値を前記遅延測定回路を用いて測定し、測定された総遅延値に基づき、前記出力バッファのドライブ能力を調整し、前記入出力要素と外部の装置との通信タイミング調整をする、Ｉ／Ｏドライブ能力調整方法。 After mounting the semiconductor integrated circuit according to claim 2 or 5 on a substrate, a plurality of input / output elements connected in a chain shape under actual use environment conditions in which the wiring on the substrate and the semiconductor integrated circuit are connected. Measuring a total delay value using the delay measurement circuit, adjusting a drive capability of the output buffer based on the measured total delay value, and adjusting a communication timing between the input / output element and an external device; / O drive capacity adjustment method.
PCT/JP2009/002373 2008-06-25 2009-05-28 Semiconductor integrated circuit and i/o drive capacity adjustment method WO2009157134A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9205267B2 (en) 2010-02-17 2015-12-08 Sorin Crm S.A.S. Apparatus and method for automatic optimization of atrioventricular delay for an active medical device

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPS63295980A (en) * 1987-05-27 1988-12-02 Nec Corp Input/output circuit
JPH01228322A (en) * 1988-03-09 1989-09-12 Nec Corp Gate array
JPH09257884A (en) * 1996-03-18 1997-10-03 Sharp Corp Integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63295980A (en) * 1987-05-27 1988-12-02 Nec Corp Input/output circuit
JPH01228322A (en) * 1988-03-09 1989-09-12 Nec Corp Gate array
JPH09257884A (en) * 1996-03-18 1997-10-03 Sharp Corp Integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9205267B2 (en) 2010-02-17 2015-12-08 Sorin Crm S.A.S. Apparatus and method for automatic optimization of atrioventricular delay for an active medical device

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