WO2009135284A1

WO2009135284A1 - Method and apparatus for converting direct current into an alternating current

Info

Publication number: WO2009135284A1
Application number: PCT/CA2008/000854
Authority: WO
Inventors: Djordje Garabandic
Original assignee: Xantrex International
Priority date: 2008-05-05
Filing date: 2008-05-05
Publication date: 2009-11-12
Also published as: EP2294685A4; EP2294685A1

Abstract

A method and apparatus for converting direct current into alternating current is disclosed. The apparatus includes a converter circuit having first and second source nodes for receiving direct current from a source and first and second load nodes for connecting a load. The circuit includes first and second switches in series between the first and second source nodes with a common first intermediate node, and third and fourth switches in series between the first and second source nodes with a common second intermediate node. A first inductor is connected between the first intermediate node and the first load node, and a second inductor is connected between the second intermediate node and the second load node. The apparatus includes a controller for causing first, second, third, and fourth switching control signals to be asserted to cause the first, second, third, and fourth switches to selectively conduct current between the first and second source nodes and the first and second load nodes to produce an alternating current, and to cause a single shunt control signal to be asserted when the switching control signals are not asserted. The apparatus includes a bidirectional current shunt connected between the first and second intermediate nodes, the current shunt including a unitary switched current path for conducting current when the shunt control signal is asserted and the switching control signals are not asserted. The current shunt is configured to bock current flow between the first and second intermediate nodes when the shunt control signal is not asserted.

Description

METHOD AND APPARATUS FOR CONVERTING DIRECT CURRENT INTO

AN ALTERNATING CURRENT

BACKGROUND OF THE INVENTION 1. Field of Invention

This invention relates generally to direct current to alternating current converters.

2. Description of Related Art Direct current to alternating current (DC/AC) converters generally receive electrical energy from a direct current (DC) source and employ switches to convert the DC into alternating current (AC) for powering a load. The DC source may be a photovoltaic panel or a fuel cell, for example. The load may include common loads such as motors, lighting components, or other electrical appliances. Alternatively the DC/AC converter may be connected to provide power to an AC power grid.

Various converter circuit configurations may be used to implement DC/AC converters. In one circuit configuration pairs of series-connected semiconductor switches are connected in parallel with the DC source to form a bridge circuit. An AC load is connected between respective common nodes of the series-connected switch pairs. The semiconductor switches may be switched in response to high-frequency pulse width modulated control signals received at respective control inputs of the switches. The control signals generally cause the semiconductor switches to conduct current in a time sequence that produces a substantially sinusoidal AC waveform at the load.

In DC/AC converters, average power flow is generally from the DC source to the AC load, which is known as inverter mode operation. However, if the load includes capacitive or inductive components, the DC/AC converter is required to also receive reactive power back from the load, in which case the converter must also be able to operate in a rectifier mode of operation. Generally, when receiving reactive power, conventional bridge circuits return reactive currents back to the source through anti-parallel diodes connected across each of the semiconductor switches. However, returning current to the source through anti-parallel diodes may result in common mode signals at the switching frequency appearing at the DC source. This can cause the DC/AC converter to generate electromagnetic interference and/or produce hazardous voltages at the DC source. As described in US Patent 7,046,534 to Schmidt et al. electromagnetic compatibility (EMC) may be improved by configuring the converter circuit to prevent common mode signals at the switching frequency from appearing at the source, while conversion efficiency may be improved by preventing current flow back to the source when the semiconductor switches are not conducting.

There remains a need for converter circuit configurations that are able to efficiently handle reactive power returned from the load.

SUMMARY OF THE INVENTION In accordance with one aspect of the invention there is provided a method for converting a direct current into alternating current in a converter circuit having first and second source nodes for receiving direct current from a direct current source and having first and second load nodes operable to be connected to a load. The converter circuit also includes first and second switches connected in series between the first and second source nodes and having a common first intermediate node therebetween and third and fourth switches connected in series between the first and second source nodes and having a common second intermediate node therebetween. The converter circuit also includes a first inductor connected between the first intermediate node and the first load node, and a second inductor connected between the second intermediate node and the second load node. The method involves causing the first, second, third, and fourth switches to selectively conduct current in response to assertion of respective first, second, third, and fourth switching control signals such that current flows between the first and second source nodes and the first and second load nodes to produce alternating current at the first and second load nodes. The method also involves causing a single shunt control signal to be asserted when the first, second, third, and fourth switching control signals are not asserted. The method further involves causing current to flow through a unitary switched current path in a bidirectional current shunt when the single shunt control signal is asserted and when the first, second, third, and fourth switching control signals are not asserted, the bidirectional current shunt being connected between the first and second intermediate nodes, and causing the current shunt to block current flow between the first and second intermediate nodes when the single shunt control signal is not asserted.

Causing current to flow through the unitary switched current path may involve causing the unitary switched current path to selectively conduct current from a first shunt node to a second shunt node in response to the single shunt control signal, and the current shunt may include a first unidirectional current path including a first diode connected to conduct current between the first intermediate node and the first shunt node and a second diode connected to conduct current between the second shunt node and the second intermediate node, and a second unidirectional current path including a third diode connected to conduct current between the second intermediate node and the first shunt node and a fourth diode connected to conduct current between the second shunt node and the first intermediate node, such that current flows through the current shunt along one of the first unidirectional current path and the second unidirectional current path when the single shunt control signal is asserted, and current flow through the current shunt is blocked when the single shunt control signal is not asserted. -A-

Causing current to flow through the unitary switched current path may involve causing a semiconductor switch to conduct current in response to assertion of the single shunt control signal.

The method may involve producing the first, second, third and fourth switching control signals and the single shunt control signal.

Producing the first, second, third and fourth switching control signals may involve producing first, second, third and fourth pulse width modulated switching control signals.

Producing the shunt control signal may involve causing the first, second, third, and fourth switching control signals and the shunt control signal to be in a non-asserted state for a dead time period before causing the shunt control signal to be asserted, the dead time period being of sufficient duration to cause the first, second, third, and fourth switches to be in a non-conducting state before causing the unitary switched current path to conduct current.

The method may involve receiving a reference signal representing a desired output voltage waveform, and producing the first, second, third, and fourth switching control signals and the shunt control signal may involve producing first, second, third, and fourth switching control signals and the shunt control signal in response to the reference signal.

The method may involve producing the reference signal.

Producing the reference signal may involve producing a sinusoidal reference signal having a frequency defining a desired frequency of an output voltage waveform across the first and second load nodes. The load may include a reactive load that causes the output current waveform at the first and second load nodes to be out of phase with the output voltage waveform such that reactive power may be received back from the load at the first and second load nodes when an instantaneous output voltage and output current have opposite polarity, and during positive half cycles of the output voltage waveform, when the output current is negative and when the single shunt control signal is asserted, current flows from the first load node through the first inductor to the first intermediate node, through the current shunt to the second intermediate node, and through the second inductor to the second load node, and when the single shunt control signal is not asserted, current flows from the first load node through the first inductor to the first intermediate node, through an anti-parallel diode connected across the first switch and back to the first source node, and from the second source node through an anti-parallel diode connected across the fourth switch, and through the second inductor to the second load node, and during negative half cycles of the output voltage waveform, when the output current is positive and when the shunt control signal is asserted, current flows from the second load node through the second inductor to the second intermediate node, through the current shunt to the first intermediate node, and through the first inductor to the first load node, and when the shunt control signal is not asserted, current flows from the second load node through the second inductor to the second intermediate node, through an anti-parallel diode connected across the third switch and back to the first source node, and from the second source node through an anti-parallel diode connected across the second switch, and through the first inductor to the first load node.

The load may include a power grid load and the method may further involve receiving a reference signal representing a grid voltage waveform of the power grid across the first and second load nodes and producing the first, second, third, and fourth switching control signals and the shunt control signal may involve producing first, second, third, and fourth switching control signals and the shunt control signal in response to the reference signal to cause an output current to be supplied to the power grid substantially in phase with the grid voltage waveform.

The load may include a power grid load and the method may further involve receiving a signal representing a grid voltage waveform of the power grid across the first and second load nodes and producing a phase shifted reference signal in response to receiving the signal representing the grid voltage waveform, and producing the first, second, third, and fourth switching control signals and the shunt control signal may involve producing first, second, third, and fourth switching control signals and the shunt control signal in response to the phase shifted reference signal to cause an output current to be supplied to the power grid out of phase with the grid voltage waveform.

In accordance with another aspect of the invention there is provided a direct current to alternating current converter apparatus. The apparatus includes a converter circuit having first and second source nodes for receiving direct current from a direct current source and having first and second load nodes operable to be connected to a load. The converter circuit includes first and second switches connected in series between the first and second source nodes and has a common first intermediate node therebetween. The converter circuit also includes third and fourth switches connected in series between the first and second source nodes and having a common second intermediate node therebetween. The converter circuit further includes a first inductor connected between the first intermediate node and the first load node, and a second inductor connected between the second intermediate node and the second load node. The apparatus also includes a controller operably configured to cause first, second, third, and fourth switching control signals to be asserted to cause the first, second, third, and fourth switches to selectively conduct current such that current flows between the first and second source nodes and the first and second load nodes to produce alternating current at the first and second load nodes. The controller is also operably configured to cause a single shunt control signal to be asserted when the first, second, third, and fourth switching control signals are not asserted. The apparatus also includes a bidirectional current shunt connected between the first and second intermediate nodes, the current shunt including a unitary switched current path operably configured to conduct current when the single shunt control signal is asserted and when the first, second, third, and fourth switching control signals are not asserted. The current shunt is operably configured to bock current flow between the first and second intermediate nodes when the single shunt control signal is not asserted.

The unitary switched current path may be connected between a first shunt node and a second shunt node and the current shunt may include a first unidirectional current path including a first diode connected to conduct current between the first intermediate node and the first shunt node and a second diode connected to conduct current between the second shunt node and the second intermediate node, and the current shunt may include a second unidirectional current path including a third diode connected to conduct current between the second intermediate node and the first shunt node and a fourth diode connected to conduct current between the second shunt node and the first intermediate node such that current flows through the current shunt along one of the first unidirectional current path and the second unidirectional current path when the single shunt control signal is asserted, and current flow through the current shunt is blocked when the single shunt control signal is not asserted.

The unitary switched current path may include a semiconductor switch.

The controller may be operably configured to produce the first, second, third and fourth switching control signals and the single shunt control signal. The controller may be operably configured to produce first, second, third and fourth pulse width modulated switching control signals.

The controller may be operably configured to produce the shunt control signal by causing the first, second, third, and fourth switching control signals and the shunt control signal to be in a non-asserted state for a dead time period before causing the shunt control signal to be asserted, the dead time period being of sufficient duration to cause the first, second, third, and fourth switches to be in a non-conducting state before causing the unitary switched current path to conduct current.

The controller may be operably configured to receive a reference signal representing a desired output voltage waveform and to produce the first, second, third, and fourth switching control signals and the shunt control signal in response to the reference signal.

The controller may be operably configured to produce the reference signal.

The controller may be operably configured to produce the reference signal by producing a sinusoidal reference signal having a frequency defining a desired frequency of an output voltage waveform across the first and second load nodes.

The load may include a reactive load that causes the output current waveform at the first and second load nodes to be out of phase with the output voltage waveform such that reactive power is received back from the load at the first and second load nodes when an instantaneous output voltage and output current have opposite polarity, and the converter circuit may include a first anti-parallel diode connected across the first switch, a second anti-parallel diode connected across the second switch, a third anti-parallel diode connected across the third switch, and a fourth anti-parallel diode connected across the fourth switch, and during positive half cycles of the output voltage waveform, when the output current is negative and when the single shunt control signal is asserted, current flows from the first load node through the first inductor to the first intermediate node, through the current shunt to the second intermediate node, and through the second inductor to the second load node, and when the single shunt control signal is not asserted, current flows from the first load node through the first inductor to the first intermediate node, through the first anti-parallel diode and back to the first source node, and from the second source node through the fourth anti-parallel diode, and through the second inductor to the second load node, and during negative half cycles of the output voltage waveform, when the output current is positive and when the shunt control signal is asserted, current flows from the second load node through the second inductor to the second intermediate node, through the current shunt to the first intermediate node, and through the first inductor to the first load node, and when the shunt control signal is not asserted, current flows from the second load node through the second inductor to the second intermediate node, through the third anti-parallel diode and back to the first source node, and from the second source node through the second anti-parallel diode, and through the first inductor to the first load node.

The load may include a power grid load and the controller may be operably configured to receive a reference signal representing a grid voltage waveform of the power grid across the first and second load nodes and to produce the first, second, third, and fourth switching control signals and the shunt control signal in response to the reference signal to cause an output current to be supplied to the power grid substantially in phase with the grid voltage waveform.

The load may include a power grid load and the controller may be operably configured to receive a signal representing a grid voltage waveform of the power grid across the first and second load nodes, to produce a phase shifted reference signal in response to receiving the signal representing the grid voltage waveform, and to produce the first, second, third, and fourth switching control signals and the shunt control signal in response to the phase shifted reference signal to cause an output current to be supplied to the power grid out of phase with the grid voltage waveform.

In accordance with another aspect of the invention there is provided an apparatus for converting a direct current into alternating current in a converter circuit having first and second source nodes for receiving direct current from a direct current source and having first and second load nodes operable to be connected to a load. The converter circuit includes first and second switches connected in series between the first and second source nodes and has a common first intermediate node therebetween. The converter circuit also includes third and fourth switches connected in series between the first and second source nodes and having a common second intermediate node therebetween. The converter circuit further includes a first inductor connected between the first intermediate node and the first load node, and a second inductor connected between the second intermediate node and the second load node. The apparatus includes provisions for causing the first, second, third, and fourth switches to selectively conduct current in response to assertion of respective first, second, third, and fourth switching control signals such that current flows between the first and second source nodes and the first and second load nodes to produce alternating current at the first and second load nodes. The apparatus also includes provisions for causing a single shunt control signal to be asserted when the first, second, third, and fourth switching control signals are not asserted. The apparatus further includes provisions for causing current to flow through a unitary switched current path in a bidirectional current shunt when the single shunt control signal is asserted and when the first, second, third, and fourth switching control signals are not asserted, the bidirectional current shunt being connected between the first and second intermediate nodes. The apparatus also includes provisions for causing the current shunt to block current flow between the first and second intermediate nodes when the single shunt control signal is not asserted.

The provisions for causing current to flow through the unitary switched current path may include provisions for causing the unitary switched current path to selectively conduct current from a first shunt node to a second shunt node in response to the single shunt control signal, and the current shunt may include a first unidirectional current path including a first diode connected to conduct current between the first intermediate node and the first shunt node and a second diode connected to conduct current between the second shunt node and the second intermediate node, and the current shunt may include a second unidirectional current path including a third diode connected to conduct current between the second intermediate node and the first shunt node and a fourth diode connected to conduct current between the second shunt node and the first intermediate node, such that current flows through the current shunt along one of the first unidirectional current path and the second unidirectional current path when the single shunt control signal may be asserted, and current flow through the current shunt is blocked when the single shunt control signal is not asserted.

The provisions for causing current to flow through the unitary switched current path may include provisions for causing a semiconductor switch to conduct current in response to assertion of the single shunt control signal.

The apparatus may include provisions for producing the first, second, third and fourth switching control signals and the single shunt control signal. The provisions for producing the first, second, third and fourth switching control signals may include provisions for producing first, second, third and fourth pulse width modulated switching control signals.

The provisions for producing the shunt control signal may include provisions for causing the first, second, third, and fourth switching control signals and the shunt control signal to be in a non-asserted state for a dead time period before causing the shunt control signal to be asserted, the dead time period being of sufficient duration to cause the first, second, third, and fourth switches to be in a non-conducting state before causing the unitary switched current path to conduct current.

The apparatus may include provisions for receiving a reference signal representing a desired output voltage waveform and the provisions for producing the first, second, third, and fourth switching control signals and the shunt control signal may include provisions for producing first, second, third, and fourth switching control signals and the shunt control signal in response to the reference signal.

The apparatus may include provisions for producing the reference signal.

The provisions for producing the reference signal may include provisions for producing a sinusoidal reference signal having a frequency defining a desired frequency of an output voltage waveform across the first and second load nodes.

The load may include a reactive load that causes the output current waveform at the first and second load nodes to be out of phase with the output voltage waveform such that reactive power may be received back from the load at the first and second load nodes when an instantaneous output voltage and output current have opposite polarity, and during positive half cycles of the output voltage waveform, when the output current is negative and when the single shunt control signal is asserted, current flows from the first load node through the first inductor to the first intermediate node, through the current shunt to the second intermediate node, and through the second inductor to the second load node, and when the single shunt control signal is not asserted, current flows from the first load node through the first inductor to the first intermediate node, through a diode connected in anti-parallel across the first switch and back to the first source node, and from the second source node through a diode connected in anti-parallel across the fourth switch, and through the second inductor to the second load node, and during negative half cycles of the output voltage waveform, when the output current is positive and when the shunt control signal is asserted, current flows from the second load node through the second inductor to the second intermediate node, through the current shunt to the first intermediate node, and through the first inductor to the first load node, and when the shunt control signal is not asserted, current flows from the second load node through the second inductor to the second intermediate node, through a diode connected in anti-parallel across the third switch and back to the first source node, and from the second source node through a diode connected in anti-parallel across the second switch, and through the first inductor to the first load node.

The load may include a power grid load and may further include provisions for receiving a reference signal representing a grid voltage waveform of the power grid across the first and second load nodes and the provisions for producing the first, second, third, and fourth switching control signals and the shunt control signal may include provisions for producing first, second, third, and fourth switching control signals and the shunt control signal in response to the reference signal to cause an output current to be supplied to the power grid substantially in phase with the grid voltage waveform. The load may include a power grid load and may further include provisions for receiving a signal representing a grid voltage waveform of the power grid across the first and second load nodes and provisions for producing a phase shifted reference signal in response to receiving the signal representing the grid voltage waveform, and the provisions for producing the first, second, third, and fourth switching control signals and the shunt control signal may include provisions for producing first, second, third, and fourth switching control signals and the shunt control signal in response to the phase shifted reference signal to cause an output current to be supplied to the power grid out of phase with the grid voltage waveform.

Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

In drawings which illustrate embodiments of the invention,

Figure 1 is a schematic diagram of an apparatus for converting a direct current into an alternating current according to a first embodiment of the invention;

Figure 2 is schematic diagram of a current shunt used in the apparatus shown in Figure 1 ;

Figure 3 is a block diagram of a processor circuit used to implement a controller for controlling the apparatus shown in Figure 1; Figure 4 is a graphical depiction of control signals produced by the controller shown in Figure 3 when operating in accordance with one embodiment if the invention;

Figure 5 is a graphical depiction of a portion of a control signal shown in

Figure 4;

Figure 6 is a graphical depiction of possible conduction states of the apparatus shown in Figure 1;

Figures 7 - 10 are a series of schematic diagrams of paths of current flow through the apparatus shown in Figure 1; and

Figure 11 is a graphical depiction of control signals produced by the controller shown in Figure 3 when operating in accordance with an alternative embodiment if the invention.

DETAILED DESCRIPTION

Referring to Figure 1 , an apparatus for converting a direct current into an alternating current in accordance with a first embodiment of the invention is shown generally at 100. The apparatus 100 includes a converter circuit 101 having first and second source nodes 102 and 104 for receiving direct current from a DC source 106, and first and second load nodes 108 and 110 operable to be connected to a load 112.

The converter circuit 101 also includes first and second switches 114 (Q1) and 116 (Q2), connected in series between the first and second source nodes 102 and 104. The first and second switches 114 and 116 have a common first intermediate node 118 therebetween. The converter circuit further includes third and fourth switches 120 (Q3) and 122 (Q4) connected in series between the first and second source nodes 102 and 104. The third and fourth switches 120 and 122 have a common second intermediate node 124 therebetween.

The first switch 114 is operable to selectively conduct current from the first source node 102 to the first intermediate node 118 in response to a first switching control signal QI_0n- The first switch 114 has an anti-parallel diode 126 connected across the first switch. The diode 126 is operable to conduct current in a direction from the first intermediate node 118 to the first source node 102 and to block current in the opposite direction.

The second switch 116 is operable to selectively conduct current from the first intermediate node 118 to the second source node 104 in response to a second switching control signal Q2_on. The second switch 116 has an anti- parallel diode 128 connected across the second switch. The diode 128 is operable to conduct current in a first direction from the second source node

110 to the first intermediate node 118 and to block current in the opposite direction.

The third switch 120 is operable to selectively conduct current from the first source node 102 to the second intermediate node 124 in response to a third switching control signal Q3_on- The third switch 120 has an anti-parallel diode 130 connected across the third switch. The diode 130 is operable to conduct current in a first direction from the second intermediate node 124 to the first source node 102 and to block current in the opposite direction.

The fourth switch 122 is operable to selectively conduct current from the second intermediate node 124 to the second source node 104 in response to a fourth switching control signal Q4_on. The fourth switch 122 has an anti- parallel diode 132 connected across the fourth switch. The diode 132 is operable to conduct current in a first direction from the second source node 104 to the second intermediate node 124 and to block current in the opposite direction.

The converter circuit 101 also includes a first inductor 134 (L1) connected between the first intermediate node 118 and the first load node 108 and a second inductor 136 (L2) connected between the second intermediate node 124 and the second load node 110. The first and second inductors 134 and 136 generally smooth the output current flowing between the first and second load nodes 108 and 110.

In this embodiment the apparatus 100 also includes a capacitor 160 (C1). The capacitor 160, together with the first and second inductors 134 and 136 provide low pass filtering of the alternating current by attenuating alternating current signal components at frequencies other than a fundamental frequency associated with the alternating current waveform. For example, a capacitance value of the capacitor 160 and inductance values of the first and second inductors 134 and 136 may be selected to provide negligible attenuation at power grid frequencies (e.g. 50Hz or 60Hz) and high attenuation of higher harmonics of the power grid frequency that would otherwise cause distortion of the output alternating current waveform. In the circuit configuration shown in Figure 1 , additional circuit components may also be included (not shown) to provide further filtering of DC source current and/or AC output current. For example, such circuit components may include a capacitor (not shown) across the source nodes 102 and 104 for filtering the DC source current.

In one embodiment the apparatus 100 may be configured as a grid-tied inverter that provides AC current to a power grid load, in which case the load 112 is the power grid, and the load nodes 108 and 110 are connected to the power grid. In other embodiments the apparatus 100 may be configured for islanded operation in which the apparatus provides AC current to a local load

112, which is not connected to a power grid. The apparatus 100 further includes a current shunt 138 connected between the first and second intermediate nodes 118 and 124. The current shunt 138 is shown in greater detail in Figure 2.

Referring to Figure 2, the current shunt 138 includes a unitary switched current path 180 that is operable to selectively conduct current in response to a single shunt control signal CS_0n- In this embodiment the unitary switched current path 180 includes a current shunt switch 182 (Q5) connected between first and second shunt nodes 184 and 186. The current shunt switch 182 is operable to conduct current from the first shunt node 184 to the second shunt node 186 in response to the single shunt control signal CS_0n.

The current shunt 138 also includes a first diode 188 (D1) connected between the first intermediate node 118 and the first shunt node 184, and a second diode 190 (D2) connected between the second shunt node 186 and the second intermediate node 124. The current shunt 138 also includes a third diode 192 (D3) connected between the second intermediate node 124 and the first shunt node 184, and a fourth diode 194 (D4) connected between the second shunt node 186 and the first intermediate node 118.

When the single shunt control signal CS_0n is asserted, the current shunt switch 182 is turned on and current flow is permitted along a first unidirectional path 119 from the first intermediate node 118, through the first diode 188, through the current shunt switch 182, and through the second diode 190 to the second intermediate node 124. The diodes 188 and 190 block current flow through the first current path 119 from the second intermediate node 124 to the first intermediate node 118. When the single shunt control signal CS_0n is asserted current flow is also permitted along a second unidirectional path 121 from the second intermediate node 124, through the third diode 192, through the current shunt switch 182, and through the fourth diode 194 to the first intermediate node 118. The diodes 192 and 194 block current flow through the first unidirectional path 119 from the first intermediate node 118 to the second intermediate node 124.

Advantageously, the current shunt 138 permits current flow through the current shunt along either the first unidirectional path 119 or the second unidirectional path 121 when the single shunt control signal CS_0n is asserted. Which of the first and second unidirectional current paths conducts current is determined by the direction of current flow through the first and second inductors 134, 136, and the load 112. When the shunt control signal CS_0n is not asserted, the current shunt switch 182 is turned off and does not conduct current and the diodes D1 - D4 block current flow in either direction between the first and second intermediate nodes 118 and 124.

Referring to Figure 1 and Figure 2, in the embodiment shown, Q1 to Q5 comprise semiconductor switches such as an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), or a junction field-effect transistor (JFET). The first switch 114 includes a control signal input 140 for receiving the first switching control signal QI_0n for controlling the conduction state of the first switch. When the first switching control signal QI_0n is asserted, the first switch 114 is switched "on" to conduct current, and when first switching control signal QI_0n is not asserted the first switch is switched "off' and conducts no more than a small leakage current. Similarly the second, third, fourth, and current shunt switches 116, 120, 122, and 182 each include respective control signal inputs 142, 144, 146, and 196 for receiving respective control signals Q2_on, Q3_on, Q4_0n, and CS_0n for controlling their conduction states. Semiconductor switches are generally available with an anti-parallel diode co-packaged together with the switch. Most semiconductor switches generally only permit current flow in one direction, and the inclusion of an anti-parallel diode facilitates bi-directional current flow through the combination of switch and anti-parallel diode. The anti-parallel diode shown connected across the current shunt switch 182 in Figure 2 may be omitted since this diode does not carry current due to the blocking action of the diodes 188 to 194.

Controller

In the embodiment shown in Figure 1 , the apparatus 100 further includes a controller 148 having a plurality of outputs 150 - 156 for generating the first, second, third and fourth switching control signals Q1_on, Q2_on, Q3_on, and Q4_0n- The outputs 150 - 156 of the controller 148 are coupled to respective control signal inputs 140, 142, 144, and 146 of the first, second, third and fourth switches 114, 116, 120, and 122. Generally the converter circuit 101 produces alternating current at the first and second load nodes 108 and 110 by causing the first, second, third, and fourth switches 114, 116, 120, and 122 to selectively conduct current between the first and second source nodes 102 and 104 and the first and second load nodes in response to asserting the first, second, third, and fourth switching control signals QI_0n, Q2_on> Q3_on, and Q4_on in a timing sequence.

The controller 148 further includes an output 158 for producing the single shunt control signal CS_0n. The controller 148 is operably configured to cause the single shunt control signal CS_0n to be asserted at the output 158 when the first, second, third, and fourth switching control signals QI_0n, Q2_on, Q3_on, and Q4_On, are not asserted. The output 158 is coupled to the control signal input 196 of the current shunt switch 182 in the current shunt 138 as shown in

Figure 2.

In one embodiment the controller 148 produces switching control signals QI_0n to Q4_on and the shunt control signal CS_0n with voltage and current levels suitable for driving the first, second, third and fourth switches 114, 116, 120, and 122 directly, and may be coupled directly to the respective control signal inputs 140 - 146, and 196. In other embodiments, the switching control signals QI_0n to Q4_on and the shunt control signal CS_0n may be logic level signals and the converter circuit 101 or the controller 148 may include driver circuitry (not shown) for converting the logic level signals into suitable control signals for driving first, second, third and fourth switches 114, 116, 120, and

122.

Referring to Figure 3, in one embodiment the controller 148 may be implemented using a processor circuit as shown generally at 200. In this embodiment the processor circuit 200 includes a microprocessor 202, a program memory 204, a random access memory (RAM) 206, and an input output port (I/O) 208, all of which are in communication with the microprocessor 202.

Program codes for directing the microprocessor 202 to carry out various functions are stored in the program memory 204, which may be implemented by a flash memory, for example.

The I/O port 208 includes an interface 210 having a first input 212 for receiving a voltage reference signal v_rβf or a grid voltage signal v_grid representing a voltage waveform of a power grid. The I/O port 208 further includes the outputs 150 - 158 for producing the switching control signals QI_0n - Q4_On and the single shunt control signal CS_0n-

The RAM 206 may include volatile and/or non-volatile memory and provides storage for operating parameters and storage for variables used during operation in accordance with the program codes.

In general, the program codes in the program memory 204 direct the microprocessor 202 to receive the reference signal v_rβf or v_gricι at the input 212 of the I/O port 208 and to produce the first, second, third, and fourth switching control signals (QI_0n - Q4_on) at the outputs 150 - 156, and the shunt control signal CS_0n at the output 158 in response to the reference signal v_ref or the grid voltage signal v_grid for controlling the switches Q1 - Q5 to cause an alternating current to be supplied to the load 112. The reference signal v_rβf may be generated externally to the processor circuit 200, for example by an external sine wave signal generator (not shown). Alternatively, the program codes in the program memory 204 may direct the microprocessor 202 to generate the reference signal internally by producing a set of digital values representing voltages defining a reference signal waveform. Such values may be generated using processor circuit timing functions that use a microprocessor clock signal as a timing reference, for example.

The processor circuit 200 may be implemented using a general purpose microprocessor, or alternatively may be implemented using a digital signal processing (DSP) processor such as the TMS320LF2407APGE processor produced by Texas Instruments of Dallas, Texas, for example. The TMS320LF2407APGE processor is optimized for digital motor control and power conversion applications and thus generally works well in this application. In other embodiments (not shown), the controller processor circuit 200 may be partly or fully implemented using a hardware circuit including analog electronic components, and/or discrete logic circuits, for example. Various other analog electronic components, and/or discrete logic circuits may be used to provide interfacing between the apparatus 100 and the processor circuit 200.

Islanded Load Operation

The operation of the apparatus 100 shown in Figure 1 to supply AC current to an islanded load 112 is described with reference to Figure 1 and Figure 4. Operation of the apparatus 100 as grid tied inverter is described later herein. In islanded load operation of the apparatus 100, the controller 148 of Figure 1 receives or generates a reference signal v_ref having a frequency and amplitude defining a desired frequency and amplitude of the AC output voltage V₀, in response to the reference signal v_rβf, the controller controls the apparatus 100 to act as a low impedance voltage source. Referring to Figure

4, the reference signal v_rΘf has a waveform as shown generally at 240. The reference signal waveform 240 has positive half cycles (one of which is shown at 242) and negative half cycles (one of which is shown at 244).

The controller 148 produces the switching control signals QI_0n to Q4_on shown at 246 and 254 and the shunt control signal CS_0n shown at 262 to cause the apparatus 100 to produce the desired AC output voltage V₀ (shown at 264) across the load nodes 108 and 110. The output voltage V₀ has a waveform having positive and negative half cycles that generally correspond to the positive and negative half cycles 242 and 244 of the reference signal 240. In islanded load operation the load 112 may be a reactive load that causes an output current i₀ (also shown at 264) that is out of phase with the output voltage waveform V₀ to be drawn from the apparatus 100. Alternatively, should the load 112 be substantially resistive, the output current i₀ drawn from the apparatus 100 will be substantially in phase with the output voltage waveform V₀.

In general, the positive voltage half cycle of the output voltage waveform V₀ is produced by causing the first and fourth switching control signals QI_0n and Q4_On and the shunt control signal CS_0n to be asserted in such a way to effect a plurality of positive half cycle switching sub-cycles. In general, the first and fourth switching control signals QI_0n and Q4_on comprise a plurality of pulses that are width-modulated to supply current to the load in such a way that the output voltage waveform V₀ conforms to the reference voltage waveform V_ref. The first and fourth switching control signals QI_0n and Q4_on control the respective conduction states of the first and fourth switches 114 and 120 during the positive half cycle of the output voltage waveform. In this embodiment the switching control signals QI_0n and Q4_on have substantially the same waveforms and accordingly the first and fourth switches 114 and

122 are switched substantially simultaneously. As indicated above, the actual drive signals for driving respective control signal inputs 140 and 146 of the first and fourth switches 114 and 122 may be level shifted, as required, for driving the particular switching devices Q1 - Q4 that are used in the apparatus 100. A waveform of the switching control signals QI_0n and Q4_on is shown at 246 in Figure 4. The switching control signals QI_0n and Q4_on include a plurality of positive half cycle switching sub-cycles 248. During each sub-cycle 248, the switching control signals QI_0n and Q4_on are in an asserted state for first time periods, such as shown at 250, and in a non-asserted state for second time periods, such as shown at 252.

The negative voltage half cycle of the output voltage waveform V₀ is produced by causing the second and third switching control signals Q2_on and Q3_on and the shunt control signal CS_0n to be asserted in such a way to effect a plurality of negative half cycle switching sub-cycles.

The second and third switching control signals Q2_on and Q3_on control the respective conduction states of the second switch 116 and the third switch 120 during the negative half cycle of the output voltage waveform V₀, and in this embodiment the switching control signals Q2_on and Q3_on have substantially the same waveforms and accordingly the second and third switches 116 and 120 are switched substantially simultaneously. A waveform of the switching control signals Q2_0n and Q3_on is shown at 254 in Figure 4. The switching control signals Q2_on and Q3_on include a plurality of negative half cycle switching sub-cycles 256. During each sub-cycle 256, the switching control signals Q2_on and Q3_on are in an asserted state for first time periods, such as shown at 258, and in a non-asserted state for second time periods, such as shown at 260.

In this embodiment, a duty cycle of the switching control signals QI_0n - Q4_on is pulse width modulated such that the first time periods 250 and 258 of the respective switching sub-cycles 248 and 256 occupy progressively greater proportions of the sub-cycle than the second time periods 252 and 260, towards respective peaks 266 and 267 of the output current waveform i₀ shown at 264. The first time periods 250 and 258 also occupy progressively lesser proportions of the sub-cycle than the second time periods 252 and 260 as the output current waveform i₀ approaches zero crossings (as shown at

268 and 269) of the output current waveform i₀.

A waveform of the shunt control signal CS_0n is shown at 262. During positive half cycles the shunt control signal CS_0n is asserted when the switching control signals QI_0n and Q4_on are not asserted, and during negative half cycles the shunt control signal CS_0n is asserted when the switching control signals Q2_on and Q3_on are not asserted. Accordingly, the shunt control signal

CS_0n is only asserted when the first, second, third, and fourth switching control signals QI_0n, Q2_on, Q3_on- and Q4_on are not asserted.

Referring to Figure 5, a portion of the waveforms of the switching control signals QI_0n and Q4_on and the shunt control signal C_0n are shown in greater detail at 280 and 282 respectively. Referring back to Figure 1, when the switching control signals QI_0n and Q4_on are asserted, the first and fourth switches 114 and 122 conduct current, and when the shunt control signal CS_0n is asserted, the current shunt 138 conducts current. If the first and fourth switches 114 and 122 are conducting while the current shunt 138 is also conducting, a short circuit will appear across the source nodes 102 and 104, possibly resulting in damage or destruction of Q1 , Q4, damage to the current shunt 138, and/or damage to the DC source 106. Accordingly, to ensure that the first and fourth switches 114 and 122 are not conducting when the current shunt 138 is conducting, the controller 148 causes the control signals Q1_Om Q4_on, and CS_0n to all be in a non-asserted state for a dead time period t_d (shown in Figure 5), before causing the shunt control signal CS_0n to be asserted. The dead time period t_d is of sufficient duration (perhaps about

2μsec, for example), to allow the first and fourth switches 114 and 122 to switch off completely before permitting current flow through the unitary switched current path 180 in the current shunt 138. Similarly the controller also causes the control signals Q2_on, Q3_on, and CS_0n to all be in a non- asserted state for a dead time period (not shown), such that the second and third switches 116 and 120 are never in a conducting state while the current shunt 138 is also in a conducting state.

In the embodiment shown, power is drawn by the load 112 from the apparatus 100 at a non-unity power factor and thus the load draws an output current from the apparatus 100 that is out of phase with the output voltage V₀ (shown at 264 in Figure 4). When both the output voltage V₀ and the output current i₀ are positive or both the output voltage V₀ and the output current i₀ are negative (i.e. time periods 1 and 3 of the waveform 264) active power flows from the DC source 106 to the load 112. When the output voltage V₀ is positive and the output current i₀ is negative (i.e. time period 4) or the output voltage V₀ is negative and the output current i₀ is positive (i.e. time period 2) reactive power is returned from the load 112 and feeds back into the load nodes 108 and 110. Referring to Figure 6, the time periods 1 - 4 are graphically represented as quadrants on a graph 290, in which the output voltage V₀ is plotted on the x-axis and the output current i₀ is plotted on the y axis. Quadrants 1 and 3 of the graph 290 represent active power transfer, while quadrants 2 and 4 represent reactive power being returned from the load. When an inverter apparatus, such as the apparatus 100, operates in all four quadrants, the inverter is said to have "four quadrant operation". The operation of the apparatus 100 is further described with reference to Figures 7 to 10, Figure 4, and Figure 1.

Referring to Figure 4, during the first time periods 250 of each positive half cycle switching sub-cycle 248 shown in Figure 4 the switching control signals

Q2_On and Q3_on cause the second and third switches 116 and 120 to be switched off (i.e. not conducting current) while the switching control signals QI_0n and Q4_on cause the first and fourth switches 114 and 122 to be switched on for conducting current. Referring to Figure 7, active power is supplied to the load 112 during the positive half cycle (i.e. quadrant 1 operation), and current flows along a path 300 from the first source node 102, through the first switch 114, through the first inductor 134, to the first load node 108, and from the second load node 110, through the second inductor 136, and through the fourth switch 122 to the second source node 104.

Referring to Figure 8, if reactive power is received back from the load 112 during the positive half cycle (i.e. quadrant 4 operation), during the first time periods 250 current flows along a path 302 from the first load node 108, through the first inductor 134, through the first diode 114, to the first source node 102, and from the second source node 104, through the diode 132, and through the second inductor 136 to the second load node 110.

During the second time periods 252 of each positive half cycle switching sub- cycle 248 shown in Figure 4, the shunt control signal CS_0n is asserted to cause the current shunt 138 to conduct current in either direction between the first and the second intermediate nodes 118 and 124. Referring back to Figure 7, during the second time periods 252 (shown in Figure 4), the first and fourth switches 114 and 120 are switched off thus interrupting the flow of current from the source except for a small leakage current through the first and fourth switches 114 and 122. However, the first and second inductors

134 and 136 act to oppose changes in current flow, and current continues to flow into the first load node 108 and back from the second load node 110, and is shunted through the current shunt. Thus, when active power is supplied to the load 112 during the positive half cycle (i.e. quadrant 1 operation), current flows along a path 304 from the second load node 110 through the second inductor 136 to the second intermediate node 124, through the current shunt

138 to the first intermediate node 118, and through the first inductor 134 to the first load node 108.

Referring back to Figure 8, if reactive power is received back from the load during the positive half cycle (i.e. quadrant 4 operation), during the second time periods 252, current flows along a path 306 from the first load node 108, through the first inductor 134 to the first intermediate node 118, through the current shunt to the second intermediate node 124, and through the second inductor 136 to the second load node 110.

During the first time periods 258 (shown in Figure 4) of each negative half cycle switching sub-cycle 244 shown in Figure 4 the switching control signals Q1_On and Q4_on cause the first and fourth switches 114 and 122 to be switched off (i.e. not conducting current) while the switching control signals Q2_on and Q3_on are asserted to cause the second and third switches 116 and 120 to be switched on for conducting current. Referring to Figure 9, active power is supplied to the load 112 during the negative half cycle (i.e. quadrant 3 operation), current flows along a path 308 from the first source node 102, through the third switch 120, through the second inductor 136, to the second load node 110, and from the first load node 108, through the first inductor 134, and through the second switch 116 to the second source node 104.

Referring to Figure 10, if reactive power is received from the load 112 during the negative half cycle (i.e. quadrant 2 operation), during the first time periods 258 current flows along a current path 310 from the second load node 110, through the second inductor 136, through the third diode 130, to the first source node 102, and from the second source node 104, through the second diode 128, and through the first inductor 134 to the first load node 108.

During the second time periods 260 (shown in Figure 4) of each negative half cycle switching sub-cycle, the shunt control signal CS_0n is asserted to cause the current shunt 138 to conduct current in either direction between the first and the second intermediate nodes 118 and 124. Referring back to Figure 9, during the second time periods 260 shown in Figure 4, the second and third switches 116 and 120 are switched off thus interrupting the flow of current from the source except for a small leakage current through the second and third switches. However, the first and second inductors 134 and 136 act to oppose changes in current flow, and current continues to flow into the second load node 110 and back from the first load node 108, and is shunted through the current shunt 138. Thus, when active power is supplied to the load during the negative half cycle (i.e. quadrant 3 operation), current flows along a current path 312 from the first load node 108, through the first inductor 134 to the first intermediate node 118, through the current shunt to the second intermediate node 124, and through the second inductor 136 to the second load node 110.

Referring back to Figure 10, if reactive power is received from the load during the negative half cycle (i.e. quadrant 2 operation), during the second time periods 260 current flows along a path 314 from the second load node 110, through the second inductor 136 to the second intermediate node 124, through the current shunt 138 to the first intermediate node 118, and through the first inductor 134 to the first load node 108.

The current shunt 138 thus provides a path for current that flows during the second time periods 252 and 260 while active power is being supplied to the load 112, and for current that flows while reactive power is being received back from the load during the second time periods. Consequently current does not flow back to the source through the anti-parallel diodes 126 - 132 during the second time periods 252 and 260. Advantageously, because the current shunt 138 is operable to conduct current in either direction between the first and second intermediate nodes 118 and 124 when the shunt control signal CS_0n is asserted, reactive power returned from the load is accommodated when the first, second, third, and fourth switches 114, 116, 120, and 122 are all switched off.

An instantaneous amplitude of the of the output current waveform i₀ (shown at 264 in Figure 4) is proportional to the time for which the respective switching control signals QI_0n and Q4_on (during the positive voltage half cycle) or Q2_on, and Q3_On (during the negative voltage half cycle) are asserted. At the peak

266 of the positive half cycle of the output current waveform i₀, the switching control signals QI_0n and Q4_on are predominantly in an asserted state, while proximate a zero crossing point 268 between the positive and negative half cycles of the output current waveform i₀, the respective switching control signals Q2_on, and Q3_on are predominantly in a non-asserted state. Similarly, at the peak 267 of the negative half cycle of the output current waveform i₀, the switching control signals Q2_on and Q3_on are predominantly in an asserted state, while proximate a zero crossing point 269 between the positive and negative half cycles of the output current waveform i₀, the respective switching control signals QI_0n, and Q4_on are predominantly in a non-asserted state.

The first and second inductors 134 and 136 resist changes in current flow and thus smooth the output current waveform to produce a smooth generally sinusoidal output current waveform i₀ at the load nodes 108 and 110 having smooth positive and negative half cycles. The first and second inductors 134 and 136 act as a filter to produce a generally smooth sinusoidal current waveform i₀ that would otherwise include output current waveform discontinuities due to the switching sub-cycles. Referring back to Figure 1 , in the circuit configuration shown, when the first second, third, and fourth switches 114, 116, 120, and 122 are all switched off, the DC source 106 is effectively isolated from the load 112 and current flows through the current shunt 138. Advantageously this isolation of the DC source 106 from the load 112 prevents common mode voltages at the switching frequency from appearing at the source, thereby providing improved electromagnetic performance and improved electrical safety at the source. The current shunt 138 also reduces instances when current flows back to the DC source 106 through the anti-parallel diodes 126 - 132, thereby improving an overall conversion efficiency of the apparatus 100.

Grid-tied operation

Still referring to Figure 1 , in grid-tied operation of the apparatus 100, the load nodes 108 and 110 of the apparatus 100 are connected to a power grid. Generally, the power grid acts as a low impedance voltage source, and the apparatus 100 is controlled to act as a current source for supplying an output current to the power grid. Utility companies generally attempt to supply power at unity power factor, and in such a case the controller 148 is configured to produce switching control signals that cause the apparatus 100 to produce an output current waveform that is in phase with the grid voltage. However the controller 148 may also be configured to produce switching control signals that cause the apparatus 100 to produce an output current waveform that is out of phase with the grid voltage to provide some compensation for a non- unity power factor of the power grid, should this be required.

In grid-tied operation, the apparatus 100 further includes a voltage sensor 162 connected between the first and second load nodes 108 and 110 for sensing the grid voltage appearing across the first and second load nodes. The voltage sensor 162 produces a grid voltage signal v_griC| having a suitable amplitude for coupling to the input 212 of the I/O port 208 shown in Figure 3 and having a frequency and phase corresponding to the power grid voltage waveform at the load nodes 108 and 110.

Referring to Figure 11 , the operation of the apparatus 100 for supplying power to the power grid is described for the case of non-unity power factor operation.

The grid voltage signal v_grιd is shown at 340. The I/O port 208 of the processor circuit 200 (shown in Figure 3) receives the grid voltage signal at the input 212 and produces a reference signal v_rβf (shown at 340 in Figure 11) that is phase shifted with respect to the grid voltage signal v_gnd by a phase angle of φ degrees, as shown at 382. In Figure 11 , the phase angle φ is positive, but in general the phase angle φ may be positive or negative, depending on whether compensation is required for loads with a leading or lagging power factor.

In grid-tied operation, the reference signal waveform v_ref (shown at 340) represents a desired output current waveform rather than a desired output voltage waveform, and the switching control signals QI_0n to Q4_on and the shunt control signal CS_0n are respectively asserted to produce a desired output current i₀ (shown at 350). The waveforms of the switching control signals Q1_on and Q4_on are shown at 344 and include a plurality of positive half cycle switching sub-cycles 352. During each sub-cycle 352, the switching control signals QI_0n and Q4_on are in an asserted state for first time periods, such as shown at 354, and in a non-asserted state for second time periods, such as shown at 356. The waveforms of the switching control signals Q2_on and Q3_on are shown at 346 and include a plurality of negative half cycle switching sub-cycles 360. During each sub-cycle 360, the switching control signals Q2_on and Q3_on are in an asserted state for first time periods, such as shown at 362, and in a non-asserted state for second time periods, such as shown at 364. The waveform of the single shunt control signal CS_0n is shown at 348 and is asserted only when the switching control signals QI_0n to Q4_on are not asserted, as descried earlier in reference to islanded load operation. An instantaneous amplitude of the of the output current waveform i₀ (shown at 350 in Figure 11) is proportional to the time for which the respective switching control signals QI_0n and Q4_on (during the positive voltage half cycle of v_rΘf) or Q2_on, and Q3_on (during the negative voltage half cycle of v_rΘf) are asserted. At a peak 352 of the positive half cycle of the output current waveform i₀, the switching control signals Q1_on and Q4_0n are predominantly in an asserted state, while proximate a zero crossing point 354 between the positive and negative half cycles of the output current waveform i₀, the respective switching control signals Q2_on, and Q3_on are predominantly in a non-asserted state.

Similarly, at the peak 356 of the negative half cycle of the output current waveform i₀, the switching control signals Q2_0n and Q3_on are predominantly in an asserted state, while proximate a zero crossing point 358 between the positive and negative half cycles of the output current waveform i₀, the respective switching control signals QI_0n, and Q4_0n are predominantly in a non-asserted state.

Since in grid-tied operation the apparatus 100 acts as a current source, power flow is always to the power grid, and reactive current is not received back from the power grid. Accordingly, in grid-tied operation current flows along the paths 300 and 304 shown in Figure 7 and paths 308 and 312 shown Figure 9 and as described earlier in connection with islanded load operation.

In cases where it is desired to produce the output current waveform i₀ in phase with the power grid voltage, the phase angle φ in Figure 11 is set to zero, such that the reference signal v_rΘf is in phase with a grid voltage signal Vgri_d and the apparatus 100 supplies an output current i₀ to the power grid that is in phase with the power grid voltage. Advantageously, the apparatus 100 shown in Figure 1 may be operated to provide power to an islanded load, and is capable of receiving reactive power back from the load, where the load draws power at a non-unity power factor. Because the current shunt 138 conducts current in either direction when activated by a single shunt control signal, the reactive power received back from the load flows through the current shunt and is not returned back to the source. The apparatus 100 may also be operated to provide power to a power grid load. In either mode of operation, the apparatus 100 reduces common mode voltages at the source nodes thereby providing improved electromagnetic performance and relatively safe operation of the apparatus.

While specific embodiments of the invention have been described and illustrated, such embodiments should be considered illustrative of the invention only and not as limiting the invention as construed in accordance with the accompanying claims.

Claims

What is claimed is:

1. A method for converting a direct current into alternating current in a converter circuit having first and second source nodes for receiving direct current from a direct current source and having first and second load nodes operable to be connected to a load, the converter circuit including first and second switches connected in series between the first and second source nodes and having a common first intermediate node therebetween and third and fourth switches connected in series between the first and second source nodes and having a common second intermediate node therebetween, the converter circuit including a first inductor connected between the first intermediate node and the first load node, and a second inductor connected between the second intermediate node and the second load node, the method comprising:

causing the first, second, third, and fourth switches to selectively conduct current in response to assertion of respective first, second, third, and fourth switching control signals such that current flows between the first and second source nodes and the first and second load nodes to produce alternating current at the first and second load nodes;

causing a single shunt control signal to be asserted when said first, second, third, and fourth switching control signals are not asserted;

causing current to flow through a unitary switched current path in a bidirectional current shunt when said single shunt control signal is asserted and when said first, second, third, and fourth switching control signals are not asserted, said bidirectional current shunt being connected between the first and second intermediate nodes; and causing said current shunt to block current flow between the first and second intermediate nodes when said single shunt control signal is not asserted.

2. The method of claim 1 wherein causing current to flow through said unitary switched current path comprises causing said unitary switched current path to selectively conduct current from a first shunt node to a second shunt node in response to said single shunt control signal, and wherein said current shunt includes a first unidirectional current path comprising a first diode connected to conduct current between said first intermediate node and said first shunt node and a second diode connected to conduct current between said second shunt node and said second intermediate node and a second unidirectional current path comprising a third diode connected to conduct current between said second intermediate node and said first shunt node and a fourth diode connected to conduct current between said second shunt node and said first intermediate node, such that current flows through said current shunt along one of said first unidirectional current path and said second unidirectional current path when said single shunt control signal is asserted, and wherein current flow through said current shunt is blocked when said single shunt control signal is not asserted.

3. The method of claim 1 wherein causing current to flow through said unitary switched current path comprises causing a semiconductor switch to conduct current in response to assertion of said single shunt control signal.

4. The method of claim 1 further comprising producing said first, second, third and fourth switching control signals and said single shunt control signal.

5. The method of claim 4 wherein producing said first, second, third and fourth switching control signals comprises producing first, second, third and fourth pulse width modulated switching control signals.

6. The method of claim 4 wherein producing said shunt control signal comprises causing said first, second, third, and fourth switching control signals and said shunt control signal to be in a non-asserted state for a dead time period before causing said shunt control signal to be asserted, said dead time period being of sufficient duration to cause the first, second, third, and fourth switches to be in a non-conducting state before causing said unitary switched current path to conduct current.

7. The method of claim 4 further comprising receiving a reference signal representing a desired output voltage waveform and wherein producing said first, second, third, and fourth switching control signals and said shunt control signal comprises producing first, second, third, and fourth switching control signals and said shunt control signal in response to said reference signal.

8. The method of claim 7 further comprising producing said reference signal.

9. The method of claim 8 wherein producing said reference signal comprises producing a sinusoidal reference signal having a frequency defining a desired frequency of an output voltage waveform across the first and second load nodes.

10. The method of claim 9 wherein the load comprises a reactive load that causes said output current waveform at the first and second load nodes to be out of phase with said output voltage waveform such that reactive power is received back from the load at the first and second load nodes when an instantaneous output voltage and output current have opposite polarity, and wherein:

during positive half cycles of the output voltage waveform, when the output current is negative:

when said single shunt control signal is asserted, current flows from the first load node through the first inductor to the first intermediate node, through said current shunt to the second intermediate node, and through the second inductor to the second load node;

when said single shunt control signal is not asserted, current flows from the first load node through the first inductor to the first intermediate node, through an anti- parallel diode connected across the first switch and back to the first source node, and from the second source node through an anti-parallel diode connected across the fourth switch, and through the second inductor to the second load node; and

during negative half cycles of the output voltage waveform, when the output current is positive:

when said shunt control signal is asserted, current flows from the second load node through the second inductor to the second intermediate node, through said current shunt to the first intermediate node, and through the first inductor to the first load node; and

when said shunt control signal is not asserted, current flows from the second load node through the second inductor to the second intermediate node, through an anti-parallel diode connected across the third switch and back to the first source node, and from the second source node through an anti-parallel diode connected across the second switch, and through the first inductor to the first load node.

11. The method of claim 4 wherein the load comprises a power grid load and further comprising receiving a reference signal representing a grid voltage waveform of the power grid across said first and second load nodes and wherein producing said first, second, third, and fourth switching control signals and said shunt control signal comprises producing first, second, third, and fourth switching control signals and said shunt control signal in response to said reference signal to cause an output current to be supplied to the power grid substantially in phase with the grid voltage waveform.

12. The method of claim 4 wherein the load comprises a power grid load and further comprising receiving a signal representing a grid voltage waveform of the power grid across said first and second load nodes and producing a phase shifted reference signal in response to receiving said signal representing said grid voltage waveform, and wherein producing said first, second, third, and fourth switching control signals and said shunt control signal comprises producing first, second, third, and fourth switching control signals and said shunt control signal in response to said phase shifted reference signal to cause an output current to be supplied to the power grid out of phase with the grid voltage waveform.

13. A direct current to alternating current converter apparatus comprising:

a converter circuit having first and second source nodes for receiving direct current from a direct current source and having first and second load nodes operable to be connected to a load, said converter circuit including first and second switches connected in series between said first and second source nodes and having a common first intermediate node therebetween and third and fourth switches connected in series between said first and second source nodes and having a common second intermediate node therebetween, said converter circuit including a first inductor connected between said first intermediate node and said first load node, and a second inductor connected between said second intermediate node and said second load node;

a controller operably configured to cause first, second, third, and fourth switching control signals to be asserted to cause the first, second, third, and fourth switches to selectively conduct current such that current flows between the first and second source nodes and the first and second load nodes to produce alternating current at the first and second load nodes, said controller being operably configured to cause a single shunt control signal to be asserted when said first, second, third, and fourth switching control signals are not asserted; and

a bidirectional current shunt connected between the first and second intermediate nodes, said current shunt comprising a unitary switched current path operably configured to conduct current when said single shunt control signal is asserted and when said first, second, third, and fourth switching control signals are not asserted, said current shunt being operably configured to bock current flow between the first and second intermediate nodes when said single shunt control signal is not asserted.

14. The apparatus of claim 13 wherein said unitary switched current path is connected between a first shunt node and a second shunt node and wherein said current shunt comprises:

a first unidirectional current path comprising a first diode connected to conduct current between said first intermediate node and said first shunt node and a second diode connected to conduct current between said second shunt node and said second intermediate node; and

a second unidirectional current path comprising a third diode connected to conduct current between said second intermediate node and said first shunt node and a fourth diode connected to conduct current between said second shunt node and said first intermediate node

such that current flows through said current shunt along one of said first unidirectional current path and said second unidirectional current path when said single shunt control signal is asserted, and wherein current flow through said current shunt is blocked when said single shunt control signal is not asserted.

15. The apparatus of claim 13 wherein said unitary switched current path comprises a semiconductor switch.

16. The apparatus of claim 13 wherein said controller is operably configured to produce said first, second, third and fourth switching control signals and said single shunt control signal.

17. The apparatus of claim 16 wherein said controller is operably configured to produce first, second, third and fourth pulse width modulated switching control signals.

18. The apparatus of claim 16 wherein said controller is operably configured to produce said shunt control signal by causing said first, second, third, and fourth switching control signals and said shunt control signal to be in a non-asserted state for a dead time period before causing said shunt control signal to be asserted, said dead time period being of sufficient duration to cause said first, second, third, and fourth switches to be in a non-conducting state before causing said unitary switched current path to conduct current.

19. The apparatus of claim 16 wherein said controller is operably configured to receive a reference signal representing a desired output voltage waveform and to produce said first, second, third, and fourth switching control signals and said shunt control signal in response to said reference signal.

20. The apparatus of claim 19 wherein said controller is operably configured to produce said reference signal.

21. The apparatus of claim 20 wherein said controller is operably configured to produce said reference signal by producing a sinusoidal reference signal having a frequency defining a desired frequency of an output voltage waveform across said first and second load nodes.

22. The apparatus of claim 21 wherein the load comprises a reactive load that causes said output current waveform at the first and second load nodes to be out of phase with said output voltage waveform such that reactive power is received back from the load at said first and second load nodes when an instantaneous output voltage and output current have opposite polarity, and wherein said converter circuit comprises:

a first anti-parallel diode connected across the first switch; a second anti-parallel diode connected across the second switch;

a third anti-parallel diode connected across the third switch; and

a fourth anti-parallel diode connected across the fourth switch; and wherein:

when said single shunt control signal is asserted, current flows from said first load node through said first inductor to said first intermediate node, through said current shunt to said second intermediate node, and through said second inductor to said second load node;

when said single shunt control signal is not asserted, current flows from said first load node through said first inductor to said first intermediate node, through said first anti-parallel diode and back to said first source node, and from said second source node through said fourth anti- parallel diode, and through said second inductor to said second load node; and

when said shunt control signal is asserted, current flows from said second load node through said second inductor to said second intermediate node, through said current shunt to said first intermediate node, and through said first inductor to said first load node; and when said shunt control signal is not asserted, current flows from said second load node through said second inductor to said second intermediate node, through said third anti-parallel diode and back to said first source node, and from said second source node through said second anti-parallel diode, and through said first inductor to said first load node.

23. The apparatus of claim 16 wherein the load comprises a power grid load and wherein said controller is operably configured to receive a reference signal representing a grid voltage waveform of the power grid across said first and second load nodes and to produce said first, second, third, and fourth switching control signals and said shunt control signal in response to said reference signal to cause an output current to be supplied to the power grid substantially in phase with the grid voltage waveform.

24. The apparatus of claim 16 wherein the load comprises a power grid load and wherein said controller is operably configured to:

receive a signal representing a grid voltage waveform of the power grid across said first and second load nodes;

produce a phase shifted reference signal in response to receiving said signal representing said grid voltage waveform; and

produce said first, second, third, and fourth switching control signals and said shunt control signal in response to said phase shifted reference signal to cause an output current to be supplied to the power grid out of phase with the grid voltage waveform.

25. An apparatus for converting a direct current into alternating current in a converter circuit having first and second source nodes for receiving direct current from a direct current source and having first and second load nodes operable to be connected to a load, the converter circuit including first and second switches connected in series between the first and second source nodes and having a common first intermediate node therebetween and third and fourth switches connected in series between the first and second source nodes and having a common second intermediate node therebetween, the converter circuit including a first inductor connected between the first intermediate node and the first load node, and a second inductor connected between the second intermediate node and the second load node, the apparatus comprising:

means for causing the first, second, third, and fourth switches to selectively conduct current in response to assertion of respective first, second, third, and fourth switching control signals such that current flows between the first and second source nodes and the first and second load nodes to produce alternating current at the first and second load nodes;

means for causing a single shunt control signal to be asserted when said first, second, third, and fourth switching control signals are not asserted;

means for causing current to flow through a unitary switched current path in a bidirectional current shunt when said single shunt control signal is asserted and when said first, second, third, and fourth switching control signals are not asserted, said bidirectional current shunt being connected between the first and second intermediate nodes; and means for causing said current shunt to block current flow between the first and second intermediate nodes when said single shunt control signal is not asserted.

26. The apparatus of claim 25 wherein said means for causing current to flow through said unitary switched current path comprises means for causing said unitary switched current path to selectively conduct current from a first shunt node to a second shunt node in response to said single shunt control signal, and wherein said current shunt includes a first unidirectional current path comprising a first diode connected to conduct current between said first intermediate node and said first shunt node and a second diode connected to conduct current between said second shunt node and said second intermediate node and a second unidirectional current path comprising a third diode connected to conduct current between said second intermediate node and said first shunt node and a fourth diode connected to conduct current between said second shunt node and said first intermediate node, such that current flows through said current shunt along one of said first unidirectional current path and said second unidirectional current path when said single shunt control signal is asserted, and wherein current flow through said current shunt is blocked when said single shunt control signal is not asserted.

27. The apparatus of claim 25 wherein said means for causing current to flow through said unitary switched current path comprises means for causing a semiconductor switch to conduct current in response to assertion of said single shunt control signal.

28. The apparatus of claim 25 further comprising means for producing said first, second, third and fourth switching control signals and said single shunt control signal.

29. The apparatus of claim 28 wherein said means for producing said first, second, third and fourth switching control signals comprises means for producing first, second, third and fourth pulse width modulated switching control signals.

30. The apparatus of claim 28 wherein said means for producing said shunt control signal comprises means for causing said first, second, third, and fourth switching control signals and said shunt control signal to be in a non-asserted state for a dead time period before causing said shunt control signal to be asserted, said dead time period being of sufficient duration to cause the first, second, third, and fourth switches to be in a non-conducting state before causing said unitary switched current path to conduct current.

31. The apparatus of claim 28 further comprising means for receiving a reference signal representing a desired output voltage waveform and wherein said means for producing said first, second, third, and fourth switching control signals and said shunt control signal comprises means for producing first, second, third, and fourth switching control signals and said shunt control signal in response to said reference signal.

32. The apparatus of claim 31 further comprising means for producing said reference signal.

33. The apparatus of claim 32 wherein said means for producing said reference signal comprises means for producing a sinusoidal reference signal having a frequency defining a desired frequency of an output voltage waveform across the first and second load nodes.

34. The apparatus of claim 33 wherein the load comprises a reactive load that causes said output current waveform at the first and second load nodes to be out of phase with said output voltage waveform such that reactive power is received back from the load at the first and second load nodes when an instantaneous output voltage and output current have opposite polarity, and wherein:

when said single shunt control signal is not asserted, current flows from the first load node through the first inductor to the first intermediate node, through a diode connected in anti-parallel across the first switch and back to the first source node, and from the second source node through a diode connected in anti-parallel across the fourth switch, and through the second inductor to the second load node; and

when said shunt control signal is not asserted, current flows from the second load node through the second inductor to the second intermediate node, through a diode connected in anti-parallel across the third switch and back to the first source node, and from the second source node through a diode connected in anti-parallel across the second switch, and through the first inductor to the first load node.

35. The apparatus of claim 28 wherein the load comprises a power grid load and further comprising means for receiving a reference signal representing a grid voltage waveform of the power grid across said first and second load nodes and wherein said means for producing said first, second, third, and fourth switching control signals and said shunt control signal comprises means for producing first, second, third, and fourth switching control signals and said shunt control signal in response to said reference signal to cause an output current to be supplied to the power grid substantially in phase with the grid voltage waveform.

36. The apparatus of claim 28 wherein the load comprises a power grid load and further comprising means for receiving a signal representing a grid voltage waveform of the power grid across said first and second load nodes and means for producing a phase shifted reference signal in response to receiving said signal representing said grid voltage waveform, and wherein said means for producing said first, second, third, and fourth switching control signals and said shunt control signal comprises means for producing first, second, third, and fourth switching control signals and said shunt control signal in response to said phase shifted reference signal to cause an output current to be supplied to the power grid out of phase with the grid voltage waveform.