WO2009135079A2

WO2009135079A2 - Ferroelectric infrared sensor and integrator

Info

Publication number: WO2009135079A2
Application number: PCT/US2009/042432
Authority: WO
Inventors: Jolanta Celinska; Carlos A. Paz De Araujo; Ricardo Unglaub
Original assignee: Symetrix Corporation
Priority date: 2008-04-30
Filing date: 2009-04-30
Publication date: 2009-11-05
Also published as: WO2009135079A3

Abstract

An infrared sensor includes a first ferroelectric capacitor, oriented such that the first ferroelectric capacitor is not exposed to radiation to be measured; a second ferroelectric capacitor, the second ferroelectric capacitor comprising a silicon substrate, an insulating layer, and a ferroelectric element; a subtractor that receives electric signals from both the first and second ferroelectric capacitor and finds a difference; and an integrator that receives electric signals from the subtractor and integrates the electric signals from the subtractor.

Description

FERROELECTRIC INFRARED SENSOR AND INTEGRATOR

FIELD OF THE INVENTION

The invention in general relates to pyroelectric sensors, and in particular such a sensor that utilizes a ferroelectric sensing element.

SUMMARY OF THE INVENTION

Numerous other features, objects and advantages will become apparent from the following description when read in conjunction with the accompanying drawings.

One embodiment of an infrared sensor includes a first ferroelectric capacitor, oriented such that the first ferroelectric capacitor is not exposed to radiation to be measured; a second ferroelectric capacitor, the second ferroelectric capacitor comprising a silicon substrate, an insulating layer, and a ferroelectric element; a subtractor that receives electric signals from both the first and second ferroelectric capacitor and finds a difference; and an integrator that receives electric signals from the subtractor and integrates the electric signals from the subtractor. A feature of the infrared sensor includes that multiple cycles of electrical signals are applied to the infrared sensor. Another feature of the infrared sensor includes that the insulating layer comprises titanium, platinum, and Strontium Tantalate. Yet another feature of the infrared sensor includes that the insulating layer comprises a first layer of titanium, a first layer of platinum, a first layer of Strontium Tantalate, a second layer of titanium, a second layer of platinum, a second layer of Strontium Tantalate.

A feature of the infrared sensor includes that the first layer of titanium is between 10-30 nm in thickness. Another feature includes that the first layer of titanium is approximately 20 nm in thickness. Yet another feature of the infrared sensor includes that the first layer of platinum is between 30-70 nm in thickness. Yet another feature of the infrared sensor includes that the first layer of platinum is approximately 50 nm in thickness. Yet another feature of the infrared sensor includes that the first layer of Strontium Tantalate is between 30-75 nm in thickness. Yet another feature of the infrared sensor includes that the first layer of Strontium Tantalate is approximately 55 nm in thickness. Yet another feature of the infrared sensor includes that the total thickness of the insulating layer is approximately 250 nm. Yet another feature of the infrared sensor includes that the ratio of the first and second layer of platinum to the first and second layer of titanium is adjusted to yield a higher density of hillocks. Yet another feature of the infrared sensor includes that the ratio of the first and second layer of platinum to the first and second layer of titanium is between 1 :5 and 3:5. Yet another feature of the infrared sensor includes that the ratio of the first and second layer of platinum to the first and second layer of titanium is between 1 :10 and 3:10. Yet another feature of the infrared sensor includes that the ratio of the first and second layer of platinum to the first and second layer of titanium is approximately 2:5. Yet another feature of the infrared sensor includes that the ratio of the first and second layer of platinum to the first and second layer of titanium is adjusted to achieve a maximum density of hillocks while retaining electrical connectivity. Yet another feature includes that the annealing at 650C of the Titanium/Platinum layer results in formation of a Titanium Oxide - Platinum interface. Yet another feature is that hillocks are created due to Titanium diffusion prior to the Strontium Tantalate layer deposition. One embodiment of an apparatus for testing IR sensors includes at least one low leakage integrator; a digital N-pulse selectable counter; a count comparator- reset command; an instrumentation amplifier; and a gain-selectable amplifier.

One embodiment of a method for testing an infrared sensor includes providing an AC signal source; exciting a reference ferroelectric capacitor sensitive to infrared radiation; exciting an exposed ferroelectric capacitor sensitive to infrared radiation; subtracting a first signal from the reference ferroelectric capacitor from a second signal from the exposed ferroelectric capacitor to produce a third signal; and integrating the third signal. A feature of the method further includes injecting the AC signal into a pulse-shaped circuit; the pulse-shaped circuit counts pulses of the AC signal and compares the count of the pulses to a pre-set count. Another feature includes that the integrating of is for a period of time; the period of time is a pulse period times the pre-set count, and the pulse period is a frequency of the pulses of the AC signal. Yet another feature includes that the pre-set count may be selected by a user. Another feature includes amplifying the third signal with a gain selectable stage. Another feature includes that a user may select an amplification level, the amplification level specifying the level of amplifying provided by the gain selectable stage. One embodiment of an apparatus for testing IR sensors includes at least one low leakage integrator; a digital N-pulse selectable counter; a count comparator- reset command; an instrumentation amplifier; and a gain-selectable amplifier. In one alternative, the apparatus further includes absolute value detectors. In one alternative, the apparatus further includes low pass filters. In one alternative, the apparatus further includes a resettable integrator. In one alternative, the resettable integrator of includes an amplification stage.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a circuit diagram for one embodiment of an infrared sensor testing device;

FIG. 2 shows a circuit diagram of another embodiment of an infrared sensor testing device;

FIG. 3 shows a functional block diagram of one embodiment of an infrared sensor testing device;

FIGS. 4a-4d shows a graph of the signal processing process resulting from one embodiment of an infrared testing device;

FIG. 5 shows a circuit diagram for one embodiment of an active pyroelectric detection;

FIG. 6 shows a functional block diagram for one embodiment of an active pyroelectric detection device;

FIG. 7 is a graphical depiction of one embodiment of ferroelectric caps;

FIG. 8 is a top view of one embodiment of ferroelectric caps;

FIGS. 9a-9c illustrate the electrical properties of one embodiment of a SBT Ferroelectric IR single pixel detector;

FIG. 10 is an alternative configuration for an active IR detection circuit; FIG. 1 1 shows a functional block diagram for one embodiment of an infrared sensor testing device;

FIG. 12 shows a more detailed circuit diagram of the digital section of the infrared sensor testing device of FIG. 11 ;

FIG. 13 shows a more detailed circuit diagram of a resettable integrators, instrumentation amplification, and gain stage of the infrared sensor testing device of FIG. 1 1 ;

FIG. 14 shows a more detailed circuit diagram for an analog to digital pulse shaper of the infrared sensor testing device of FIG. 1 1 ;

FIG. 15 shows a more detailed circuit diagram for a reset/clear-count pulse shaper of the infrared sensor testing device of FIG. 1 1 ;

FIG. 16 shows a more detailed circuit diagram for diode network connections of the infrared sensor testing device of FIG. 1 1 ;

FIG. 17 shows an infrared (IR) sensor testing setup into which the infrared sensor testing device of FIGs. 1 , 2, and 1 1 may be incorporated;

FIG. 18 shows a front panel silk-screen of the infrared sensor testing device of FIG. 1 1 ;

FIG. 19 is a graph of polarizability vs. voltage of one embodiment of a ferroelectric sensor; and

FIG. 20 is a circuit diagram for one embodiment an array of ferroelectric IR sensors.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Since ferroelectric capacitors can heat up when exposed to IR radiation, the heat may be transferred to the underlying layers. This transfer of heat may cause the underlying layers to function improperly. An insulator or low thermal conductivity nanolaminate may be introduced to lessen the impact of the IR radiation on the underlying layers, including but not limited to the silicon. In one embodiment as shown in Table 1 , the insulating layer is a nanolaminate composed of a layer of titanium, followed by a layer of platinum, and a layer of Strontium Tantalate (SrTa2O6). This insulating layer may be twice deposited. The thicknesses of the layers are shown in Table 1. The thicknesses are as follows: a 20nm layer of Ti; a 50nm layer of Pt; and a 55nm layer of SrTa2O6. In one aspect of the insulator, two layers of this Ti/Pt/ SrTa2O6 are deposited. As show in Table 1 the insulating layers of Ti/Pt/ SrTa2O6 yielded two different thermal conductivities: 0.75 K and 1.05 K. As shown, the S003 sample hand a higher density of hillocks.

TABLE 1

Hillocks are characterized as a rough surface, comprising discrete bumps in the surface, which penetrate a layer (typically the dielectric layer) at the interface and anchors a layer (typically an electrode) to improve adhesion of the electrode materials to another layer (typically the ferroelectric layer). The term "hillocks" is sometimes used to indicate detrimental formation of crystals at interfaces. The term hillocks refers to the bumps which comprise part of the rough surface of the mixed alloy layer, and which penetrate the dielectric and act as anchors for the electrode material in the ferroelectric. The rough surface and hillocks are beneficial in improving adhesion between the ferroelectric layer and the electrode structure. However, if the hillocks become too prominent, the electrical connection may be compromised. Hillocks often result in current leakage or device shorts.

Traditionally, ferroelectric structures are designed to create a low level of hillocks, since a high density can cause a break down in electrical connectivity and an increase in size/thickness. In one aspect of the insulating layer it has been found that a high density of hillocks yields lower thermal conductivity and therefore a better insulating layer. The formation of hillocks is related to the ratio of the thickness of Ti deposited to the Pt.

The difference in test results between the S003 sample and the S004 sample is thought to be the result of irregularities in the formation process of the insulating layer. Slight adjustments of the ratio of Ti to Pt may yield an increased level of hillocks. The Ti helps regulate the formation of hillock due to its thermal expansion coefficient (being between that of Pt and the underlying silicon layer). Therefore, a slight adjustment down of the ratio of Ti to Pt is thought to yield a greater concentration of hillocks, resulting in a device short. It is thought that the lower thermal conductivity of the S003 sample (0.75 K) as compared to the S004 sample (1.05K) is a result of the slight adjustment of this ratio.

Many different options are available for thickness of the insulating layer. In one alternative the first layer of titanium is between 10-30 nm in thickness. In another, the first layer of titanium is approximately 20 nm in thickness. In one alternative the first layer of platinum is between 30-70 nm in thickness. In another the first layer of platinum is approximately 50 nm in thickness. In one alternative the first layer of Strontium Tantalate is between 30-75 nm in thickness. In another the first layer of Strontium Tantalate is approximately 55 nm in thickness. In one alternative the total thickness of the insulating layer is approximately 250 nm. In another embodiment the ratio of the layers is important to forming hillocks that will provide greater thermal insulation. In one alternative the ratio of the first and second layer of platinum to the first and second layer of titanium is adjusted to yield a higher density of hillocks. In another alternative the ratio of the first and second layer of platinum to the first and second layer of titanium is between 1 :5 and 3:5. In another the ratio of the first and second layer of platinum to the first and second layer of titanium is between 1 :10 and 3:10. In yet another the ratio of the first and second layer of platinum to the first and second layer of titanium is approximately 2:5.

In one embodiment the ratio of the first and second layer of platinum to the first and second layer of titanium is adjusted to achieve a maximum density of hillocks while retaining electrical connectivity. The annealing at 650C of the Ti/Pt layer results in formation of the TiOx-Pt interface and creation of hillocks due to Ti diffusion prior to the STO smoothing layer deposition.

It should be understood that although specific embodiments of the systems, devices, methods, and techniques are described herein, the specifics are merely exemplary, and in light of the present disclosure, those of ordinary skill in the art will realize modifications of the systems, devices, methods, and techniques.

A number of embodiments of Infrared (IR) Detector systems are shown in the various FIGs. At least three primary configurations in FIGs. 1 , 2, and 11 are shown. The embodiment of FIG. 1 1 and the additional FIGs. associated therewith goes into greater detail

The detection of infrared radiation may be accomplished according to a variety of techniques. One such technique involves the use of ferro-electric sensors. The composition of ferro-electric sensors may affect their functionality. The thermal conductivity of the sensors may be important, since if too much heat is transferred to the underlying circuitry then its electrical properties may be compromised. Furthermore, due to the small size and unique nature of ferro-electric sensors, special testing mechanisms are needed.

One embodiment of a pulse-count resettable dual integrator apparatus with differential gain output includes a system for testing Infrared Sensors. In one embodiment this system is specifically designed to test ferro-electric infrared sensors. The system includes various design features to address the specifics of ferro-electric infrared sensors, including the small size of the sensors and the need to have an active sensor that is exposed to radiation and a reference sensor that is not. The IR testing systems includes two precision, low leakage integrators, a digital N-pulse selectable counter, a count comparator-reset command, and instrumentation amplifier, a gain-selectable amplifier, and associated conditioning circuits. Generally, this apparatus is specifically designed to test single IR sensors, where the IR sensors include and active cell, which receives radiation, and a reference cell, which receives essentially no radiation.

In basic operation the IR testing system receives a signal from an active and a reference sensor, takes the difference of the signals, and integrates the difference. From the outputted calculation, the IR radiation received by the active sensor may be calculated.

FIG. 1 shows a circuit diagram for one embodiment of an infrared sensor testing device. The infrared sensor testing device shown in FIG. 1 outputs a signal at Input Vod (Difference Output) 11 . The device includes a instrumentation amplifier, which includes Operational Amplifier 10, Capacitor 12 (0.1 uF), Capacitor 13 (0.1 uF), Diode 14 (1 N914), Diode 15 (D6 1 N914), Resistor 16, and Resistor 17 (100Ω). Exemplary ratings and identifiers are given in parenthesis. The device includes a low pass filter, which includes Capacitor 18 (1 OuF), Capacitor 19 (330Ω), Resistor 20 (330Ω), Resistor 21 (330Ω). Switch 22 allows for the difference determination of the IR sensors A and B to be in a B-A arrangement or a A-B arrangement. The signal source comes from Input 23, Vo(A) and Input 24, Vo(B), for infrared sensors A and B respectively. Voltage is provided by source 25, 25, in this case 15V. The device includes precision rectifiers, or absolute value detectors, one for each signal. The signal A rectifier includes Resistor 28, Capacitor 29, Capacitor 29(0.1 uF), Operational Amplifier 30 (U2 LT1793), Resistor 31 (22kΩ), Capacitor 32, Resistor 33 (10kΩ), Resistor 34 (2OkQ), and Resistor 35 (1 OkQ). The signal B rectifier includes Capacitor 36, Resistor 37, Capacitor 38 (0.1 uF), Operational Amplifier 39

(LT1793), Resistor 40 (22kΩ), Capacitor 41 , Resistor 42 (1 OkQ), Resistor 43 (2OkQ), and Resistor 44 (10kΩ). The device includes two integrators, one for each of the A and B signals from the A and B IR detectors. The A integrator includes Capacitor 45 (0.1 uF), Resistor 46, Resistor 47, Resistor 48, Resistor 49, Diode 50 (1 N914), Diode 51 (1 N914), Operational Amplifier 52 (LT1793), Capacitor 53 (0.1 uF), Resistor 54 (22kΩ), Resistor 55 (10kΩ), Resistor 56 (20kΩ), Resistor 57(1 OkQ), and Capacitor 58.The B integrator includes Capacitor 59 (0.1 uF), Resistor 60, Resistor 61 , Resistor 62, Resistor 63, Diode 64 (1 N914), Diode 65(1 N914), Capacitor 66 (0.1 uF), Operational Amplifier 67 (LT1793), Resistor 68 (22kΩ), Capacitor 69, Resistor 70 (1 OkQ), Resistor 71 (2OkQ), and Resistor 72 (1 OkQ). Also shown is the back of switch connections 78 to the output from sensor A 73, output from sensor B 74, output to integrator A 76, output to integrator A 77.

FIG. 2 shows a circuit diagram of another embodiment of an infrared sensor testing device. This embodiment includes connectors 21 1 and 212 from the IR detectors and integrators 213, 214, Absolute-Value Converters 215, 216, which have similar circuitry to the embodiment shown in FIG. 1. The device includes connector BNC 217 (Vo (A)) and connector BNC 218 (Vo (B)). Switch 219 allows for the difference determination of the IR sensors A and B to be in a B-A arrangement or a A-B arrangement. The instrument amplification stage of the device includes Resistor 220 (330Ω), Resistor 221 (100Ω), Resistor 222 (2OkQ), Resistor 223(330Ω), Operational Amplifier224, Diode 225 (1 N914), Capacitor 226 (0.1 uF), Capacitor 227(0.1 uF), Diode 228 (1 N914), Resistor 229(22kΩ), Resistor 230 (2OkQ), Resistor 231 (22kΩ), and Resistor 232 (47kΩ). This embodiment differs from the previous embodiment, at least in that the low pass filters in the embodiment shown in FIG. 1 is removed and a resettable integrator is added at the output of the amplification stage. Additionally an amplification stage was added after the reset integrator. The reset integrator includes Resistor 233 (47kΩ), Operational Amplifier 234, reset pulse 235, Diode 236 (1 N914), Resistor 237(1 OOkΩ), Capacitor 238( 0.1 uF), N-Channel MOSFET 239 (3N171 ), Capacitor 240 (0.1 uF), Resistor 241 (440kΩ), Capacitor 242 (0.1 uF), Capacitor 243 (0.1 uF). The amplification stage after the integrator includes, Resistor 244 (2kΩ), Resistor 245 (200Ω), Operational Amplifier 246, Resistor 247 (1.8kΩ), Capacitor 248 (0.1 uF), Capacitor 249(0.1 uF), Resistor 250 (19.8kΩ), and Resistor 251 (10kΩ). The integrated difference is output at connector 252. Back of switch connection 253 is similar as to the embodiment shown in FIG. 1. Since a pure integrator has a pole at zero frequency, it amplifies the low- frequency variations with very high gain, making the 1/f noise predominant. This is observed in the amplification of the induced ambient electromagnetic fields of 60Hz when the sensors were probed at different probing stands, or in different enclosures. One way to reduce this problem is to set both sensors in the same enclosure, and operate the sensors in bridge mode so both are exposed to the IR radiation. While the integrator effectively eliminates the high frequency noise with a roll-off of - 20dB/decade, the 1/f noise amplification on the lower frequencies still persists. This mandates to limit the gain at a frequency just below the 1 OkHz excitation frequency. That is, we are back to an equivalent circuit as the one shown in FIG. 1 where the low pass-filters have the desired transfer function. Now the transfer function must be implemented in the integrator by lowering the Rp (R32) resistance in parallel with the integrator capacitor in FIG. 2. One advantage of the circuit in FIG. 2 is the N-pulses reset capability.

A further improvement to the circuit in FIG. 2 is to utilize ultra-low noise operational amplifiers in the absolute value converters. To this end, LT1028 Op- Amps from Linear Technology with a PSD of ~1 nV/sqrt(Hz) may be used.

FIG. 3 shows a functional block diagram of one embodiment of a infrared sensor testing device. This block diagram is similar to the embodiment shown in FIG. 2. This 1x1 Pixel Read-Out (RO) Circuit Block Diagram provides a conceptual model for the testing device. The device has been designed for testing the 1 x1 pixel SBT IR sensors. The signal source 351 provides a signal to the reference (dark) and IR Signal (exposed) sensors 352. An output of these respective signals may be taken at output 353, 354. An output of the signal prior to exposure may also be taken at output 355. Pulses are generated and the number of pulses is counted in block 356. Block 356 includes pulse generator 357, counter 361 , comparator 360 and N-Set 359. Power supplies of +5V and +/-15V are provided in source 362.

Block 363 includes a signal conditioner 364 and an analog circuit 367. The signals from the sensors 352 pass through absolute value converters 368, 369 and then amplitude adjustors 370, 371. Switch 373 may be set to determine the difference of signal A and B or B and A (A-B or B-A). The absolute value signals are output at output 372, 374 respectively (Vo(A) and Vo(B)). The signal conditioner 364 includes an analog to digital pulse shaper 365 and a reset pulse circuit 366. After the count is met, a reset signal may be sent to MOSFET switch 376 that resets resettable integrator 376. The device further includes capacitor 377 and amplifier 379. The integrated signal is output at output 380. The number N of integration cycles (N-set) is manually selected (at N-Set 359) such that the resetting of the integrator occurs every N cycles of the interrogation signal Vs(t), set to 10 kHz and peak voltage of 3 volts. For performance measures and characterization of the sensor, both frequency and amplitude of Vs(t) are varied. The integrator resets every Tr = N/10000 seconds. The active and dark sensor responses to the excitation signal are absolute-value converted, and their dark signals are amplitude-equalized before the IR radiation exposure measurements via amplitude adjustment trim-pots to yield null output when both sensors are at dark (no IR radiation). This is achieved by comparing (with an oscilloscope) the absolute-value converted signals output at the terminals Vo(A) and Vo(B) respectively.

The signal processing of the two sensors (now one in dark and the other exposed to radiation) is depicted in FIGS. 4a-d. The responses of the sensors FIG. 4a are absolute-value converted FIG. 4b and subsequently differenced by an instrumentation amplifier (IA) with a fixed gain of 10 FIG. 4c. The amplified differenced and signal is then integrated for the duration of N cycles FIG. 4d before a reset pulse is sent by the digital circuit to null the integration. A post-amplification with selectable gain between 0.1 and 10 (which, together with the IA gain of 10 gives a total gain of 1 to 100) completes the signal processing. A digital oscilloscope is utilized to perform a subsequent averaging (signal ° in FIG. 4d) of the integrated output signal.

In FIG. 5 an embodiment of a ferroelectric detector is depicted. The sensor consists of two ferroelectric capacitor elements 510 and an off-chip subtractor 520 and integrator 530. One reason these element may be positioned off chip is to minimize the effects of the heat absorbed by the ferroelectric capacitor. One of the ferroelectric capacitors is exposed to radiation and the other ferroelectric capacitor is not. The capacitor exposed to radiation is the active capacitor and the unexposed capacitor is the reference capacitor as explained above. The difference of the two ferroelectric capacitors is differenced and integrated by an integrator. In one aspect, the Active Pyroelectric Detector may multiply the pyroelectric coefficient by twice the number of switching cycles.

Turning now to FIG. 5, an electrical circuit diagram of a preferred pyroelectric sensor is shown. Parts of sensor that are identical to generalized sensor 300 are labeled with the same numeral. Sensor preferably includes a source of a voltage pulse, V.sub.s, a first ferroelectric capacitor and a second ferroelectric capacitor 510, a subtractor 520, an integrator 530, and an output. Subtracter 520 comprises diodes and ground connections. Integrator 530 includes a capacitor, operational amplifier, and ground connection. The voltage pulse source is connected between the system ground and first electrodes and of capacitors 510, respectively. Second electrodes of capacitors 510 are connected to the anode and the cathode of diodes respectively in difference circuit 520. The anode and cathode of the diodes are connected to ground. Then the diodes are connected to the capacitor in the integrator circuit.

Sensor operates as follows. A voltage V.sub.s is applied to capacitors 510 and by the pulse source. This pulse, for example, may oscillate from -5V to 5V. On the positive pulse, that is, when V.sub.s goes from OV to 5V and back to OV, ferroelectric switching current from capacitor2 510 into the capacitor of the integrator circuit 530. On the negative pulse, that is, when V.sub.s goes from OV to -5V and back to OV, charge is drawn from the capacitor of the integrator circuit 530 by the ferroelectric switching current flowing back to capacitor 510. Thus, the charge associated with one of the ferroelectric capacitors 510 is subtracted from the charge associated with the other one of the ferroelectric capacitors 510 by subtractor 520.

With a temperature difference .DELTA. T between capacitor 510, the charge difference integrated on the capacitor of the integrator circuit 530 is: .DELTA.Q=2A.sub.fp.sub.y.DELTA.T (5) where A.sub.f is the area of the ferroelectric capacitors 510. After applying n cycles of excitation, the total charge on the capacitor of the integrator circuit 530 is: Q.sub.0=n.DELTA.Q (6) and the voltage shown across the capacitor of the integrator circuit 530 is:

V.sub.O=Q.sub.O/C.sub.O=n2A.sub.fp.sub.y.DELTA.T/C.sub.O (7) Note that in the above equation, C.sub.O is not bounded by the ferroelectric capacitance as in the prior art. In fact, C.sub.O can be any value, but no less than the ferroelectric capacitance of capacitors 510. From equation 7, the output voltage V.sub.O is a linear function of applied excitation cycles, n.

It should be understood that the sensors are only intended to illustrate the inventive sensor sufficiently so that it can be understood by those skilled in the art. Those skilled in the art will understand that, though the sensors have been described in terms of a voltage pulse V.sub.s and a voltage output V.sub.O, they could also have been described in terms of currents, charges, or a mix of voltages, currents, and charges, since when voltage is applied, current and charge will also flow.

Assume a sensor with sensitivity, in terms of noise equivalent temperature difference, of 50 mK is required. This sensitivity means that a temperature change of 50 mK can be sensed in the radiant infrared energy, and is a reasonable goal for an imaging device. Assuming that 1/100 of the temperature difference is absorbed by the exposed ferroelectric capacitor, the actual sensitivity on chip is 50 mK/100=0.5 mK. Assuming the total temperature change of the radiant energy is 200K and the exposed ferroelectric capacitor can only see 2 T temperature change, the total number of levels of the A/D converter should be 2K/0.5 mK=4000. Assuming the A/D converter swings from OV to 2V, the resolution of A/D converter should be 2V/4000=500 .mu.V. Then to obtain a sensitivity corresponding to the required 0.5 mK temperature difference, the minimum voltage built up on capacitor 408 should be 500 .mu.V.

For strontium bismuth tantalite (SBT), the pyroelectric coefficient is py=0.03 .mu.C/cm.sup.2K (microcoulombs per centimeter squared Kelvin). The charge difference corresponding to 0.5 mK is .DELTA.Q=2^*Af py^*.DELTA.T. Assume Af is 100 .mu.m.sup.2, then .DELTA.Q=3.times.10.sup.-17C, or about 200 electrons. If the integration capacitor 408 is 15 pF, then V.sub.0=.DELTA.Q/Co=2 .mu.V after one full cycle of excitation. Therefore, we need n=250 for V.sub.O to reach 500 .mu.V. In other words, corresponding to 2K temperature difference, n must be 250 for V.sub.O reaching 2 volts. In FIG. 6 an embodiment of a ferroelectric detector is depicted. The sensor consists of two ferroelectric capacitor elements 610 and an off-chip subtractor 620 and integrator 630. One reason these element may be positioned off chip is to minimize the effects of the heat absorbed by the ferroelectric capacitor. The sensors 610 receive voltage pulses from a voltage source. One of the ferroelectric capacitors is exposed to radiation and the other ferroelectric capacitor is not. The capacitor exposed to radiation is the active capacitor and the unexposed capacitor is the reference capacitor as explained above. The difference of the two ferroelectric capacitors is differenced and integrated by an integrator. In one aspect, the Active Pyroelecthc Detector may multiply the pyroelecthc coefficient by twice the number of switching cycles. Preferably, the sensor output signal, V.sub.O, is a voltage representative of the difference in polarizability, and thus temperature, between first ferroelectric capacitor and second ferroelectric capacitor. In the preferred embodiment of sensor, one capacitor is exposed to the environment to be sensed, and the other capacitor is shielded from the environment, which in the application of an imager, means it is in the dark.

FIG. 7 depicts the structure of a pyroelecthc sensor and the composition process. First a silicon substrate 778 is deposited. An insulating layer may be deposited next in order to reduce the exposure of the silicon substrate to heat which can affect the properties of the substrate. A silicon dioxide (SiO2) layer may also be deposited. A bottom electrode 777 may be deposited next. The bottom electrode may be composed of Platinum (Pt) and may range in thickness from 50 nm to 500 nm. In one embodiment the bottom electrode is approximately 200 nm in thickness.

The strontium bismuth tantlate (SBT) layer 776, which is a bismuth layer- structure ferroelectric material, is a ferroelectric capacitor. In one embodiment this layer has an approximate thickness of 150nm, however its thickness may range from 100 nm to 500 nm. The SBT undergoes rapid thermal bonding (RTB) at 750 degrees Celsius. A top electrode 775 is then deposited. The top electrode is of similar thickness and material as the bottom electrode. In one embodiment the top electrode has a thickness of 200 nm and is composed of platinum. After deposition, the device may be etched to size the various sections. A first photo resist is applied and the top electrode and ferro-electric capacitor are etched according to techniques that will be apparent to those skilled in the art in light of this disclosure. A second photo resist is applied and the bottom electrode is etched. The device then undergoes rapid thermal annealing (RTA) at a temperature of 750 degrees Celsius. The annealing at 650C of the Ti/Pt layer results in formation of the TiOx-Pt interface and creation of hillocks due to Ti diffusion prior to the STO smoothing layer deposition.

In one aspect of the ferroelectric capacitors, the capacitors may be fabricated on 4-inch silicon wafer using 2 micron standard process. Since it is necessary to keep one ferroelectric capacitor in the dark (away from the infrared radiation to be measured, the wafer is cut into halves. The ferroelectric capacitors may be deposited as dots platinum and strontium bismuth tantalite (SBT) on top of a platinum, insulator, silicon dioxide, and silicon substrate. In this configuration, the layers of platinum function as an electrodes and the layer of SBT functions as the ferroelectric element. In this configuration, as described in relation to the fabrication process, the top and bottom electrode may be etched so that each is accessible to be probed using needle probes as described above in relation to FIGS. 17.

FIGs. 8a-b shows a top view of deposited and etched ferro caps. In Fig. 8b the insulator 810, the top electrode and strontium bismuth tantalite 820, and the bottom electrode 830 may be seen. The ferroelectric devices can be fabricated in various sizes, ranging from having a diameter of 50 micrometers to 250 micrometers.

FIGS. 9a-9c illustrate the electrical properties of a SBT Ferroelectric IR single pixel detector. In one aspect of the SBT Ferroelectric IR single pixel detector, the ferroelectric capacitor is formed of strontium bismuth tantalate (SrBi2Ta2O9) that undergoes a RTB (rapid thermal bake) at 750 degrees Celsius. Two layers are deposited for a total thickness of 150 nm. The cap formed is 100 micrometers in diameter. FIG. 9a shows a graph of polarization [uC/cm^Λ2] for P-E hysteresis. FIG. 9b shows a graph of leakage measurement for leakage current in A/cm^Λ2 versus Bias in volts. Fig. 9c shows a graph of Q-V hysteresis for polarization [uC/cm^Λ2] versus bias in volts. FIG. 10 shows an alternative configuration for a ferroelectric detector like the one depicted in FIG. 6. The sensor consists of two ferroelectric capacitor elements 1010, 1020, one exposed 1010 and one in the dark 1020. Instead of subtracting first, the signals are first integrated at integrators 1030, 1040. They are subtracted at subtractor 1050. The signals are then integrated at variable gain amplifier 1060. FIG. 3 shows a functional block diagram of one embodiment of an infrared sensor testing device;

FIG. 11 shows a functional block diagram for one embodiment of the IR testing system. Previous embodiments shown in FIGs. 1 and 2 are similar in many ways to this embodiment. In the embodiment shown in FIG. 11 , the ferroelectric thermal sensor capacitors had to be connected in Sawyer tower configuration, otherwise a fairly triangular-wave-shape would be obtained, with little difference in wave-shape as compared with the input triangular wave. By connecting the capacitors in Sawyer tower configuration, the voltage output would saturate at 0.35V to 0.4V-peak when the input triangular wave excursion was 5V to 7V-peak. Further input peak voltage would rupture the capacitors. The Sawyer tower output voltage was below the barrier voltage of the rectifier diodes, even Schottky diodes. As noted previously, in the case of the embodiment of FIG. 1 precision rectifiers were added to modify the configuration to obtain a full-wave rectified signal. A low-pass filter to obtain peak detection was inserted at the output of each absolute value detector and a follow-on difference amplifier (instrumentation amplifier) was connected to amplify any difference between the two sensor outputs. The absolute-value converters were able to be calibrated to output the same signal or peak voltage when both circuits were connected to the same source. As previously noted in respect to the embodiment shown in FIG. 2, given that the integration feature of the original design was desired to be kept, the low-pass filters after the absolute value detectors were removed and a resettable integrator was added at the output of the instrumentation amplifier. An amplification stage was also added to the integrator circuit. This is the present configuration.

As can be seen in FIG. 11 , the IR testing system is composed of a number of elements, including a Logic Circuit and a Pulse Generator 1120, a Signal Conditioner 1165, an Analog PCB 1170, which includes resettable integrators 1180, a Diode Network 1 160, a number of sensors 1 140, and a control/input panel 1 110. A number of the features of this diagram will be described in greater detail, in respect to FIGS. 12-18. The control/input panel 1 110 in FIG. 1 depicts a number of the settable testing features of the IR testing system. The gain of the system can be set between 1 and 100 though use of the gain selector on the control/input panel. The amplification of the signal according to the gain selected is generally implemented after differencing.

The control/input panel 1 1 10 enables the user to set number of pulses (n1 ) output from the pulse generator and logic circuit. As can be seen in FIG. 1 1 , the logic circuit 1120 counts the number of pulses (n2) and compares that to the pulse number setting (n1 ) for a cycle.

Furthermore, the control/input panel includes a differencing switch 1 185 that allows the users to set the difference calculation of the IR testing system. In one setting the system subtracts input A from B; in the other setting B from A.

The control/input panel also includes a number of input and output signal connectors. Connector C1 is an input for receiving an input source from a battery or other power source. Connectors C2 and C3 are for receiving signals from the active and reference IR sensors. Connectors C4 and C5 output an integrated signal from their respective circuit path, C4 corresponding to the input from the IR sensor at Connector C2 and C5 corresponding to the input signal from the IR sensor at Connector C3. Connector C6 outputs the difference of the signals from the IR sensors after integration, differencing, and amplification. The respective signals are amplified and differenced according to the differencing switch and the gain selector settings.

FIG. 12 shows a detailed circuit diagram corresponding to the logic circuit specifying the circuitry arrangement of the logic circuit. As can be seen in FIG. 2, the number of pulses selected from the control/input panel is received by the logic circuit by way of thumbwheel BCD Decade Select Switches. The logic circuit receives pulses from the pulse generator from T2. These pulses are counted according to the corresponding circuitry and compared to the pulse count setting n1 . When the number of pulses counted reaches the pulse count setting the counter may be reset. The signal from the logic circuit also servers to reset the resettable integrators, so the signals received from the sensors are only integrated for the selected number of pulses. The integrators integrate for a period of time (Tr) dictated by the signal period (Ts) times the pulse count setting (n1 ) (or count number selected).

FIG. 13 shows the resettable integrators, amplification, and difference stages of the IR testing system. The integrators receive signals from the IR sensors and integrate the signals until given a reset command from the logic circuit. Also depicted is the difference switch. This switch is controllable from the control/input panel as mentioned above. Furthermore, the amplification mechanism is depicted, by which the user may choose an amplification level for the difference output. In the embodiment of FIG. 13 the signals are integrated first and then differenced. As a result different circuitry for the reset pulse is required as shown in reset circuitry 1305. Reset circuitry 1305 includes Resistor 1306 (10kΩ), Small-signal Bipolar Transistor 1307, 1309 (2N3451 ), Diode 1308 (1 N914), Resistor 1310 (20kΩ), Resistor 1311 (1.0MΩ), and Capacitor 1312 (0.01 μF). Instrument Amplifier and Variable Gain Amplifier 1320 provide for a total gain between 1-100; the Instrument Amplifier providing 10 and the Variable Gain Amplifer provided 0.1-10. Instrument Amplifier and Variable Gain Amplifier 1320 includes Resistor 1322 (5.61 kΩ), Operational Amplified 323 (AD622), Capacitor 1324 (0.1 μF), Capacitor 1325 (0.1 μF), Diode 1325 (1 N914), Diode 1326 (1 N914), Resistor 1327 (2kΩ), Resistor 1328 (22kΩ), Resistor 1329 (20kΩ), Resistor 1330 (22KΩ), Capacitor 1331 (0.1 μF), Operational Amplifier 1332 (LM318), Resistor 1333 (200Ω),Capacitor 1334 (0.1 μF), Resistor 1335 (19.8kΩ), Capacitor 1336 (0.1 μF), and connector 1337.

The IR testing system, also includes the Pulse Generator depicted in FIG. 14. The Pulse Generator receives a signal from the AC source 1410. In order to interact with the digital sections of the logic circuit, the pulses of the AC source are counted. In order to accomplish this, the pulse shaped circuit depicted in FIG. 14 is utilized. Digital pulses are output at connection point 1426. The pulse generator includes Resistor 1411 (4.7kΩ), Resistor 1412 (20kΩ), Resistor 1413 (4.7kΩ), Resistor 1414 (10kΩ), Resistor 1415 (2.67kΩ), Capacitor 2416 (0.1 μF), Operational Amplifier

1417 (LM318), +15V source 1418, -15V source 1419, Capacitor 1420 (0.1 μF), Capacitor 1421 (0.1 μF), Resistor 1422 (470Ω), Diode 1423 (1 N4733), Diode 1424, and Resistor 1415 (1.OkQ).

FIG. 15 shows in detail the signal conditioner, which serves to Reset/Clear the count of pulses received and reset the integrators. The first stage 1520 receives a signal from the comparator (see Fig. 3, comparator 360) at connection 1505. The first stage 1520 further includes Capacitor 1506 (22OpF), Resistor 1507 (10kΩ), Resistor 1508 (22kΩ), Quad Two Transistor 1509 (2N2222), and Resistor 1510 (15kΩ). Stage 2 1530 includes Operational Amplifier 1511 (555, 8 pin), Resistor 1512 (2.63kΩ), Resistor 1513 (5OkQ), Capacitor 1514 (22nF), and Capacitor 1515 (0.01 μF). In stage 3 1550, a reset signal to the counter is produced at connection 1516 when the count is met. Stage 3 1550 includes a connection to a +5V source 1517, Operational Amplifier 1518, Capacitor 1519 (0.1 μF), Diode 1521 (1 N914), Resistor 1522 (1OkQ), Diode 1523, and Resistor 1524 (330Ω). In stage 4 1540, a reset pulse to the integrator is produced at connection 1541 when the count is met. Stage 4 1540 includes Resistor 1525 (1 OkQ), Resistor 1526 (2OkQ), Resistor 1527 (1 OkQ), Resistor 1528 (1 OkQ), Resistor 1529 (2.67kΩ), Capacitor 1531 (0.1 μF), Operational Amplifier 1532 (LM318), Capacitor 1533 (0.1 μF), Capacitor 1534 (100μF), Capacitor 1535 (0.1 μF), Capacitor 1536 (100μF), Resistor 1537 (470Ω), Diode 1538, and Diode 1539.

FIG. 6 shows the Diode Network in greater detail. As is clear in the diagram, depending on the switching status of the Diode Network the IR testing device may be set to utilize either one or two integrators. Signals from the ferro-electric capacitors 1605 are received through connectors 1606, 1607, relating to capacitors A and B respectively. The signals are passed through the diode network 1608 and signals to integrators 1609 are produced. As shown connecting posts 1611 and diode network 1608 (diode network 1620 is shown in a different configuration) can be arranged in two integrators connection configuration or a one integrator connection configuration. In the two integrators connection configurations both integrators 1612 will product a signal. In the single integrators connection configurations only one of the integrators of integrators 1612 will product a signal. FIG. 17 depicts a setup for the connection of ferro caps to the IR testing system and an overall setup for the testing system. The signal generator 1730 sends signals to each sensor 1720 and the integrator apparatus 1735. Needle probes 1715 are utilized to make connections with the sensors due to the small size of the sensors 1720. A microscope 1745 is provided in order to see the needles 1715 connected to the ferro caps 1720 on such a small scale. Output from the sensors 1720 is sent to the integrator apparatus 1735. After the signal is manipulated by the integrator 1735, the signal is output to an oscilloscope 1740 to provide a graphic output of the manipulated signal. A thermal controller 1725 is provided for each sensor in order to vary the amount of infrared radiation received by each sensor.

FIG. 18 depicts a front panel silk screen of the apparatus, showing in basic form, the circuitry of the system. The apparatus includes a thumbwheel selector 1810, a counter 1815, and a comparator 1820 that delivers a reset pulse when the count on the counter 1815 is equal to the count on the thumbwheel selector 1810. Pulse shaper 1830 shapes the pulses received form the signal generator through connector 1821 . Connector 1822 and connector 1823 receive signals from the IR sensors being tested, one of which is exposed to radiation and the other which is not. These signals are fed into integrators 1835. Connectors 1824, 1825 provide an output of the signal after integration. Switch knob 1840 controls the switch 1845, which may be set to difference A and B or B and A. The signal is amplified at amplifier 1850 and the gain may be adjusted through gain selection knob 1855, which controls amplifier 1860. The signal is output at connector 1865.

Turning to FIG. 19, an example of the response of a ferroelectric hysteresis loop to a change in temperature is shown. As known in the ferroelectric art, a ferroelectric hysteresis curve is created by plotting ferroelectric polarizability, P, versus the voltage applied to the ferroelectric material. Two hysteresis curves are shown, one plotted for the ferroelectric material at a temperature T.sub.O and a second plotted for the same ferroelectric material at a temperature T.sub.1 , where T1 >T0. As shown in the figure, ferroelectric polarization typically decreases as temperature increases. This change is called the ferroelectric pyroelectric effect. In general, the fact that the spontaneous polarization P of a ferroelectric is a function of temperature T is written as: P=P(T), (3) and the pyroelecthc coefficient py is given by: p.sub.y=dP(T)/dT (4).

The pyroelecthc sensors sense the change in ferroelectric polarization caused by a temperature change. These pyroelectric sensors have many applications. As known in the art, when combined with suitable optics, an array of such sensors can form an infrared imaging system.

FIG. 20 shows an image sensor 700 with 2.times.2 array design. Image sensor 700 includes four sensor cells 701 , 702, 703, and 704. Each cell 701 through 704 comprises a pair of ferroelectric capacitors, such as 760 and 762, four diodes 764, 765, 766, and 767, and a pair of ground connections 768 and 769, all connected identically as shown in the cell 440 of FIG. 4. In addition, each cell includes a transistor, such as 706. The cells are arranged in to two columns, 710 and 711 , and two rows, 714 and 715. Each row, 714 and 715, is address via a word line 716 and 717, respectively. Each column, 710 and 71 1 , is pulsed via a read line 721 and 722, respectively. Each column, 710 and 71 1 , is read via a bit line 724 and 725, respectively. Each read line, 721 and 722, is connected to a read pulse source 730 and 732, respectively. Each read pulse source, such as 730, preferably includes a voltage source 735 connected to a ground 736. Each bit line 724 and 725 is connected to an integrator 740 and 742, respectively. Each integrator, such as 740, comprises a capacitor 752, an operational amplifier 754, and a reset transistor 765, with the non-inverting or reference input 758 of the operational amplifier 754 connected to a ground 759, and the inverting input 757 of the op amp 754 connected to the bit line, such as 724. The bit line also connects to the first electrode 762 of capacitor 752, while the second electrode 763 of capacitor 752 is connected to the output 764 of op amp 744 and to output 756. The gates of the reset transistors, such as 765, are connected to a source 767 of a reset signal. The gates of access transistors 706 and 707 in row 714 are connected to word line 716, while the gates of access transistors 708 and 709 of row 715 are connected to word line 717.

Image sensor 700 operates as follows. First, the reset signal goes high to short the integrating transistors, such as 765, and clear them. The reset signal goes low, and then the word line signal, such as Y.sub.0, of the selected row, such as 714, goes high to turn on the access transistors of that row. Each read line, such as 721 , is pulsed by its pulse source, such as 730, a sufficient number of times to produce readable output on the corresponding output, such as 756. The word line signal, such as Y.sub.O, then goes low, and the cycle is repeated for the next selected row. Only one row at a time is accessed, and each column shares an integrator.

Image sensor 700 is only intended to illustrate the structure and operation of an image sensor array. As known in the art, a practical array will include hundreds or even thousands of rows and columns. The array may not be a square array, but may also be rectangular, with more rows than columns, or more columns than rows.

A feature of IR sensor array is that background noise in the circuit is canceled. In one aspect, this noise cancellation is due to the fact that two ferroelectric capacitors which are essentially equivalent with respect to noise are used, and the ferroelectric switching charge for one is subtracted from the ferroelectric switching charge for the other. The ferroelectric capacitors in each cell, such as 310 and 320, are made in the same semiconductor process at the same time, are of preferably the same size, and are located very close to one another on an integrated circuit chip. Thus, non-random sources of noise, such as noise due to the capacitance of lines 721 and 724, or the electronic lines in the individual cells, will be present in both the positive cycle pulse and the negative cycle pulse, and will be subtracted out so only the difference signal remains. This noise subtraction increases the sensitivity of the sensor as compared to prior art sensors. The integration over many cycles also reduces the noise. Random noise increases with increasing number of cycles as the square root of n, the number of cycles. However, the output V.sub.O increases linearly. Thus, the signal to noise ratio will increase as the square root of n as the number of cycles increases. Since, for the sensor, the output voltage V.sub.O can increase all the way to the system voltage, that is, in practice the voltage has a much wider range, the noise can be reduced much more significantly than in the prior art. These noise reduction effects can be useful in many IR sensing applications other than the embodiments described herein. There has been described a novel infrared sensor and image sensor utilizing a pair of ferroelectric capacitors. Now that the sensor architecture has been described, those skilled in the art may make many variations. It should be understood that the particular embodiments shown in the drawings and described within this specification are for purposes of example and should not be construed to limit the disclosure, which will be described in the claims below. For example, if the array of FIG. 20 is turned ninety degrees, rows become columns and columns become rows. Further, word lines may be formed parallel to columns instead of rows, and bit lines may be formed parallel to rows instead of columns. Folded architectures known in the art may be employed. It is also evident that those skilled in the art may now make numerous uses and modifications of the specific embodiments described, without departing from the inventive concepts. It is further evident that the methods recited may, in many instances, be performed in a different order, or equivalent components may be used in the sensors, and/or equivalent processes may be substituted for the various processes described. Consequently, the disclosure is to be construed as embracing each and every novel feature and novel combination of features present in and/or possessed by the disclosure as herein described.

Claims

1. An infrared sensor comprising:

(a) a first ferroelectric capacitor, oriented such that said first ferroelectric capacitor is not exposed to radiation to be measured;

(b) a second ferroelectric capacitor, said second ferroelectric capacitor comprising a silicon substrate, an insulating layer, and a ferroelectric element;

(c) a subtractor that receives electric signals from both said first and second ferroelectric capacitor and finds a difference; and

(d) an integrator that receives electric signals from said subtractor and integrates said electric signals from said subtractor.

2. An infrared sensor as in claim 1 wherein multiple cycles of electrical signals are applied to said infrared sensor.

3. An infrared sensor as in claim 1 wherein said insulating layer comprises titanium, platinum, and strontium tantalate.

4. An infrared sensor as in claim 1 wherein said insulating layer comprises a first layer of titanium, a first layer of platinum, a first layer of strontium tantalate, a second layer of titanium, a second layer of platinum, a second layer of strontium tantalate.

5. An infrared sensor as in claim 4 wherein said first layer of titanium is between 10-30 nm in thickness.

6. An infrared sensor as in claim 4 wherein said first layer of titanium is approximately 20 nm in thickness.

7. An infrared sensor as in claim 4 wherein said first layer of platinum is between 30-70 nm in thickness.

8. An infrared sensor as in claim 4 wherein said first layer of platinum is approximately 50 nm in thickness.

9. An infrared sensor as in claim 4 wherein said first layer of strontium tantalate is between 30-75 nm in thickness.

10. An infrared sensor as in claim 4 wherein said first layer of strontium tantalate is approximately 55 nm in thickness.

1 1. An infrared sensor as in claim 4 wherein the total thickness of the insulating layer is approximately 250 nm.

12. An infrared sensor as in claim 4 wherein the ratio of the first and second layer of platinum to the first and second layer of titanium is adjusted to yield a higher density of hillocks.

13. An infrared sensor as in claim 4 wherein the ratio of said first and second layer of platinum to the first and second layer of titanium is between 1 :5 and 3:5.

14. An infrared sensor as in claim 4 wherein the ratio of said first and second layer of platinum to the first and second layer of titanium is between 1 :10 and 3:10.

15. An infrared sensor as in claim 4 wherein the ratio of said first and second layer of platinum to the first and second layer of titanium is approximately 2:5.

16. An infrared sensor as in claim 4, wherein the annealing at 650C of the Titanium/Platinum layer results in formation of a Titanium Oxide - Platinum interface.

17. An infrared sensor as in claim 4, wherein hillocks are created due to Titanium diffusion prior to the strontium tantalate layer deposition.

18. An infrared sensor as in claim 4 wherein the ratio of said first and second layer of platinum to the first and second layer of titanium is adjusted to achieve a maximum density of hillocks while retaining electrical connectivity.

19. An apparatus for testing IR sensors, the apparatus comprising:

(a) at least one low leakage integrator;

(b) a digital N-pulse selectable counter;

(c) a count comparator-reset command;

(d) an instrumentation amplifier;

(e) a gain-selectable amplifier; and

(f) needle sensors for contacting the IR sensors.

20. A method for testing an infrared sensor, the method comprising:

(a) providing an AC signal source;

(b) exciting a reference ferroelectric capacitor sensitive to infrared radiation;

(c) exciting an exposed ferroelectric capacitor sensitive to infrared radiation;

(d) subtracting a first signal from said reference ferroelectric capacitor from a second signal from said exposed ferroelectric capacitor to produce a third signal; and

(e) integrating said third signal.

21. A method as in claim 20, further comprising

(f) injecting said AC signal into a pulse-shaped circuit, wherein said pulse- shaped circuit counts pulses of said AC signal and compares the count of said pulses to a pre-set count.

22. A method as in claim 21 wherein the integrating of (e) is for a period of time, wherein said period of time is a pulse period times said pre-set count, wherein said pulse period is a frequency of said pulses of said AC signal.

23. A method as in claim 22 wherein said pre-set count may be selected by a gser.

24. A method as in claim 21, further comprising

(g) amplifying said third signal with a gain selectable stage.

25. A method as in claim 24 wherein a user may select an amplification level, said arηpiification level specifying the level of amplifying provided by said gain selectable stajge.

26. An apparatus for receiving a signal from IR sensors, the apparatus comprising:

(a), at least one low leakage integrator;

(b) a digital N-pulse selectable counter;

(c) & count comparator-reset command;

(d) <m instrumentation amplifier; and

(e) si gain-selectable amplifier.

27. The apparatus of claim 26, further comprising: (f). absolute value detectors.

2β. The apparatus of claim 27, further comprising:

(f) low pass filters.

2$. The apparatus of claim 26, further comprising:

(f) ;a resettable integrator.

30. The apparatus of claim 29, wherein the resettable integrator of (f) includes an amplification stage.