WO2009127377A1

WO2009127377A1 - Method for charging and discharging a capacitor block, and charging station for charging and consumer for discharging the same

Info

Publication number: WO2009127377A1
Application number: PCT/EP2009/002697
Authority: WO
Inventors: Richard Fodor
Original assignee: Forschungszentrum Karlsruhe Gmbh
Priority date: 2008-04-18
Filing date: 2009-04-11
Publication date: 2009-10-22
Also published as: DE202008017360U1

Abstract

A method for charging a capacitor block and for discharging a capacitor block to a consumer as well as a charging and discharging station are disclosed. Charging and discharging is individually process-controlled and monitored for each capacitor block. The capacitor block comprises n identical capacitors C or capacitor cells C that can be connected together in a purely parallel circuit, serial circuit combinations of parallel groups and individual capacitors, or a purely serial circuit. The capacitor block is charged by a voltage source with a time variable source voltage (U₀(t)) and is discharged as a current source to a time variable load. The load is discharged between two voltage thresholds in nominal operating conditions. The current time constant of the charging or discharging circuit is essential for charging and discharging the capacitor block, and so is the continuous repositioning of the serial stages of the current configuration of the capacitor block in order to continuously balance the charge among the capacitors while maintaining the current total capacity.

Description

Method for charging and discharging a capacitor block and charging station for charging and consumer for discharging the same

The invention relates to a method for charging a capacitor block or parallel capacitor blocks with a DC voltage source of the source voltage uo (t) and discharging a capacitor block thus charged in a load R _E (t) with the operating voltage range U _UBS <= u (t) <= UoB _S - There is a capacitor block of n equal capacitors C or capacitor cells C, which can be interconnected electronically from a pure parallel connection via series combinations of parallel groups and single capacitors to the pure series connection.

The natural charging and discharging of a capacitor is a known, simple electrophysical process, which is determined in time by the capacitance of the capacitor and the ohmic resistance in the charging circuit. The charging of a capacitor to its rated voltage U _N with a charger whose charging voltage is equal to the rated voltage is a theoretically infinitely long process. The minimum charging voltage should therefore be greater than the rated voltage of the capacitor C to be charged in order to disconnect it from the charger when the rated voltage U _{N is reached} . The complete unloading into a load R _E is theoretically an infinitely long process. However, devices to be operated electrically usually have an operating voltage range U _uB s <= u (t) <= U _0BSf in which they operate, ie when they fall _below the lower operating voltage _limit U _uB s they no longer operate in rated operation, such as one operated by a rechargeable battery Device, such as a screwdriver or a drill, is known.

If a capacitor is an energy source for operating a device, it can be discharged to a lower operating voltage _limit U _uB s. Ie. unused remains sitting on the capacitor the power 0,5CU _UBS ² . Only the energy difference 0.5C (U _N ² - U _UBS ² ) is used, or can be used.

In DE 602 Ol 615 an electric drive system for a vehicle is described, in which the drive system comprises, inter alia, one or more supercapacitors. The unit for controlling the the torque applied to the wheel of the vehicle uses the electric energy storage device different from the other electric power source, as a matter of priority, to supply the power necessary for driving the vehicle in case of request of drive torque. In the other case, namely the braking request, the electrical energy storage device is prioritized in relation to the use of any other braking device.

Capacitors C have the advantage over accumulators that they can be charged easily and quickly with a typical time constant τ = RC. More can be exploited the stored energy from two equal, initially parallel to each other sitting capacitors C, which are connected after reaching the lower operating voltage _barrier U _UBS serially to each other, since they are then, starting with the double lower operating voltage barrier, further discharged. The usable energy is then 0.5C (U _N ² - 0.5U _uB s ² ) - With more than 2 equal capacitors C or even with 2 different capacitors switching from parallel connection to serial circuits in a discharge problematic, because small serial partial capacities are charged or discharged faster than large ones, and even reloaded to voltage compensation, or destroyed in the worst case by exceeding the rated voltage U _N.

If a capacitor C is used as energy storage, it must first be charged to a charger. Usually and in the simplest case, this is done with a constant voltage source, which itself is connected to a power distribution network. Charging the same capacitors C in parallel to their nominal voltage means a stored energy of 0.5nCU _N ² . If this parallel connection is switched to the pure series circuit after reaching the lower operating voltage _limit U _uB s, the energy 0, 5 (C / n) U _uB s ² remains on the capacitors. Thus, the energy 0.5 (nU _N ² - (l / n) U _UBS ² ) C could be used. It has to be checked: Can the voltage of nü _uB s be controlled by isolation technology at the beginning of pure series connection? The larger n, the more sensitive this problem. This resulted in the object on which the invention is based, namely: it should be a capacitor block; or capacitors blocks made of or in each case of n identical, interconnectable capacitors C or capacitor cells C at a charging station, which acts as a voltage source with time-varying source voltage Uo (t) are charged up to a predetermined nominal voltage U _N = U _OBS and a charged Capacitor _block in an electrical load R _E (t) with a predetermined operating voltage range U _uB s <= u (t) <= U _oB s can be discharged.

The object is achieved by a method according to the method steps of claim 1, for which purpose an energy converter is used as charging station and thus DC voltage source uo (t) or a consumer R _E (t) according to the features of claim 8.

The method for charging a capacitor block with a DC voltage source with time-varying source voltage uo (t) and the method for discharging into a load R _E (t) with a predetermined operating voltage range U _uB s <= u (t) <= U _OBS is electrotechnically as loading the See capacitor block with a voltage source and discharge the charged capacitor block as a power source in a consumer. A capacitor block consists of n equal capacitors C, which can be interconnected with electronic means / switches, such as transistors, so that when charging or discharging the capacitors of the capacitor block are interconnected to a total capacitance C _tot .

The following method step is common for charging and discharging: A capacitor made up of the n equal capacitors C of a capacitor _{block is} defined as reference capacitor C _ref . At it, the voltage u _re f (t) is constantly tapped during charging and discharging and transferred to control the charging to a first, the voltage source and the capacitor block linking processor P ₁ and to control the discharge to a second, the capacitor block and the consumer R _E (t) linking processor Pn transfer. - A -

For charging the capacitor block from n equal capacitors C, the following method steps are carried out:

From the set of all possibilities of parallel and series connection of the n capacitors C of the capacitor block of serial stages n _s , with 1 <= n _s <= n, with parallel groups λ C of capacitors C, with 1 <= λ <= n, to each of a total capacity C _tot at least a subset including the pure parallel and series circuit is stored as a set for interconnection selection in the first processor Pi.

The voltage u _ref (t) on the reference capacitor C _ref of the capacitor block connected for charging to the DC voltage source uo (t) is monitored and compared by the first processor P ₁ to place the n capacitors C of the capacitor block through the processor P ₁ in one of the Charging time constant T ₁ = R ₁ C ^ ₅ and thus total load capacitance C _ges to account for load and voltage, so that the terminal voltage u (t) in the range: n _s * u _ref (t) = u (t) <= U _oB s <Uo (t) moves. U _OBS is the upper operating voltage _threshold to be observed. The charging current i _L (t) into the load R _L (t), the capacitor block to be charged, is meaningful. When the voltage u _ref (t) = U _N at the terminals of the reference capacitor C _ref is reached, the capacitor block is disconnected from the voltage source uo (t) and ready for discharging into a load, the load R _E (t). For charging, it is crucial that the circuit capacitances of the n capacitors of the capacitor block to be charged, which are stored in the processor P ₁ , be constantly checked as to which total capacitance C _ges , taking into account the source voltage u _o (t) or the charging current i _L (t) and the charging time is convenient or most convenient for the charging process. The sequence of the total capacities C _tot during the charging process must by no means be monotone. It is determined by the situation at the DC voltage source uo (t) and the temporal Ladeverlangen from the existing Verschaltungsmöglichkeiten.

For discharging the capacitor block from n equal capacitors C, the following method steps are carried out: How to charge is from the set of all possibilities of parallel and series connection of the n capacitors C of the capacitor block from serial stages n _s , with 1 <= n _s <= n, with parallel groups λC of

Capacitors C, with 1 <= λ <= n, for each total capacity C _ges at least a subset including the pure parallel and series circuit stored as a set for interconnection selection in the second processor Pn.

The discharge of a charged capacitor block in the connected load R _E (t) is started via the processor Pu with the pure parallel connection. The discharge, which is based on the current time constant τ _E = R _E (t) C _tot , proceeds in a similar way to the discharge of an RC element. For this purpose, a wiring sequence with increasing serial Verschaltungsstufe n _s and thus a monotonically decreasing sequence of total capacitances C _ges - When each reaching the lower limit of the operating voltage U _uB s, the processor Pn interconnects the n capacitors C of the capacitor _block in a higher serial stage n _s , The terminal voltage u (t) goes through the voltage _limits during the process: U _uBS ≤u {t) ≤U _oBS . Upon reaching the lower voltage _limit u _ref (t) = U _uB s / n at the reference _capacitor C _ref and thus the last connection from the discharge: the pure series circuit with the smallest total capacity C _ges = C / n, the capacitor block of the load R _E (t) separated.

Common to the process of charging and discharging and essential for this is the following process step or are the process steps during the existence of a current interconnection of the n capacitors of the capacitor block:

During charging and discharging of the capacitor block during each interconnection at 1 <n _s <n serial stages, the interconnection while maintaining the current total capacity C _ges for constant charge equalization between the capacitors C at least once cyclically over the electronic switching means such as interconnected. In the pure parallel connection of the n capacitors of the capacitor block with the total capacitance C _ges = nC all n capacitors are always loaded the same, a cyclic changeover in this interconnection is unnecessary. The charge or discharge of the capacitor block in pure series connection of its capacitors C also takes place uniformly, since the initial charge on all capacitors C is the same at the beginning of the interconnection state. For protection and thus for safety, all n capacitors could be short-circuited in parallel, for example, before the pure series connection, in order to force charge equalization. For long unused capacitor blocks such a protective measure is useful.

If the terminal voltage u (t) between the capacitor _block and the load is in the range U _uBS <u (t) = n _s * u _re f (t) <U _oBS , from n = 4 capacitors C per capacitor _block can be used in one _{switching stage} serial interconnection, in which there is a sequence of at least two total capacitances C _tot , are selected and interconnected by the processor P ₁₁ because of between a short-term and a long-term discharge (claim 4).

If the terminal voltage u (t) between the capacitor _block and the load reaches the lower operating voltage _limit u (t) = U _uBS , starting at n = 3 capacitors C per capacitor _block , the n capacitors C from the processor P _{11 are converted} into an at least next higher serial interconnection connected stage n _s <= n, ie, the new total capacity C _ge s for further discharge into the load R _E (t) has become lower.

When the lower limit u _ref (t) = U _uB s / n is reached during the final purely serial connection of the n capacitors, the capacitor _block is taken from the load R _E (t). When unloading - in contrast to loading - when changing the serial interconnection stages a monotonically decreasing interconnection sequence for the total capacity C _{ges is} passed through. In a fixed serial stage n _s , this must not be the case when unloading, if more than one total capacity switch is possible (see below). There can be unloaded for a short or long time.

Generally applies to a capacitor block of n equal capacitors C, of the pure parallel circuit, nC, via serial stages n _s of parallel groups of λ capacitors C, with 1 <= λ <= n, up to the pure series circuit C / n are interconnected can that the smallest total capacity of the serial stage n _{s is} greater than the maximum total capacity of the next stage n _s + 1. The operating voltage range U _uB s <= u (t) <= U _oB s is to be observed when unloading in the consumer R _E (t) due to a safe nominal operation. A capacitor block; With capacitors C charged to nominal voltage, it would be possible to connect them directly to the pure series circuit with C _ges = C / n for discharging into the load without safety device and thus have a terminal voltage of u (0) = nU _N at the beginning of the discharge. A capacitor block would have to be dimensioned at least isolation technology dimensioned. It would be problematical milder that the n capacitors C of the capacitor block charged to rated voltage U _{N are connected} at the beginning of the discharge immediately into a serial connection with n _s > 1. It would then be u (0) = n _s U _N. Although these cases are not a problem in terms of realization, they should be left out of this context.

According to claim 2, several capacitor blocks can be charged in parallel to the voltage source uo (t) during charging and discharged in parallel into the consumer R _E (t) during discharging. The capacitor blocks are decoupled from each other via their individual processor P and thereby charged or discharged independently of the others. Ie. one capacitor block does not see the other connected, but the DC voltage source Uo (t) or the consumer R _E (t) sees the connected capacitor blocks in parallel.

According to claim 3, the discharge of the fully charged capacitor block starts in the consumer R _E (t) with the largest total capacity

Cges = ⁿ C and the underlying discharge time constant τ _E = R _E {t) nC. The terminal voltage u (t) moves in the range:

U _uBS = ^ ≤ u (t) ≤ U o _BS = U _N.

If the terminal voltage u (t) reaches the lower limit voltage threshold U _U B _S, the processor PII switches over to a serial stage <= n _s . It is then based on the discharge time constant τ _E = R _E {t) C _gesaklu . At the beginning of this new interconnection u (0) <= n _s U _uB s <= U _N. This consideration by the processor P ₁₁ , the rated voltage for the consumer R _E (t) is not exceeded. For the following wiring up in the direction of pure series connection, a monotonically decreasing sequence of the total capacitances takes place, in which at the beginning of each new connection it can also be: u (0) = U _{oBS -U} _N , ie the upper voltage threshold U _{OBS is} no longer reached.

In claim 4, therefore, the number n of the capacitors C of a capacitor block is specified. Then n = 2 ^m , with m = 0; 1; 2; ..., the interconnection is based on the pure parallel circuit n _s = 1 and transitions into the new interconnection in such a way that with respect to the new serial stage: n _sneu = 2n _sall . With this setting, the terminal voltage in each interconnection moves exactly between the

_{Limit voltage thresholds} : U _uBS = - ≤u (t) ≤U _N = U _oBS , where: M (O) _{n ^} = 2 * -.

This has the advantage that the terminal voltage for the current C _geSak tu always the entire voltage difference: .DELTA.U = U _OBS - U _UBS , with the underlying current time constant τ _L = R, C _ges or τ _E = R _L (t) C _ges runs through and thus each time to be traversed time interval for the terminal voltage u (t) is the longest.

If there is more than one possibility of interconnection in one stage of n _s serial stages, ie different total capacitances C _tot , which is the case for the first time with n = 4 capacitors C at n _s = 2 serial stages, then according to claim 5 Processor Pn be switched between these total capacities as long as the terminal voltage of the capacitor _block between the two _{threshold voltage thresholds} : U _uBS <u (t) <U _oBS = U _N moves. Thus, the underlying discharge time constant τ _E = R _E (t) C _{ges is} variable during this discharge interval. This can also be done with an odd but also an even number n of capacitors C, in which: 2 ^m ≠ n, however, then not up to the pure series circuit C / n, but only up to a maximum of 2 ^m <n.

The charging station with its electrical effect as a DC voltage source at the output is a photovoltaic system, for example, which is placed in a remote area and the light / radiation is exposed, or the photovoltaic system is on the roof of a

Building mounted. Such a system can be a performance very scattering system, which depends on the available Einstrahlfläche. Solar cells can be dimensioned by series and parallel connection to any power outputs. The electrical output of the solar surface is available as a voltage source, wherein the electrical power output varies with the Einstrahlintensität and therefore is variable over time. The source voltage uo (t) is therefore variable.

Other energy converters are gas / air powered systems. Here, a mass flow is used to drive a generator. This is very broad and covers such areas as wind turbines, hydropower plants in the form of turbines, walking time operated facilities to point to energy conversion areas only by way of example. For such an energy conversion principle of mechanical energy (kinetic energy of a mass flow) are electrical generators, generally three-phase generators, as an actual converter necessary whose electrical output voltage is a speed-dependent AC voltage. The rectifier is connected directly to the electrical output of the generator, so that the output of the rectifier acts as a DC voltage source with the speed-dependent and therefore time-variable source voltage u _o (t).

The advantage of a capacitor memory with n equal capacitors C would be that due to its highly variable overall capacitance C _ges between nC and C / n and thus the variability of the load R _L (t) for the voltage source uo (t) (see below in the description of Embodiment), a mechanical transmission between the rotor and generator could be completely eliminated, which would be a weight saving and would save the maintenance of the transmission in the generator room.

Decisive for the usefulness and effectiveness of the method are on the one hand the possibilities of interconnecting n equal capacitors C of a capacitor block from the pure parallel connection of all n capacitors C with the highest total capacitance C _ges = nC via mixed interconnections from serial parallel groups to purely serial connection of the n capacitors C with the smallest

Total capacity C _ges = C / n and on the other hand, the constant cyclic repositioning of the serial interconnection stages while maintaining the current total capacity C _ges during a current interconnection. The latter, the constant charge equalization among the capacitors of a current overall interconnection, is critical to the charging or discharging of a capacitor block or capacitor blocks. Namely, conventional accumulators can not be balanced with each other in terms of their charge among each other.

Therefore, when charging the capacitor block, taking into account the terminal voltage u (t) and the state of charge u _ref (t), it is always possible to connect it to a total capacity C _{tot which} fits best. However, can also quickly in pure series circuit at sufficiently large uo (t), because then τ _L = -R, C is based, or slowly in maturing ner parallel connection, because then

is underlying, to be loaded. During unloading, it is expedient and expedient to start unloading with the greatest total capacity C _ges = nC.

Purely technically, the unloading could be started with an interconnection with a smaller total capacity, this would affect the area of the voltage multiplication, which should not be considered here. When connecting to a sequence connection for discharging, in order to return to the range U _uB s <= u (t) = n _s * u _re f (t) <= U _OBS ZU, a connection with a smaller overall capacitance C _{ges must be} connected , wherein the sequence of the total capacitances C _ges in increasing the serial stages is accompanied by a monotonously decreasing sequence of the successive total capacities.

In the following, the method for charging a capacitor block or parallel capacitor blocks with a DC voltage source of the source voltage uo (t) and discharging a capacitor block into a load R _L (t) with operating voltage range U _UBS <= u (t) <= U _OBS? with the help of the drawing explained in more detail. The drawing consists of Figures 1 to 8, which show in detail:

Figure 1 shows the situation when loading;

FIG. 2 shows the situation during unloading;

FIG. 3 shows the situation for charge equalization;

FIG. 4 shows the situation for transhipment;

FIG. 5 shows the connection options for 1, 2 and 3 capacitors;

FIG. 6 shows the connection options for 4 capacitors;

FIG. 7 shows the connection options for 5 capacitors;

FIG. 8 shows the connection options for 8 capacitors; ,

FIG. 9a, the interconnection device;

FIG. 9b shows the first position of the changeover;

FIG. 9c shows the second position of the changeover;

Figure 9d, the third position of the changeover.

In Figure 1, the purely electrical situation when charging a capacitor block of a total capacity C _ges circuit technology is shown. On the left side of the picture is the energy converter, which converts a primary energy E _prim , light intensity, air, gas, water into the converted energy form E _e i. For the connected capacitor block of a current total capacitance C _ges, the energy converter acts as a DC voltage source with the time-varying source voltage Uo (t) and the internal resistance Ri. The capacitor block is the load R _L (t) for the DC voltage source during charging and consists of n equal capacitors C 9, depending on the electrical situation with the interconnection device according to the figure 9 interconnected or are purely parallel, purely serial or in series stages of purely parallel groups of at least one capacitor C. Due to the cyclical conversion of the serial stages during a current Interconnection with the measurement at one of the n capacitors of the capacitor block, the reference capacitor C _re f, the state of the capacitor block charge and thus voltage constantly detected. The capacitor block C _tot is coupled via the processor Pi to the DC voltage source, monitored by him and controlled with respect to the charging process. Between the DC voltage source and the connected load R _L (t) there is the terminal voltage u (t), which is why the charging current i _L (t) flows through the load R _L (t). The capacitor block has the terminal voltage U _E immediately before charging. For the following consideration it is assumed for the sake of simplicity that the source voltage uo (t) = Uo = is constant. This facilitates the illustration, there must be provided anyway, that the temporal change in the source voltage duo (t) / dt is very small and within a few charging time constant of the electrical charging circuit, τ _L = Ric _ges to the source voltage uo (t) changes little. This is reasonable considering the rate of change in incident light intensity or the torque of a mechanically coupled generator turbine.

For U ₀ (t) = U ₀ = constant resulting from the charging circuit, see Figure 1, then the time-dependent charging current:

the time-dependent terminal voltage:

u (t) = U ₀ - (U ₀ -U _E ) e ^R ' ^c ° "and from both relationships the time-dependent load R _L (t) at the voltage source during charging:

Depending on the remaining on the capacitor storage discharge voltage U _E results in a load resistance at the beginning of the loading of

^LK) U ₀ -U _E '

The total capacity is only in the charging time constants τ _L = R, C _ges . The initial current I _L (O) AT the beginning of a new connection is always:

The underlying charging time constant is greatest for pure parallel connection with total capacitance C _ges = nC and smallest for pure series connection with the total capacitance C _ges = C / n, so that is the interconnectable total capacitance Cges of the capacitor block of the range:

-R ₁ C ≤τ _L ≤nR, C n selectable. If: NU _N <U ₀ , the fastest possible charge of the capacitor block is given in pure series connection with the charging time constant τ _u = -R ₁ C. n

Is: n _s U _N <U _Q <nu _N, stands for the fastest possible charging of the capacitors block the smallest total capacitance C _tot of the n _s -th serial staging with the underlying charge time constants ^ _Ln1 = R, C _total available for this purpose.

The voltage source and thus the energy converter can therefore because of the time-varying load R _L (t) with great freedom for the current total capacity C _ges variable between a long-term charge, because τ _Lp = ni ?, C - pure parallel circuit -, and a short ¬

early charge, because τ _u = - * R ₁ C - pure series circuit -, loaded n. Charge time constants τ _{L in} between can be set up by means of corresponding serial increments n _s , or with sufficient available charging time t and the voltage situation U _N <u _o (t), the natural charge of the capacitor block with the greatest total capacitance Cgesmax = n * C can be carried out ie without necessary repositioning of the serial stages n _s , because n _s = 1.

From these considerations, it is immediately apparent that the charging of the capacitor _block can only be used if the condition: u _o (O) = U _o > U _E is present at the beginning of the charge, at which actual total capacitance C _ge ak _tu always. After three charging time constants τ = RiC _ges , the load resistance would be: i? _L (3r) = ( ^U ° e ³ -l) i? , If the voltage u _re f (t) = u (t) / n _s = U _{N is} reached at the reference capacitor C _ref , the processor P _{1 takes} the capacitor block; from the DC voltage source. He is available for unloading.

The consumer or consumers R _E (t) is or are operated in the following voltage range between two voltage _thresholds U _uB s < ⁼ u (t) <= U _OBS ⁼ U _N. FIG. 2 shows, by way of example and for the sake of clarity, the circuitry situation with a capacitor block as a current source for the consumer. The second processor P ₁₁ in turn detects the voltage u _ref (t) at the reference capacitor C _ref and compares with the terminal voltage u (t). At the beginning of the discharge of the capacitor block this is connected with its n equal capacitors in the pure parallel circuit and thus has the largest total capacity C _ges = nC. Assuming that the consumer does not change in time or at most slowly and with little change, the behavior of the discharge can be considered with good approximation via the current and voltage relationships derived from FIG. 2. It is then namely:

or more generally, depending on the serial staging n _s :

with the underlying time constant for the discharge: τ _E -R _E C _tot , where U ₀ (n _s ) means the upper voltage at the beginning of the n _s _-stufigen interconnection, which must be smaller U _oB s. Since upon reaching the lower voltage _threshold U _uB s for a rated operation of the load R _E (t) are switched to another circuit, in such a way that the terminal voltage u (t) again in the operating voltage range U _uB s <= u (t) < = U ₀ B _S comes to rest, must be connected to a higher serial level n _s <n. For the switchover from the pure parallel connection to the following two-stage connection n _s = 2, this becomes quickly apparent. If, in pure parallel connection, n _s = 1, the lower threshold U _{uBS is} reached during the discharge, the initial voltage at n _s = 2 u (0) = 2U _uBS , at n _s = 3 u (0) = 3 U _uBs , general u (0) = n _s U _UB s in the new interconnection from the pure parallel connection out. If the serial stages n _{s are} successively passed under the respective discharge, the voltage end conditions are to be taken over as the voltage starting condition in the subsequent connection. The computational determination to do so is expensive. However, the above considerations make the unloading process during each interconnection basically clear.

On this basis, a charging station, capacitor blocks are dimensioned and adaptable to a consumer.

When charging the capacitor block between the serial stages 1 <= n _s <= n to the source voltage U ₀ (t) and connected as a load back and forth, even with a serial stage n _s between the existing there stage equal opportunities must During unloading, the number of stages n _s when reaching the lower threshold voltage in the new interconnection can be increased. However, this is not problematic if, when changing from one interconnection to another - when charging or discharging - all n capacitors have the same charge and therefore the same voltage. The need is highlighted by the following brief considerations for charge balancing and transhipment.

Figure 3 shows two parallel capacitors of capacitance mC and nC, m and n are integers. Reality is considered the circle of the two capacitors mC, resistor R _a and the open switch. Before switching on, the voltage U _n o or the voltage U _m o is present at both capacitors. With the switch-on, the equalizing current i _A (t) begins to flow. At the beginning of the compensation process, the highest balancing current i _A (Q) = - -, which flows after 3

^R A

Time constant τ _A = R _A C for the charge compensation significantly m + n is reduced, namely e ^"3 = 0.049787 ... or about to 4.74% (e ^{~ 5} = 0.00674 or 0.674% or e ^"10 = 0.0000454 or 0.00454%), whereby there is almost equal stress between and thus charge equality on the two capacitors. This balancing process is carried out at closed switch off automatically. A superimposed current I _E in this parallel circuit and out of her does not affect the charge balance.

For the dimensioning of a charging station and the consumer or vice versa of a capacitor block of n equal capacitors, the two time constants are: τ _L = R _i C _tot for charging and τ _E = R _E C _tot for

unloading, in relation to the time constant τ _A = R _A C for the m + n

To put in charge balance relationship, ie the repositioning of the serial stages of a current wiring must be at least several times n _s going quickly than the interconnection in a Sequence Ever circuit.

In the case of a series connection of two capacitors nC and mC, there is the risk of reloading the smaller capacitance, and the faster, the greater the difference in capacitance, if the two serial capacitors come to rest in a closed circuit. FIG. 4 shows the situation by way of example when the current iu (t) flows through the resistor R _L and the two capacitors nC and mC. In such a circuit no current flows when there is opposite voltage to the two capacitors. The voltage nU _nC -mU "at the capacitor nC becomes: u _nC (∞) = - -, and at the capacitor mC: m + n

^u _m c ( ^∞ ) ⁼ ~ ~ ^and thus u _c + u _c = 0. The reloading problem is clear from the two counter differences m + n. Such a situation must be avoided. This is granted by the constant cyclic switching of the serial stages of a current interconnection C _tot . In a pure parallel connection, this is not necessary because of the natural self-compensation. In order to be able to interconnect in the pure serial interconnection without any problem, this is absolutely necessary until the immediate Cg _es switchover because of the eventual DC discharge.

The circuit groups of an interconnection consist of pure parallel circuit groups, which are in series with each other or from one series mixture of parallel circuit groups and serial capacitors, with respect to the total generative capacities framed between the pure parallel circuit and the pure series connection of all capacitors C of the capacitor block. For n = 1; 2; 3, the advantages of changing the interconnection of the capacitors C of a capacitor block equipped in this way are indicated successively. FIG. 5 shows the case for a capacitor C, two capacitors C and three capacitors C, each as a capacitor block. A capacitor C is trivial here. There is only one interconnection option. The energy more of it can Ei = 0.5C (U _O U _U ~ BS ² BS ²⁾ ent ^¬ taken not.

In a capacitor block of two capacitors, there are the two interconnection options of pure parallel and the pure series circuit. The extractable energy is E ₂ = 0.5C (2U _oB s ² - (1/2) U _UBS ² ) - Two interconnections can be set, namely Cg _es = 2C and Cg _es = C / 2, so n _s = 2 serial stages. Both are implied.

If the capacitor block consists of three capacitors C, the three options shown for the interconnection are C _ges = 3C; 2C / 3 and C / 3, so n _s = 3 serial stages. Thus, here the energy E ₃ = 0.5C (3U _O Bs ² - (1/3) U _U BS ² ) can be removed. The interconnection paths are passing through the sequence: 3C; 2C / 3; C / 3, or only the consequence: 3C; C / 3; back and forth for loading and from the higher total capacity to the lower for unloading.

FIG. 6 shows all 5 possibilities of the interconnection for 4 capacitors of a capacitor block. There are n _s = 4 serial stages, whereby in the second serial stage, n _s = 2, there are now for the first time two possibilities of interconnection. On the right in the picture next to the, the interconnections the total capacities are registered, which decrease monotonically upwards, in the second serial stage from left to right. It can thus long term on the sequence: 4C; C; 2C / 5; C / 4, and short over the sequence: 4C; 3C / 4; 2C / 5; C / 4, to be unloaded. If no threshold voltages are touched during charging and discharging in the circuits of the second serial stage, it is possible to switch between them in this voltage band or back and forth, this is indicated by the dashed horizontal arrow. indicates (increasingly diverse in Figures 7 and 8). Both sequences can be traversed completely or incompletely, ie by skipping at least one sequence n _s . The arrows between the possible total capacities indicate only the complete passage for clarity. As explained above, the energy E4 = 0.5C (4U _oB s ² ~ (1/4) U _U BS ² ) can now be extracted accordingly.

FIG. 7 shows all interconnection options of n = 5 capacitors C, there are 7 interconnection options. With two options in the second serial stage, n _s = 2, in the third serial stage, n _s = 3, and one more each. Right next to the circuits, the total capacities are written. There is again a vertical sequence of total capacities for long-term unloading, namely the right pass, and the short run left vertical. With two and three serial stages, at U _uB s <= u (t) <= U _{OBS can} be reversed again. The two crossed arrows point out. Here, accordingly, the extractable energy is E ₅ = 0.5C (5U _OBS ² - (1/5) U _UBS ² ).

From Figure 8a, the development of the variety of possible interconnections and thus the generation of total capacity can be seen. The capacitor block now has 8 interconnected in the manner indicated capacitors C. There are a total of 22 possibilities of interconnection. Based on claim 3, the interconnection of the 8 capacitors C of the capacitor block for discharging should proceed in such a way that the terminal voltage u (t) in each serial stage the entire range between the upper operating voltage _threshold U _0BS and the lower operating voltage _threshold

UUBS, ie: U _uBS = - ≤ u (t) ≤ U _N = U _oBS . The interconnection options for this are outlined in the wiring development of FIG. 8a. This applies to the pure parallel connection, n _s = 1, via the possibility of n _s = 2 for the serial step, further to that of the serial step n _s = 4 and finally n _s = 8. For ns = 2, as long as U _uBS = - <u (t) <U _N = U _oBS , λ = 4 possibilities in this Time interval arbitrarily reconnect according to expediency or just to select at least one interconnection. The same is true for ns = 4, just maximum with λ = 5 possibilities (see the dashed arrows in Figure 8b). Will the sequence of serial staging be: n _s = 1; 2; 4; 8, this results in a monotonous decrease in total capacities from 8C through the serial stages to C / 8. It is general that the smallest total capacity of a serial stage n _s is greater than the maximum total capacity of the next stage n _s + 1, here with 1 <= n _s <= 8 (see Figure 8b). FIG. 8b further shows the manifold possibilities of the interconnection via the serial stages n _s = 2 and 4, which is indicated by the arrow tufts. With the smallest time constants, the left edge path becomes: 8C; 7 / 8C; 5 / 16C; 1 / 8C selected, with the largest time constants the right edge path: 8C; 2C; 1 / 2C; 1 / 8C, otherwise in between. It can be taken n = 8 the energy E ₈ = 0.5C (8U _OBS ² ~ (l / 8) U _uB s ² ). It can be seen from the examples: FIGS. 5 to 8b how, as n increases, a capacitor block can always be charged and discharged more finely.

The determination of all possible interconnections of even more capacitors can be safely developed according to the method shown. As a result, the interconnections and the associated total capacity can be entered into the two processors for loading and unloading and the links for monitoring and controlling the processes can be impressed. It is remarkable how the difference between successive total capacities from the monotonically decreasing sequence of all possible total capacitances to a capacitor block of n equal capacitances C in the direction of pure series connection, Cges = C / n, becomes ever smaller. A technically usable sequence of interconnections to total capacities for a capacitor block therefore advantageously utilizes a monotonically decreasing total capacity subsequence, which omits more and more interconnection stages in the pure series connection, as was explained for the case n = 2 ^m above, in order to interconnect into the next stage reach the upper operating voltage threshold or get close to it so that there is sufficient operating voltage range for the consumer for the current interconnection and because of the discharging time constant τ _E = R _L (t) C _geSa k _t u at least one override cycle can safely be run (see below).

Decisive for the implementation of the method of charging is the setting of a currently necessary interconnection of the n capacitors C of a capacitor block to a total capacitance C _tot and the cyclic conversion of the serial stages 1 <n _s <n during an assumed interconnection while maintaining the current total capacity C _ges - All Verschaltungsmöglichkeiten in the manner given above can with 3 (n - 1) switches, which always sit in the same place so fixed, are set up. This is demonstrated by way of example using the example of a capacitor block with n = 5 identical capacitors C in FIG. 9 for the case of the total capacitance C _ges = C / 2 and the step response n _s = 3.

FIG. 9a shows the arrangement of the 5 capacitors C and the connection with the 3 (n-1) open switches. Between two consecutive, equally arranged capacitors C sit 3 switches, two of which connect the same capacitor plates, one of the two different. If the terminal voltage u (t), as indicated in the figure, tapped, the lower plate of the first, in the figure 9a left capacitor is the potential reference point, as indicated by the grounding symbol representative.

In FIGS. 9b to 9d, the interconnection of the five capacitors is shown while retaining the total capacitance C _ges = C / 2. These figures 9b to 9d show the conversion of the three serial groups for constant charge equalization in the 5 capacitors involved.

In FIG. 9b, the position of the three groups consists of the two serial groups of two parallel capacitors C, followed serially by the one capacitor C.

In FIG. 9c, the conversion is made such that a capacitor C is followed by the two serial groups of two parallel capacitors each. In Figure 9d is further converted, as a group of two parallel capacitors C series a capacitor C and this in turn serially follows the second group of two parallel capacitors C. Thus, the cycle of changeover while maintaining the fixed Total capacity once done. It may be this indicated cycle of

Repositioning or the opposite clocked.

With a complex, potential-free switch, on the one hand, the change of the interconnection can be switched to a currently required total capacity and, on the other hand, the repositioning of the groups of the current interconnection can be switched while maintaining the total capacity. Switching to a new interconnection to a different total capacity will be slow compared to repositioning, which must be much faster if at least one complete conversion cycle is to be switched. In DE 10 2008 010 417, for example, such a potential-free / potential-unbound switch is described, with which a corresponding number of switches, namely 3 (n-1), are switched in the described manner on the one hand by a current interconnection of the n capacitors C in a new interconnection and on the other hand, during a current interconnection, the serial groups of the interconnection can be cyclically repositioned at least once while retaining the total capacitance C _ges .

Due to a first construction of a capacitor block of 10 equal capacitors at which the charging and discharging with repositioning of the serial stages of a current interconnection has been investigated, a demonstration object is currently under construction. The energy converter is a solar-electric device in the form of a Fotovoltaikanla- ge of 4 solar cells ä 80 and thus 320 W peak power and a voltage of 16.5 V. Thus, the capacitor memory of a vehicle is loaded, the drive motor as a DC motor with 500 W and 36 V direct current voltage The capacitor block consists of 66 capacitors of 5 000 F, which can be recharged to a maximum of U _N = 2.7 V. Thus 10 Wh of sunshine 800 Wh are stored. That's enough to run the DC motor 1.6 h.

Claims

Claims:

1. A method for charging at least one capacitor block with a DC voltage source of the source voltage U ₀ (t) and for discharging at least one capacitor block Ri, (t) thus charged into a load R _E (t), which in an operating voltage range U _UBS <= u ( t) <= U _{OBS is} operated, wherein a capacitor block consists of n equal capacitors C or capacitor cells C, which can be interconnected by a pure parallel connection via series combination of parallel groups and single capacitors to the pure series connection,

consisting of the steps:

on a selected capacitor of the n capacitors C of the capacitor block, the reference capacitor C _ref , the voltage u _{ref is} measured during charging and discharging and for controlling and monitoring the charging to a first processor P ₁ and for controlling and monitoring the discharge to a second processor Transmit Pn;

A. Load: from the set of all possibilities of the parallel and series connection of the n capacitors C of the capacitor block from serial stages n _s , with 1 <= n _s <= n, with parallel groups λ C of capacitors C, with 1 <= λ <= n, to each of a total capacity C _total is at least stored a subset including the pure parallel and series connection of the amount to Verschaltungsauswahl in the first processor P _1, the beginning of each connection of the n capacitors to a current total capacitance C _tot is the measurement the initial terminal voltage u (0) and the charging current I _L (O) in the processor Pi, the internal resistance Ri (O) of the voltage source uθ (t) determines the voltage u _re f (t) on the reference capacitor C _ref des for charging the DC voltage source u _o (t) connected capacitor block is monitored and compared by the first processor Pi chen to the n capacitors C of the capacitor block through the

Processor P ₁ into a charge time constant τ _L = R _j C _ges and thus

_Comply with load-taking total capacity C _{tot, which} complies with the voltage range with the upper voltage _limit U _OBS : n _s * u _ref (t) = u (t) <= U _{o BS} <U ₀ (t); when the voltage u _ref (t) = U _{N is reached} at the terminals of the reference capacitor C _ref , the capacitor _block is disconnected from the voltage source U ₀ (t);

B. Discharge: from the set of all possibilities of parallel and series connection of n capacitors C of the capacitor block of serial stages n _s , with 1 <= n _s <= n, with parallel groups λC of capacitors C, with 1 <= λ <= n, at least one subset including the pure parallel and series circuit is stored as a set for interconnection selection in the second processor P ₁₁ for each total capacitance C _ges ; During the discharge of the capacitor block into the consumer, the measurement of the terminal voltage u (t) and the discharge current i _E (t) in the processor Pn determines its current resistance R _E (t), the discharge of a charged capacitor block into the connected load R _E (t) is started via the processor Pn with the pure parallel connection, which is based on the current discharge time constant τ _E ⁼ RεC _ges , wherein a wiring sequence with increasing serial Verschaltungsstufe n _{s is} driven, wherein upon reaching the lower limit of the operating voltage U _uB If the processor Pn connects the n capacitors C of the capacitor block to a higher serial stage n _s , when the lower voltage _limit u _ref (t) = U _uB s / n at the reference capacitor C _ref is reached, the capacitor _{block is disconnected} from the load R _E (t) separated;

during charging and discharging of the capacitor block during each interconnection at 1 <n _s <n serial stages the

Interconnection while maintaining the current total capacity C _ges for constant charge equalization between the capacitors C cyclically changed at least once.

A method according to claim 1, characterized in that a plurality of capacitor blocks when charging in parallel at the voltage source U ₀ (t) and during discharge parallel to the load R _E (t), wherein the capacitor blocks are decoupled via their individual processor P mutually independent be loaded or unloaded by the others.

A method according to claim 2, characterized in that when unloading the capacitor block of the processor Pn, starting from the pure parallel circuit, after reaching the lower

Operating voltage U _uBS = ^oBS at most in the serial stage n _s

* 5, whereby the initial voltage u (0) for the interconnection of the serial stage n _{s can be} maximally u (0) = U _oBS = U _N and the terminal voltage always in the voltage range:

U _uBS = - ≤ "(0 ≤ U _oBS n., The discharge is based on the current discharge time constant τ _E = R _E (t) C _saktu , wherein the upper voltage _limit U _{OBS is} at most equal to the rated voltage U _{N of} the capacitors C.

4. The method according to claim 3, characterized in that for discharging a capacitor block in the load R _E (t) by the processor Pn a wiring sequence of serial stages with monotonically decreasing total capacity is traversed, in which the following number of stages is twice the previous, n _sneu = 2n _sall .

5. The method according to claim 4, characterized in that in the

Voltage range of the terminal voltage at the capacitor _block between: U _uBS <u (t) <U _oBS = U _N , between different available total capacitances C _{ges of} a serial stage n _s can be switched over.

6. A charging station for electrically charging capacitor blocks and loads for discharging a capacitor block, wherein a capacitor block consists of n equal, interconnectable capacitors or capacitor cells C, characterized in that:

the charging station is a device for energy conversion, which acts on its energy extraction side as a voltage source with time-varying source DC voltage uo (t),

the consumer R _E (t) with a charged capacitor _block as a current source in a predetermined voltage range U _uB s ^<= u (t) <= U _{oBS is} operable,

a first processor P ₁ during charging, the charging station and the connected capacitor block monitoring and control technology coupled, monitors the capacitor block and sets the necessary interconnection C _tot and controls the cyclic serial changeover during a current interconnection,

a second processor P ₁₁ during discharging couples the load R _E (t) and the connected capacitor block, monitors the capacitor block and adjusts the interconnections and switches the cyclic changeover during a current interconnection.

7. charging and discharging station for capacitor blocks according to claim 5, characterized in that the charging station is a photovoltaic system, the one in its intensity in time fluctuating light incidence is suspendable.

8. charging and discharging station for capacitor blocks according to claim 6, characterized in that the voltage source is an electric generator with a rectifier at its output and the generator is operable at a time not constant speed.