WO2009122365A2

WO2009122365A2 - Ultra wide band demodulator

Info

Publication number: WO2009122365A2
Application number: PCT/IB2009/051371
Authority: WO
Inventors: Gerrit Van Veenendaal; John R. Long; Yunzhi Dong
Original assignee: Nxp B.V.
Priority date: 2008-04-04
Filing date: 2009-04-01
Publication date: 2009-10-08
Also published as: WO2009122365A3

Abstract

The invention relates to a Ultra Wide Band signal demodulator comprising a phase shifter (Phase) circuit for phase shifting an input signal (Vin) and for delivering a phase shifted signal to an amplifying circuit (Gain) for amplifying the phase shifted signal and for generating an amplified signal (VDO). The demodulator further comprises a multiplier (Multiplier) for mixing the input signal with the amplified signal.

Description

Ultra Wide Band Demodulator

FIELD OF THE INVENTION

The invention relates to a Ultra Wide Band (UWB) demodulator.

BACKGROUND OF THE INVENTION

UWB-FM radio system is a novel wireless communication system developed as a low cost solution for low power low data-rate applications. Integrated transceiver based on UWB-FM radio will show advantages in circuit complexity, power consumption and general cost over traditional heterodyne or homodyne transceivers. Also the UWB-FM scheme spreads power into a spectrum shape, which fits the energy emission mask better than the traditional pulse UWB radio.

The traditional 3.1-10.6GHz UWB frequency band has been cut in the middle by WIMAX application into two parts: known as low band and high band. Yet the low band is surrounded by a lot of strong interferences and facing potential applications in the future. As our goal aims at having a commercial prototype, we choose the high band from 7.2GHz to 7.7GHz as our application frequency.

A transceiver architecture diagram for UWB-FM radio is in Fig.4. The input signal from baseband is firstly converted into triangle wave before being used to drive a RF VCO directly to generate the UWB-FM signal. In the receiver path, the received RF signal is first amplified by a LNA, and then demodulated into baseband FSK signal by a UWB-FM demodulator before entering baseband-processing circuitry.

The aim of having a maximum functioning distance of 10 meters for the receivers has imposed a sensitivity target around -8OdBm for the front-end. The key block to a relatively high sensitivity is the demodulator and an old implementation in 2005 showed an unsatisfying sensitivity performance.

Usually, the Low Noise Amplifier (LNA) is used to minimize influence of the noise from mixer and baseband circuitry to enhance the receiver's sensitivity performance. In our case, high voltage gain is also required to ease the circuit operation of the demodulator. Additionally, to ease the input interface to standard antenna and duplex and also to enhance immunity to environment noise after LNA, a single-ended in, differential out interface has been specified. The target power consumption has been defined as 4mW under 1.8V supply voltage.

For a proper FM demodulation, generally we first convert FM into AM or PM and then use a multiplier to demodulate the PM or AM signal to retrieve the original FM information. The most classical and promising multiplier is Gilbert Multiplier as shown in Fig. 1, which is the most important circuitry in present RF designs. The disadvantage of using it as a multiplier at RF region is that, it has a high output noise lever which originates from the 4 transistors of its "mixing" stage which I stated in figure 1. The noise here is approximately proportional to the bias current flowing through these transistors, while these bias currents will also flow into the bottom "Gm" stage which determines the gain and linearity. This is usually the disadvantage compared to mixers in conventional RF front end circuitry. That's why we usually prefer to use a mixer instead of a multiplier in conventional RF front end circuitry. In our case, we need the multiplier to stay away from the switching state in order to remain the multi-access capability of the demodulation. So the large noise at the Gilbert output or a large equivalent NF will limit our system's sensitivity, especially under a low power nature in Spec. Also in a FM demodulation process, we need to convert the FM signal to PM signal by means of group delay and an odd 90 degree phase shift at the RF carrier frequency. That means we have to implement some delay blocks in one of the paths to the multiplier. The old designs are not applicable because of their noise performance.

SUMMARY OF THE INVENTION

Hence, it is a need, to improve the demodulator for providing a low noise performance, which is necessary in UWB applications.

It is therefore an object of the invention to provide a low noise UWB demodulator.

The invention is defined by the independent claims. Dependent claims define advantageous embodiments.

It is provided a Ultra Wide Band signal demodulator comprising: a phase shifter (Phase) circuit for phase shifting an input signal (Vin) and for delivering a phase shifted signal to an amplifying circuit (Gain) for amplifying the phase shifted signal and for generating an amplified signal (VDO); a multiplier (Multiplier) for mixing the input signal with the amplified signal.

In an embodiment, the multiplier (Multiplier) is a Gilbert cell.

Preferably, the input signal is a differential signal comprising an in phase component and a inverse component i.e. phase shifted with 180 degrees with respect the in phase signal. The phase shifter comprises an all pass filter implemented as a cross-coupled LC circuit.

In another embodiment the multiplier comprises a supply loop, which is controlled by a signal for optimizing the noise performance of the demodulator.

Preferably, the phase shifter circuit, the amplifying circuit and the multiplier comprise transconductance amplifiers for compensating input capacitances of said phase shifter and amplifying circuit.

In particular, the multiplier comprises a lower stage coupled to an upper circuit, said circuit being supplied from different power sources.

In an embodiment, the demodulator is used in a receiver and/or in a transceiver.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages will be apparent from the exemplary description of the accompanying drawings in which

Fig. 1 depicts a prior art Gilbert multiplier;

Fig. 2 depicts a receiver comprising a UWB demodulator;

Fig. 3 depicts a UWB demodulator according to the invention; and

Fig. 4 depicts a UWB transceiver.

DETAILED DESCRIPTION OF EMBODIMENTS

The UWB-FM demodulator is designed to demodulate the second frequency modulation formally performed at the RF VCO of the transmitter shown in Fig.4. After considering the high sensitivity requirement, multi-access capability, low power low cost specifications of the project, we choose the fixed-time-delay (FTD) based FM demodulation scheme. In this scheme a group time delay is applied to the input signal s(t) to get a delayed version s(t-τ). This delay should have a 90 degree phase shift at central RF carrier frequency. Then the original signal s(t) is multiplied with s(t-τ) to get the final demodulated result. If we consider φ(t) as the modulated information, K as the multiplication gain, A for the signal amplitude and Wc as carrier frequency, we can derive:

S(t) = ACos(w_ct+φ(t)) S(t-τ) = ACos(w_c(t-τ)+φ(t-τ))

= KA²Co_S(w_cτ +φ(t)-φ(t-τ))

As we have fixed the system level scheme, we can draw the diagram for the front-end shown in Fig.5 with an LNA inserted before the demodulator. Now we can derive the sensitivity and dynamic range of the front-end as below. Here a balanced Gilbert multiplier is used for the multiplication and the maximum input signal power is limited by the limited input rage of the analog Gilbert multiplier other than the common nonlinearity induced inter-modulation components. Here R is the impedance level between antenna and front-end, AV_LNA is the voltage gain of LNA, NFLNA is the noise figure of LNA, SNRS_UB is the SNR needed at baseband input for proper FSK demodulation, B_SUB is the baseband signal bandwidth, Today is the delay in the delay path, A_Deiay is the voltage gain in the delay path, SNGiibert is the output noise voltage power spectrum density of the demodulator and K is the multiplication gain of the Gilbert cell.

_DR _ P_RFmMιa _ 3F_r K(τ_Delay)

P_ms«→ A_Dday JSNR_SUBB_SUBSN_Nom

Then maximum input power is limited by the input range of the balanced Gilbert multiplier, which is 3V_T for our case. For the sensitivity, we can see when noise from Gilbert cell is dominating, which is the case for the old design, increasing voltage gain of LNA or delay path, increasing delay and minimizing noise contributed from Gilbert cell are effective methods to improve sensitivity performance. But then the noise from LNA could not be neglected any more. The DR expression neglects the noise contributed from LNA. If we consider the dynamic range (DR) as a design parameter where the voltage gain AVoeiay in the delay path turns out to be a negative factor, only minimizing noise from Gilbert cell and increasing group delay within certain limitation will remain effective methods. Now if we include the noise from LNA for the DR only makes it more sensitive to AVoday-

The circuit design of the demodulator has been divided into two parts: group time delay and balanced Gilbert multiplier optimization for better noise performance. The group delay path is implemented by a cross-coupled LC filter named all pass filter (APF). This filter determines a 90 degree phase shift between input current and output voltage with certain group time delay at certain RF frequency. The total demodulator circuit schematic is shown in Fig.3. The biasing circuitry is not shown here. A CMFB loop is used to control the bias current flowing in the switching quad consisting Q13-Q16.

Transistors Q1-Q2 act as transconductance stage for APF and Q3-Q4 are used to compensate miller effect of Q1-Q2. An additional gain stage consisting of a transconductance stage Q5-Q6 and loading LC tank is inserted after the APF stage to increase the group delay and voltage gain of delay path. Thus the phase shift and group delay/voltage gain realization for the delay pass have been orthogonalized into APF stage and gain stage. The noise at the output of a balanced Gilbert cell is dominated by the noise originated from the switching quad Q13-Q16, among which the collector shot noise 2qlc accounts for the most. With balanced operation, noise contributed from one multiple pass into the Gilbert cell will be balanced out mostly while the noise from the switching quad remains.

Noise simulations results from QPSS and QPnoise have shown noise from switching quad accounts for 93% of the total output noise. Here we use a bias recycling technique to set different bias current for the switching quad and bottom transconductance stage. The recycling is implemented by a shunt LC tank conducting the bias current from APF and Gain stages into the transconductance stage which determines the multiplication gain K. As the bias current in the switching quad drops, the noise decreases. So we finally improve the output SNR. The transistor size of switching quad is chosen based on tradeoffs between noise, gain degeneration from base and emitter resistance and influence on fj.

For proper single demodulator measurement, the input of the demodulator has been terminated by a shunt resistor with consideration of package parasitic.

It is remarked that the scope of protection of the invention is not restricted to the embodiments described herein. Neither is the scope of protection of the invention restricted by the reference numerals in the claims. The word "comprising" does not exclude other parts than those mentioned in the claims. The word "a(n)" preceding an element does not exclude a plurality of those elements. Means forming part of the invention may both be implemented in the form of dedicated hardware or in the form of a programmed purpose processor. The invention resides in each new feature or combination of features.

Claims

CLAIMS:

1. A Ultra Wide Band signal demodulator comprising: a phase shifter (Phase) circuit for phase shifting an input signal (Vin) and for delivering a phase shifted signal to an amplifying circuit (Gain) for amplifying the phase shifted signal and for generating an amplified signal (VDO); a multiplier (Multiplier) for mixing the input signal with the amplified signal.

2. A Ultra Wide Band signal demodulator as claimed in claim 1, wherein the multiplier (Multiplier) is a Gilbert cell.

3. A Ultra Wide Band signal demodulator as claimed in any of the previous claims wherein the input signal is a differential signal comprising an in phase component (Vin+) and a inverse component (Vin-).

4. A Ultra Wide Band signal demodulator as claimed in previous claims, wherein the phase shifter (Phase) comprises an all pass filter implemented as a cross- coupled LC circuit.

5. A Ultra Wide Band signal demodulator as claimed in any of the previous claims, wherein the multiplier (Multiplier) comprises a supply loop (SL), which is controlled by a signal (CMFB) for optimizing the noise performance of the demodulator.

6. A Ultra Wide Band signal demodulator as claimed in any of the previous claims, wherein the phase shifter circuit (Phase), the amplifying circuit (Gain) and the multiplier (Multiplier) comprise transconductance amplifiers (Q3, Q4; Q7, Q8; QI l, Q12) for compensating input capacitances of said phase shifter and amplifying circuit.

7. A Ultra Wide Band signal demodulator as claimed in any of the previous claims, wherein the multiplier(Multiplier) comprises a lower stage (Q9, QlO, Ql 1, Q 12) coupled to an upper circuit (Q 13, Q 14, Q 15, Q 16), said circuit being supllied from different power sources.

8. A Ultra Wide Band receiver comprising a Ultra Wide Band signal demodulator as claimed in any of the previous claims.

9. A Ultra Wide Band transceiver comprising a Ultra Wide Band signal demodulator as claimed in any of the previous claims.