WO2009110537A1

WO2009110537A1 - Mram mixed system

Info

Publication number: WO2009110537A1
Application number: PCT/JP2009/054137
Authority: WO
Inventors: 俊輔深見; 延行石綿; 哲広鈴木; 則和大嶋; 聖万永原
Original assignee: 日本電気株式会社
Priority date: 2008-03-07
Filing date: 2009-03-05
Publication date: 2009-09-11
Also published as: JPWO2009110537A1; JP5488833B2

Abstract

A semiconductor device comprises a first magnetic random access memory having a first memory cell (9) and a second magnetic random access memory provided in the same chip as the first magnetic random access memory and having a second memory cell (8) operating at a higher speed than that of the first memory cell (9). The first memory cell (9) constitutes a spin-polarized current write type MRAM. Spin-polarized current is injected into a ferromagnetic conductor of a magnetoresistive effect element and a direct interaction between the spin of a conduction electron contributing to the current and the magnetic moment of the conductor causes a magnetization reversal, based on which data is stored. Write current flows through at least a magnetic free layer. The second memory cell (8) constitutes a current-induced magnetic field write type MRAM. Data is stored based on the magnetic field induced by a write current.

Description

[Name of invention determined by ISA based on Rule 37.2] MRAM mixed loading system

The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a magnetoresistive effect element for a memory cell.

Magnetic Random Access Memory (Magnetic Random Access Memory; MRAM) is expected to be a non-volatile memory capable of high-speed operation and infinite rewriting, and has been actively developed. In the MRAM, a magnetoresistive effect element is integrated in a memory cell, and data is stored as the magnetization direction of the ferromagnetic layer of the magnetoresistive effect element. Several types of MRAMs have been proposed corresponding to the method of switching the magnetization of the ferromagnetic layer.

The most common MRAM is a current-induced magnetic field writing type MRAM. In this MRAM, wiring for passing a write current is arranged around the magnetoresistive effect element, and the magnetization direction of the ferromagnetic layer of the magnetoresistive effect element is switched by a current magnetic field generated by passing the write current. In principle, this MRAM can be written in 1 nanosecond or less, and is suitable as a high-speed MRAM. For example, there has been a report of successful operation verification at 250 MHz (N. Sakimura et al., “A 250-MHz 1-Mbit Embedded MRAM Macro Usage 2T1MTJ Cell Bitline Separation and Half-ShipCritichi” Conference, 2007. ASSCC '07. IEEE Asian. P. 216.). Furthermore, a circuit configuration suitable for operation at 500 MHz has also been proposed (N. Sakimura et al., “MRAM Cell Technology for Over 500-MHz SoC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 42. pp. 830.).

However, the magnetic field for switching the magnetization of the magnetic material in which the thermal stability and the disturbance magnetic field resistance are ensured is generally about several tens [Oe]. In order to generate such a magnetic field, a large write current of about several mA is required. Even the lowest reported write current is about 1 mA (H. Honjo et al., “Performance of write-line-inserted MTJ for low-write-current MRAM cell”, 52nd MagnetismensMet 2007 (MMM 2007), p. 481.). When the write current is large, the chip area is inevitably increased, and the power consumption required for writing increases. In addition to this, when the memory cell is miniaturized, the write current further increases and does not scale.

As another MRAM, there is a spin polarized current writing type MRAM. In this MRAM, a spin-polarized current is injected into the ferromagnetic conductor of the magnetoresistive element, and the magnetization is caused by a direct interaction between the spin of the conduction electron carrying the current and the magnetic moment of the conductor. (Hereinafter referred to as “Spin Transfer Magnetization Switching”). The presence or absence of spin injection magnetization reversal depends on the current density (not the absolute value of the current). Accordingly, when spin injection magnetization reversal is used for data writing, the write current is reduced if the size of the memory cell is reduced. That is, the spin injection magnetization reversal method is excellent in scaling. When the write current is small, the chip area is small, and high integration and large scale are possible. However, the writing time tends to be longer than that of the current-induced magnetic field writing type MRAM (example: 1 nsec. Or more).

In a semiconductor device (hereinafter also referred to as a “memory-embedded semiconductor device”) such as a system LSI (Large-Scale Integration) equipped with logic and memory, an area that requires high-speed operation, large capacity and high integration ( That is, there are areas that require a low write current, and a memory is provided in each area. For example, a register or cache is provided as a memory in an area requiring high-speed operation, and a main storage device or an auxiliary storage device is provided as a memory in an area requiring large capacity and high integration. Since the performance and functions required for each memory are different from each other, one type of memory cannot be used. Therefore, at least one of a plurality of types of memory (FF (Flip-Flop), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), flash memory, etc.) has been operated at high speed so far. At least one of the other required areas was used for a large capacity / highly integrated area. However, in this case, the number of processes increases because the materials and processes used in each memory are different from each other. As a result, problems such as an increase in manufacturing cost, a prolonged manufacturing period, and a decrease in manufacturing yield may occur.

Therefore, an object of the present invention is to provide a memory-embedded semiconductor device capable of achieving both high-speed processing and large-capacity processing in an internal memory.

The semiconductor device of the present invention has a first magnetic random access memory having a first memory cell and a second memory cell that operates at a higher speed than the first memory cell, and is the same as the first magnetic random access memory. And a second magnetic random access memory provided in the chip. The first memory cell includes a first magnetization fixed layer whose magnetization direction is fixed, a first magnetization free layer whose magnetization direction can be reversed, a first magnetization fixed layer, and a first magnetization free layer sandwiched between the first magnetization fixed layer and the first magnetization free layer. A nonmagnetic layer. The first magnetization free layer and the first magnetization fixed layer are made of a ferromagnetic material. A write current flows through at least the first magnetization free layer. The second memory cell includes a second magnetization free layer, a second magnetization fixed layer, and a second nonmagnetic layer provided between the second magnetization free layer and the second magnetization fixed layer. The write current does not flow through the second magnetization free layer. The second magnetization free layer and the second magnetization fixed layer are made of a ferromagnetic material.

FIG. 1 is a schematic diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2A is a schematic diagram illustrating a configuration of a current-induced domain wall motion type magnetoresistive effect element according to an embodiment of the present invention. FIG. 2B is a schematic diagram illustrating a configuration of a current-induced domain wall motion type magnetoresistive effect element according to an embodiment of the present invention. FIG. 2C is a schematic diagram illustrating a configuration of a current-induced domain wall motion type magnetoresistive effect element according to an embodiment of the present invention. FIG. 2D is a schematic diagram illustrating a configuration of a current-induced domain wall motion type magnetoresistive effect element according to an embodiment of the present invention. FIG. 3A is a schematic diagram showing a configuration of a spin-injection magnetization reversal type magnetoresistive effect element according to an example of the present invention. FIG. 3B is a schematic diagram showing a configuration of a spin-injection magnetization reversal type magnetoresistive effect element according to an example of the present invention. FIG. 4A is a schematic diagram showing a configuration of a current-induced magnetic field writing type magnetoresistive effect element according to an example of the present invention. FIG. 4B is a schematic diagram showing a configuration of a current-induced magnetic field writing type magnetoresistive effect element according to the example of the present invention. FIG. 4C is a schematic diagram showing a configuration of a current-induced magnetic field writing type magnetoresistive effect element according to the example of the present invention. FIG. 5A is a circuit diagram showing a configuration example of a memory cell in which the magnetoresistive effect element of this embodiment is integrated. FIG. 5B is a block diagram illustrating a configuration example of an MRAM in which the memory cells of this embodiment are integrated. FIG. 6 is a circuit diagram showing another configuration example of the memory cell in which the magnetoresistive effect element of this embodiment is integrated. FIG. 7A is a perspective view showing a configuration of a first modification of the magnetoresistive element in each MRAM according to the embodiment of the present invention. FIG. 7B is a plan view showing a configuration of a first modification of the magnetoresistive effect element in each MRAM according to the embodiment of the present invention. FIG. 7C is a plan view showing a configuration of a first modification of the magnetoresistive element in each MRAM according to the embodiment of the present invention. FIG. 7D is a plan view showing a configuration of a first modification of the magnetoresistive element in each MRAM according to the embodiment of the present invention. FIG. 8 is a perspective view showing a configuration of a second modification of the magnetoresistive effect element in each MRAM according to the embodiment of the present invention. FIG. 9 is a perspective view showing a configuration of a third modification of the magnetoresistive element in each MRAM according to the embodiment of the present invention. FIG. 10 is a perspective view showing a configuration of a fourth modification of the magnetoresistive effect element in each MRAM according to the embodiment of the present invention. FIG. 11A is a perspective view schematically showing the configuration of the fifth modification example of the magnetoresistance effect element according to the present example. FIG. 11B is a plan view schematically showing the configuration of the fifth modification example of the magnetoresistance effect element according to the present example. FIG. 11C is a plan view schematically showing the configuration of the fifth modification example of the magnetoresistance effect element according to the present example. FIG. 12A is a circuit diagram showing a configuration example of a memory cell in which a fifth modification of the magnetoresistive effect element of this embodiment is integrated. FIG. 12B is a circuit diagram showing another configuration example of the memory cell in which the fifth modification example of the magnetoresistive effect element of this embodiment is integrated.

Hereinafter, embodiments of the semiconductor device of the present invention will be described. FIG. 1 is a schematic diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. The semiconductor device 1 of the present embodiment is a memory-embedded semiconductor device. The semiconductor device 1 is exemplified by a memory-embedded LSI formed on one chip, and includes a logic unit 2 and a memory unit 3.

The logic unit 2 is an area that requires high-speed operation, and has a logic circuit that performs a logical operation. The logic unit 2 further includes MRAMs 4-1 to 4-4 capable of high speed operation. The MRAMs 4-1 to 4-4 are exemplified as current-induced magnetic field writing type MRAMs, and are used as registers, L1 caches (primary caches), and L2 caches (secondary caches). Hereinafter, when it is not necessary to distinguish between them, they are simply abbreviated as MRAM4.

The current-induced magnetic field writing type MRAM is theoretically 1 nsec. The following writing is possible, and it is suitable as an MRAM capable of high-speed operation (the operation frequency is desirably 200 MHz or more). In general, since the write current is large, the area of the present MRAM is relatively large. However, since the memory is used as a memory having a relatively small capacity such as a register, an L1 cache, or an L2 cache, the area of the entire chip. The impact on is very small.

The memory unit 3 is an area that requires large capacity and high integration (that is, low write current), and has a memory circuit for storing data. As the storage circuit, large-capacity and highly integrated MRAMs 5-1 to 5-3 are included. The MRAMs 5-1 to 5-3 are exemplified as spin-polarized current writing type MRAMs, and are used as a main storage device or an auxiliary storage device. Hereinafter, when it is not necessary to distinguish between them, they are simply abbreviated as MRAM5.

The spin-polarized current writing type MRAM (the writing current is preferably 0.5 mA or less) is exemplified by a current-induced domain wall motion type MRAM and a spin injection magnetization switching type MRAM.
In the spin injection magnetization reversal type MRAM, the magnetoresistive effect element includes a first ferromagnetic layer having a reversible magnetization (often referred to as a magnetization free layer) and a second ferromagnetic layer having a fixed magnetization ( (Often referred to as a magnetization fixed layer) and a tunnel body provided with a tunnel barrier layer provided between these ferromagnetic layers. Such MRAM data writing utilizes the interaction between spin-polarized conduction electrons and localized electrons in the magnetization free layer when a current is passed between the magnetization free layer and the magnetization fixed layer. The magnetization of the magnetization free layer is reversed. In this case, the magnetoresistive effect element is a two-terminal element having a terminal connected to the magnetization free layer and a terminal connected to the magnetization fixed layer. Therefore, this MRAM is effective for reducing the area.

In a current-induced domain wall motion type MRAM, the magnetoresistive effect element generally includes a first ferromagnetic layer that holds data (often referred to as a magnetic recording layer) and a second strong layer in which magnetization is fixed. A magnetic layer (often referred to as a magnetization fixed layer) and a laminated body including a tunnel barrier layer provided between these ferromagnetic layers. The magnetic recording layer has a magnetization reversal portion having reversible magnetization and two magnetization fixed portions having fixed magnetization connected to both ends thereof. The data is stored as the magnetization of the magnetization switching unit. The magnetizations of the two magnetization fixed portions are fixed so as to be substantially antiparallel to each other. When the magnetization is arranged in this way, a domain wall is introduced into the magnetic recording layer. When a current is passed in the direction penetrating the domain wall, the domain wall moves in the direction of spin-polarized conduction electrons (Domain Wall Motion), so that data can be written by passing a current through the magnetic recording layer. In this case, the magnetoresistive element is a three-terminal element having two terminals connected to both ends of the magnetic recording layer and a terminal connected to the magnetization fixed layer. This MRAM has improved durability, life, and reliability because the write current does not pass through the tunnel barrier layer.

Regarding the reduction of the write current, for example, there is a report demonstrating the write at 0.2 mA in the spin injection magnetization reversal type MRAM (T. Kawahara et al., “2 Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by -Bit Bidirectional Current Write and Parallelizing-Direction Current Read ", Solid-State Circuits Confence, 2007. ISSCC 2007. DigestEnt. However, it has been reported that the write current increases rapidly in the nanosecond region in principle (T. Aoki et al., “Spin transfer switching in nano second switching speed region for MgO based ferromechanical 31”. Conference on MAGNETICS in Japan (2007), The Magnetics Society of Japan.p.340.). In addition, there is a report that a type having perpendicular magnetic anisotropy is more advantageous than a type having in-plane magnetic anisotropy for reducing current (M. Nakayama et al., “TbCoFe / CoFeB”). / MgO / CoFeB / TbCoFe magnetotunative tunneling junctions with perpendental magnetic anisotropy ", 52nd Magnetism and MagneticMen.M200.

In addition, for example, there is a report showing that a domain wall motion at 0.05 mA is possible in a current-induced domain wall motion type MRAM (S. Fukami et al., “Micromagnetic analysis of current dominant wall motion in-mannan- strips with perpendicular magnetic anisotropy. ", 52nd Magnetism and Magnetic Materials Conference 2007 (MMM 2007) .p.352.). In addition, the domain wall moving speed is proportional to the current density, and is reported to be about 100 m / s at the maximum (M. Hayashi et al., “Current Driven Domains, World Velocities, Exceeding The Spin Annular Momentum” (Physical Review Letters, vol. 98, p. 037204 (2007).). In this case, the movement of 100 nm takes 1 ns.

The current-induced domain wall motion type MRAM and the spin-injection magnetization reversal type MRAM have excellent scaling properties as described above, and are suitable as MRAMs capable of high integration and large scale. In addition, although the operation speed is relatively low, the influence is extremely small because it is used as a memory that does not require high-speed operation as compared with a register such as a main storage device or an auxiliary storage device.

In the semiconductor device 1, when all of the storage elements of the logic unit 2 and the memory unit 3 are nonvolatile memory MRAMs, it is preferable that data can be retained in the MRAMs even when the power is turned off. In that case, power off can be set to the basic state (instant on). Thereby, power consumption can be reduced.

Furthermore, in the semiconductor device 1, when the memory elements of the logic unit 2 and the memory unit 3 are nonvolatile memory MRAMs, the memory elements can be manufactured in the same process as described later, which is preferable. Thus, by manufacturing different types of MRAMs in the same process, the semiconductor device 1 can be manufactured at a low cost and in a short time.

Note that the semiconductor device of the present invention is not limited to the configuration illustrated in FIG. That is, the number, shape, arrangement, etc. of the MRAM in each part, such as the shape and arrangement of the logic part 2 and the memory part 3, can be freely modified within the scope of the technical idea of the present invention.

Next, the magnetoresistive effect element used in the spin polarized current writing type MRAM 5 will be described in detail. First, a current-induced domain wall motion type magnetoresistive effect element will be described. 2A to 2D are schematic views showing the configuration of a current-induced domain wall motion type magnetoresistive effect element according to an embodiment of the present invention. 2A and 2B show a configuration in which the magnetization free layer in which the domain wall moves linearly extends, and FIGS. 2C and 2D show a configuration in which the magnetization free layer has a substantially U-shape.

As shown in FIGS. 2A and 2B, the current-induced domain wall motion type magnetoresistive effect element is provided between the magnetization free layer 10, the magnetization fixed layer 30, and the magnetization free layer 10 and the magnetization fixed layer 30. A nonmagnetic layer 20 is provided. The magnetization free layer 10 is connected to the first magnetization fixed region 11a in which the magnetization is fixed, the second magnetization fixed region 11b in which the magnetization is fixed, and the first magnetization fixed region 11a and the second magnetization fixed region 11b. Includes a reversible magnetization free region 12. The magnetization free region 12 overlaps with the magnetization fixed layer 30. The magnetizations of the first magnetization fixed region 11a and the second magnetization fixed region 11b may be fixed by a magnetization fixed layer (not shown) provided above or below the first magnetization fixed region 11a and the second magnetization fixed region 11b. The first magnetization fixed region 11 a and the second magnetization fixed region 11 b are formed so as to extend substantially linearly together with the magnetization fixed region 12, and their magnetization directions are fixed in opposite directions with respect to the magnetization fixed region 12. ing. In the illustrated example, the magnetization direction of the first magnetization fixed region 11a is the + x direction, and the magnetization direction of the second magnetization fixed region 11b is the -x direction. On the other hand, the magnetization free region 12 has reversible magnetization as described above. Therefore, the domain wall is formed at the boundary between the first magnetization fixed region 11 a and the magnetization free region 12 or at the boundary between the second magnetization fixed region 11 b and the magnetization free region 12.

The current-induced domain wall motion type magnetoresistive effect element shown in FIGS. 2C and 2D is basically the same as the current-induced domain wall motion type magnetoresistive effect element shown in FIGS. 2A and 2B. However, the difference is that the magnetization free layer 10 has a substantially U-shaped shape. Specifically, the magnetization free layer 10 includes a first magnetization fixed region 11a in which magnetization is fixed, a second magnetization fixed region 11b in which magnetization is fixed, a first magnetization fixed region 11a, and a second magnetization fixed region 11b. And a magnetization free region 12 that can be reversed in magnetization. The magnetization free region 12 overlaps with the magnetization fixed layer 30. The magnetizations of the first magnetization fixed region 11a and the second magnetization fixed region 11b may be fixed by a magnetization fixed layer (not shown) provided above or below the first magnetization fixed region 11a and the second magnetization fixed region 11b. The first magnetization fixed region 11a and the second magnetization fixed region 11b are formed so as to extend at substantially right angles (y direction) with respect to the magnetization fixed region 12 (extend in the x direction). It is fixed in the same direction (+ y direction) with respect to the fixed region 12. On the other hand, the magnetization free region 12 has reversible magnetization as described above. Therefore, the domain wall is formed at the boundary B1 between the first magnetization fixed region 11a and the magnetization free region 12, or at the boundary B2 between the second magnetization fixed region 11b and the magnetization free region 12.

The magnetization free layer 10 and the magnetization fixed layer 30 are made of a ferromagnetic material. In the case of FIG. 2A and FIG. 2C, the magnetization free layer 10 and the magnetization fixed layer 30 are in-plane magnetization films having in-plane magnetic anisotropy. That is, the magnetization free layer 10 and the magnetization fixed layer 30 have magnetic anisotropy in the in-plane direction. 2A and 2C show the in-plane magnetic anisotropy in the horizontal direction (direction from one of the first magnetization fixed region 11a and the second magnetization fixed region 11b to the other) in the figure as the magnetization direction of each layer. Has been. However, it may have another in-plane direction substantially perpendicular to this direction. On the other hand, in the case of FIG. 2B and FIG. 2D, the magnetization free layer 10 and the magnetization fixed layer 30 are a perpendicular magnetization film having a perpendicular magnetic anisotropy (perpendicular magnetic anisotropy). That is, the magnetization free layer 10 and the magnetization fixed layer 30 have magnetic anisotropy in the film thickness direction. 2A, 2B, 2C, and 2D, a magnetic tunnel junction (MTJ) is formed by the magnetization free layer 10, the nonmagnetic layer 20, and the magnetization fixed layer 30.

The following are examples of materials for each layer. Note that all the materials shown here are examples, and any material may be used in practice as long as the above-described magnetization state can be realized.

First, it is desirable that the magnetization free layer 10 includes at least one material selected from Fe, Co, and Ni. Furthermore, perpendicular magnetic anisotropy can be stabilized by including Pt and Pd. In addition to this, B, C, N, O, Al, Si, P, Ti, V, Cr, Mn, Cu, Zn, Zr, Nb, Mo, Tc, Ru, Rh, Ag, Hf, Ta, W , Re, Os, Ir, Au, Sm, and the like can be added so that desired magnetic properties are expressed. Specifically, Co, Co—Pt, Co—Pd, Co—Cr, Co—Pt—Cr, Co—Cr—Ta, Co—Cr—B, Co—Cr—Pt—B, Co—Cr—Ta— B, Co-V, Co-Mo, Co-W, Co-Ti, Co-Ru, Co-Rh, Fe-Pt, Fe-Pd, Fe-Co-Pt, Fe-Co-Pd, Sm-Co, Examples thereof include Gd—Fe—Co, Tb—Fe—Co, and Gd—Tb—Fe—Co. In addition, the magnetic anisotropy in the perpendicular direction can also be exhibited by laminating a layer containing any one material selected from Fe, Co, and Ni with different layers. Specifically, a laminated film of Co / Pd, Co / Pt, Co / Ni, Fe / Au, and the like are exemplified.

The nonmagnetic layer 20 is preferably made of an insulator. Specific examples of suitable materials for the nonmagnetic layer 20 include Mg—O, Al—O, Al—N, Ni—O, and Hf—O. However, the present invention can also be implemented by using a semiconductor or a metal material as the nonmagnetic layer 20. Specifically, examples of materials that can be used for the nonmagnetic layer 20 include Cr, Al, Cu, and Zn.

It should be noted that it is preferable to select materials for the magnetization free layer 10, the nonmagnetic layer 20, and the magnetization fixed layer 30 that have a large magnetoresistance effect ratio corresponding to the SN ratio of the read signal. For example, in a Co—Fe—B / Mg—O / Co—Fe—B MTJ, a very large magnetoresistance effect ratio of 500% has been reported in recent years. From this viewpoint, it is desirable that the magnetization free layer 10 and the magnetization fixed layer 30 are made of a Co—Fe—B material, and the nonmagnetic layer 2 is made of an Mg—O material.

As described above, the magnetization direction of each layer of the current-induced domain wall motion type magnetoresistive effect element is arbitrary. However, when it is desired to reduce the write current, it is preferable to use the magnetoresistive effect element having the perpendicular magnetic anisotropy in the case of FIGS. 2B and 2D. On the other hand, when it is desired to obtain a high MR ratio, it is preferable to use the magnetoresistive effect element shown in FIGS. 2A and 2C having in-plane magnetic anisotropy.

Next, an operation method of the current-induced domain wall motion type magnetoresistive effect element, specifically, a writing method and a reading method will be described.

First, the data writing method will be described. Data writing to the current-induced domain wall motion type magnetoresistance effect element is performed by moving the domain wall formed in the magnetization free layer 10. As described above, the magnetization free layer 10 includes the first magnetization fixed region 11a and the second magnetization fixed region 11b whose magnetizations are fixed substantially antiparallel to each other, and the magnetization free region 12 electrically connected thereto. The magnetization of the magnetization free region 12 is substantially parallel to either the first magnetization fixed region 11a or the second magnetization fixed region 11b. Due to the restriction of the magnetization state, a domain wall is introduced into the first magnetization free layer 10. For example, when the magnetization of the magnetization free region 12 is substantially parallel to the magnetization of the first magnetization fixed region 11a and is substantially antiparallel to the magnetization of the second magnetization fixed region 11b, the magnetization free region 12 and the second magnetization fixed region A domain wall is formed near the boundary of 11b. In addition, when the magnetization of the magnetization free region 12 is substantially parallel to the magnetization of the second magnetization fixed region 11b and is substantially antiparallel to the magnetization of the first magnetization fixed region 11a, the magnetization free region 12 and the first magnetization fixed region A domain wall is formed near the boundary of 11a.

The position of the formed domain wall can be moved by passing a current directly through the first magnetization free layer 10. For example, when a domain wall is formed in the vicinity of the boundary between the magnetization free region 12 and the first magnetization fixed region 11a, the first magnetization fixed is obtained by flowing a current in a direction from the magnetization free region 12 toward the first magnetization fixed region 11a. Conduction electrons flow from the region 11a to the magnetization free region 12, and the domain wall moves in the same direction as the flow of the conduction electrons. Due to the movement of the domain wall, the magnetization of the magnetization free region 12 becomes parallel to the first magnetization fixed region 11a. When a domain wall is formed in the vicinity of the boundary between the magnetization free region 12 and the second magnetization fixed region 11b, the second magnetization fixed is obtained by flowing a current in a direction from the magnetization free region 12 toward the second magnetization fixed region 11b. Conduction electrons flow from the region 11b to the magnetization free region 12, and the domain wall moves in the same direction as the flow of the conduction electrons. Due to the movement of the domain wall, the magnetization of the magnetization free region 12 becomes parallel to the second magnetization fixed region 11b. In this way, information can be rewritten between the “0” state and the “1” state. *

In this way, “1” write from the “0” state and “0” write from the “1” state are realized. Although not shown, “0” writing from the “0” state and “1” writing from the “1” state, that is, overwriting is also possible.

Actually, in order to introduce the write current as described above, it is desirable that the first magnetization fixed region 11a and the second magnetization fixed region 11b be provided with terminals connected to external wiring. At this time, the write current flows between the first terminal connected to the first magnetization fixed region 11a and the second terminal connected to the second magnetization fixed region 11b. However, the path of the write current for writing data to the magnetoresistive effect element of this embodiment is not limited to this.

Next, a method for reading data will be described. The magnetoresistive effect is used to read data from the current-induced domain wall motion type magnetoresistive effect element. Specifically, a current is passed between the magnetization fixed layer 30 and the magnetization free region 12 of the magnetization free layer 10 via the nonmagnetic layer 20, so that the magnetization of the magnetization fixed layer 30 and the magnetization of the magnetization free region 12 are relative to each other. Data is read by detecting a change in resistance according to the angle. For example, when the domain wall is near the boundary between the magnetization free region 12 and the first magnetization fixed region 11a, the magnetization of the magnetization fixed layer 30 and the magnetization of the magnetization free region 12 are parallel (for example, “0” is stored). A low resistance state is realized. On the other hand, when the domain wall is in the vicinity of the boundary between the magnetization free region 12 and the second magnetization fixed region 11b, the magnetization of the magnetization fixed layer 30 and the magnetization of the magnetization free region 12 are antiparallel (for example, “1” is stored). A high resistance state is realized. A change in the resistance of the magnetoresistive effect element is detected as a voltage signal or a current signal, and data stored in the magnetoresistive effect element is determined using the voltage signal or the current signal.

The shape of each layer on the in-plane plane is not limited to the example shown in each figure, and may be a circle, an ellipse, a rectangle, a rhombus, or another polygon. In addition, irregularities can be appropriately provided on the surface of each layer so that appropriate characteristics can be obtained. Also, the area of each layer is arbitrary.

Next, a spin injection magnetization reversal type magnetoresistive effect element will be described. 3A to 3B are schematic views showing the configuration of a spin-injection magnetization reversal type magnetoresistive effect element according to an embodiment of the present invention.

As shown in FIGS. 3A and 3B, this spin-injection magnetization reversal type magnetoresistive effect element is provided between the magnetization free layer 10, the magnetization fixed layer 30, and the magnetization free layer 10 and the magnetization fixed layer 30. A nonmagnetic layer 20 is provided. The magnetization free layer 10 has reversible magnetization. The magnetization fixed layer 30 has a fixed magnetization.

The magnetization free layer 10 and the magnetization fixed layer 30 are made of a ferromagnetic material. In the case of FIG. 3A, the magnetization free layer 10 and the magnetization fixed layer 30 are in-plane magnetization films having in-plane magnetic anisotropy. That is, the magnetization free layer 10 and the magnetization fixed layer 30 have magnetic anisotropy in the in-plane direction. In FIG. 3A, in-plane magnetic anisotropy in the horizontal direction in the figure is shown as the magnetization direction of each layer. However, it may have another in-plane direction substantially perpendicular to this direction. On the other hand, in the case of FIG. 3B, the magnetization free layer 10 and the magnetization fixed layer 30 are perpendicular magnetization films having perpendicular magnetic anisotropy. That is, the magnetization free layer 10 and the magnetization fixed layer 30 have magnetic anisotropy in the film thickness direction. 3A and 3B, a magnetic tunnel junction (MTJ) is formed by the magnetization free layer 10, the nonmagnetic layer 20, and the magnetization fixed layer 30.

Hereinafter, the material of each layer is the same as in the case of the current-induced domain wall motion type magnetoresistive effect element as shown in FIGS. 2A to 2D.

As described above, the magnetization direction of each layer of the spin-injection magnetization reversal type magnetoresistive effect element is arbitrary. However, when it is desired to reduce the write current, it is preferable to use the magnetoresistive effect element in FIG. 3B having perpendicular magnetic anisotropy. On the other hand, in order to obtain a high MR ratio, it is generally preferable to use the magnetoresistive effect element in the case of FIG. 3A having in-plane magnetic anisotropy.

Next, an operation method of the spin-injection magnetization reversal type magnetoresistive effect element, specifically, a writing method and a reading method will be described.

First, the data writing method will be described. Data writing to the spin transfer magnetization reversal type magnetoresistive effect element is realized by a spin transfer magnetization reversal method. Specifically, a write current flows between the first magnetization fixed layer 10 and the first magnetization free layer 30. Here, the case where the magnetization of the magnetization free layer 10 and the magnetization direction of the magnetization fixed layer 30 are in an antiparallel state is referred to as a “1” state (a state in which data “1” is recorded) and is in a parallel state. The case is a “0” state (a state where data “0” is recorded).

When the write current flows from the magnetization fixed layer 30 to the magnetization free layer 10 through the nonmagnetic layer 20, conduction electrons flow from the magnetization free layer 10 to the magnetization fixed layer 30 through the nonmagnetic layer 20. For example, when the magnetization direction of the magnetization fixed layer 30 is fixed in the first direction, the conduction electrons having the spin angular momentum in the second direction opposite to the first direction are conduction electrons having the spin angular momentum in the first direction. Compared to electrons, the light is reflected more at the interface of the magnetization fixed layer 30. As a result, in the magnetization free layer 10, electrons having the spin angular momentum in the second direction become majority, and magnetization reversal in the second direction is induced. Since the magnetization of the magnetization free layer 10 is in the second direction and the magnetization direction of the magnetization fixed layer 30 is in the first direction, both magnetizations are in an antiparallel state. Therefore, a “1” state (a state in which data “1” is recorded) is written.

On the other hand, when the write current flows from the magnetization free layer 10 through the nonmagnetic layer 20 to the magnetization fixed layer 30, conduction electrons flow from the magnetization fixed layer 30 through the first nonmagnetic layer 20 to the magnetization free layer 10. For example, when the magnetization direction of the magnetization fixed layer 30 is fixed in the first direction, many conduction electrons having a spin angular momentum in the first direction flow into the magnetization free layer 10. As a result, in the magnetization free layer 10, electrons having a spin angular momentum in the first direction become majority, and magnetization reversal in the first direction is induced. Since the magnetization of the magnetization free layer 10 is the first direction and the magnetization direction of the magnetization fixed layer 30 is the first direction, both magnetizations are in a parallel state. Therefore, a “0” state (a state in which data “0” is recorded) is written.

By the above method, “0” writing and “1” writing are realized. At this time, not only “0” write from the “1” state and “1” write from the “0” state, but also “0” write from the “0” state and “1” write from the “1” state. Overwriting such as 1 "writing is also possible.

Next, a method for reading data will be described. The magnetoresistive effect is used for reading data from the spin injection magnetization reversal type magnetoresistive effect element. Specifically, this is the same as in the case of a current-induced domain wall motion type magnetoresistive effect element.

As described above, as the magnetoresistive effect element used in the MRAM 5, any of the spin-polarized current write type magnetoresistive effect elements shown in FIGS. 2A to 2D and FIGS. 3A to 3B can be used.

Next, a magnetoresistive effect element used in the current-induced magnetic field writing type MRAM 4 will be described. 4A to 4C are schematic diagrams showing the configuration of a current-induced magnetic field write type magnetoresistive effect element according to an embodiment of the present invention.

4A includes a magnetization free layer 210, a magnetization fixed layer 230, and a nonmagnetic layer 220 provided between the magnetization free layer 210 and the magnetization fixed layer 220. Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

The magnetization free layer 210 and the magnetization fixed layer 230 are made of a ferromagnetic material. The magnetization free layer 210 and the magnetization fixed layer 230 are in-plane magnetization films having in-plane magnetic anisotropy. That is, the magnetization free layer 210 and the magnetization fixed layer 230 have magnetic anisotropy in the in-plane direction (xy in-plane direction). In this embodiment, the nonmagnetic layer 220 is made of an insulator, and a magnetic tunnel junction (MTJ) is formed by the magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230. The nonmagnetic layer 220 is preferably made of an insulator, but may be made of a semiconductor or a conductor. Specific materials of the magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230 are the same as those of the magnetization free layer 10, the nonmagnetic layer 20, and the magnetization fixed layer 30 in the spin-polarized current write type magnetoresistive effect element. Things can be used.

The magnetization fixed layer 230 has a fixed magnetization. This fixed magnetization is set in a direction perpendicular to the longitudinal direction (x direction) of the magnetization fixed layer 230 or has a vertical component. On the other hand, the magnetization free layer 210 has reversible magnetization. The easy axis of magnetization of the magnetization free layer 210 is perpendicular to the longitudinal direction (x direction) of the magnetization fixed layer 230 or has a perpendicular component. Such magnetic anisotropy can be imparted by shape magnetic anisotropy.

When the fixed magnetization of the magnetization fixed layer 230 and the magnetization easy axis of the magnetization free layer 210 are as described above, the magnetization of the magnetization free layer 210 is either a parallel component or an antiparallel component with respect to the magnetization of the magnetization fixed layer 230. You can have either. In the magnetoresistive element of FIG. 4A, the magnetization direction of the magnetization free layer 210 corresponds to stored data.

Next, an operation method of the current-induced magnetic field writing type magnetoresistive effect element of FIG. 4A, specifically, a writing method and a reading method will be described.

Explain how to write data. First, a write current is passed through the magnetization fixed layer 230. The magnetization of the magnetization free layer 210 is reversed by a current-induced magnetic field generated by the write current. At that time, the direction of the current-induced magnetic field generated by the direction of the write current can be controlled to change the magnetization of the magnetization free layer 210 to a desired direction. Thereby, desired data is recorded in the magnetization free layer 210. The magnetization fixed layer 230 may be referred to as a base electrode because of its role. Such a writing method in which a writing current is supplied to the magnetization fixed layer 230, that is, the base electrode can also be referred to as a base writing type. In this method, since a write current is directly supplied to the magnetoresistive effect element, the magnitude of the current-induced magnetic field becomes relatively large. Therefore, the write current can be reduced. Moreover, since the magnetization fixed layer 230 introduces a write current, it is desirable that the electric resistance is relatively small. Therefore, the electrical resistance may be lowered by making a conductive layer adjacent to the magnetization fixed layer 230.

Next, a method for reading data will be described. First, a read current is passed between the magnetization fixed layer 230 and the magnetization free layer 210 via the nonmagnetic layer 220. Then, data is read by detecting a change in resistance according to the relative angle between the magnetization of the magnetization fixed layer 230 and the magnetization of the magnetization free layer 210. For example, when the magnetization of the magnetization fixed layer 230 and the magnetization of the magnetization free layer 210 are parallel (example: “0” is stored), a low resistance state is realized, and the magnetization of the magnetization fixed layer 230 and the magnetization of the magnetization free layer 210 are Are antiparallel (example: “1” is stored), a high resistance state is realized. A change in the resistance of the magnetoresistive effect element is detected as a voltage signal or a current signal, and data stored in the magnetoresistive effect element is determined using the voltage signal or the current signal.

4B is provided in the vicinity of the magnetization free layer 210, the magnetization fixed layer 230a, the nonmagnetic layer 220 provided between the magnetization free layer 210 and the magnetization fixed layer 230a, and the magnetization free layer 210. The conductive layer 250 is provided. Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

The magnetization free layer 210, the magnetization fixed layer 230a, and the nonmagnetic layer 220 in FIG. 4B are the same as the magnetization free layer 210, the magnetization fixed layer 230, and the nonmagnetic layer 220 in FIG. 4A. However, the magnetization pinned layer 230a is different from the magnetization pinned layer 230 of FIG. 4A in that no write current flows.

The conductive layer 250 is a wiring layer for writing data and is formed of a conductor. The direction of the magnetization of the magnetization free layer 210 is controlled by a current-induced magnetic field generated by a write current flowing inside the conductive layer 250. That is, data is written in the magnetoresistive effect element by the current-induced magnetic field. Since the write current is not supplied to the magnetization fixed layer (ferromagnetic material) but to the conductive layer 250 formed of a highly conductive conductor such as copper (Cu) or aluminum (Al), the write wiring resistance is further reduced. I can do it. The conductive layer 250 may be electrically connected to the magnetization fixed layer 230a (or the magnetization free layer if closer to the conductive layer 250) via a contact.
Other configurations are the same as those in the case of FIG.

Next, an operation method of the current-induced magnetic field writing type magnetoresistive effect element of FIG. 4B, specifically, a writing method and a reading method will be described.

Explain how to write data. First, a write current is passed from one end of the conductive layer 90 to the other end. The magnetization of the magnetization free layer 210 is reversed by a current-induced magnetic field generated by the write current. At that time, the direction of the current-induced magnetic field generated by the direction of the write current can be controlled to change the magnetization of the magnetization free layer 210 to a desired direction. Thereby, desired data is recorded in the magnetization free layer 210. Such a writing method in which a writing current is allowed to flow through the conductive layer 250 can be called a wiring layer writing type because a wiring dedicated to writing is provided.

Next, a method for reading data will be described. First, a read current is passed through the paths of the magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230a. Then, data is read by detecting a change in resistance according to the relative angle between the magnetization of the magnetization fixed layer 230a and the magnetization of the magnetization free layer 210. For example, when the magnetization of the magnetization fixed layer 230a and the magnetization of the magnetization free layer 210 are parallel (example: “0” is stored), the low resistance state is realized, and the magnetization of the magnetization fixed layer 230a and the magnetization of the magnetization free layer 210 are realized. Are antiparallel (example: “1” is stored), a high resistance state is realized. A change in the resistance of the magnetoresistive effect element is detected as a voltage signal or a current signal, and data stored in the magnetoresistive effect element is determined using the voltage signal or the current signal.

4C includes a magnetization fixed layer 230b, a magnetization free layer 210, a nonmagnetic layer 220 provided between the magnetization fixed layer 230b and the magnetization free layer 210, and a nonmagnetic layer sandwiching the magnetization free layer 210. 220, a conductive layer 250 provided on the opposite side of 220, and a magnetization free layer 210a provided on the opposite side of the magnetization free layer 210 across the conductive layer 250. Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

The magnetization free layer 210, the magnetization fixed layer 230b, and the nonmagnetic layer 220 are the same as the magnetization free layer 210, the magnetization fixed layer 230a, and the nonmagnetic layer 220 in FIG. 4B. However, the magnetoresistive effect element of FIG. 4B is different from the magnetoresistive effect element of FIG. 4B in that the magnetization free layer has two magnetization

free layers

210 and 210a, and the conductive layer 250 is between the magnetization free layer 210 and magnetization free layer 210a. Different.

The magnetization free layer 210a is preferably made of the same ferromagnetic material as the magnetization free layer 210, has the same in-plane magnetic anisotropy, and has a reversible magnetization in the reverse direction. The magnetization free layer 210a is magnetically coupled to the magnetization free layer 210 in an antiferromagnetic manner, and stabilizes the magnetization of each other. Further, the magnetization free layer 210a and the magnetization free layer 210 located on both sides of the conductive layer 250 have a function of amplifying a current-induced magnetic field generated by a write current flowing through the conductive layer 250 during a write operation. Note that the magnetization free layer 210, the nonmagnetic layer 220, the magnetization fixed layer 230b, and the magnetization free layer 210a may be stacked in this order, and the magnetization fixed layer 230b may also function as the conductive layer 250. However, in this case, a nonmagnetic layer is inserted between the magnetization fixed layer 230b and the magnetization free layer 210a, and the magnetic coupling between the magnetization fixed layer 230b and the magnetization free layer 210a is cut.
Other configurations are the same as those in the case of FIG.

Next, regarding the data writing method of the magnetoresistive effect element 8b of the present embodiment, the current induced magnetic field due to the write current flowing through the conductive layer 250 is amplified by the magnetization free layer 210a and the magnetization free layer 210, and the current induction Except for the point that the magnetization free layer 210a is magnetized in the opposite direction to the magnetization free layer 210 by the magnetic field, it is the same as in the case of FIG. A writing layer 250 serving as a writing wiring layer is located between the magnetization free layer 210a and the magnetization free layer 210, and such a writing method in which a writing current is supplied thereto is also referred to as an intermediate wiring layer writing type.
The method for reading data from the magnetoresistive effect element is the same as that in the case of FIG.

In FIG. 4C, the magnetization free layer 210 and the magnetization free layer 210a are depicted as having substantially the same shape, but the shapes of the two layers may be different. For example, the magnetization free layer 210 a may have the same shape as the conductive layer 250. In this case, the magnetization of the magnetization free layer 210a is oriented in the x direction, which is the longitudinal direction in a steady state, and rotates in the direction of a current-induced magnetic field when a current is introduced into the conductive layer 250, A magnetic field can be applied efficiently. The magnetization free layer 210a having such a role is often referred to as a cladding layer or a yoke layer.

In the above description, the current-induced magnetic field writing type magnetoresistive effect elements shown in FIGS. 4A to 4C are all examples in which the magnetization free layer and the magnetization fixed layer are composed of in-plane magnetization films having in-plane magnetic anisotropy. ing. However, the present invention is not limited to this, and the magnetization free layer and the magnetization fixed layer may be composed of a perpendicular magnetization film having perpendicular magnetic anisotropy.

As described above, as the magnetoresistive effect element used in the MRAM 4, any of the current-induced magnetic field write type magnetoresistive effect elements shown in FIGS. 4A to 4C can be used.

In the present invention, in a memory-mounted semiconductor device, an appropriate type of MRAM is selected and arranged according to a required function. For example, as a memory for a logic circuit that requires high-speed operation, an MRAM using a current-induced magnetic field writing type magnetoresistive effect element capable of high-speed operation shown in FIGS. 4A to 4C is used. On the other hand, as memories for main storage devices and auxiliary storage devices that require low current (large capacity and high integration), the low current (large capacity and high capacity) shown in FIGS. 2A to 2D and FIGS. 3A and 3B can be used. An MRAM using a spin-polarized current writing type magnetoresistive element that can be integrated) is used. As described above, the non-volatile memory mixed in which high-speed processing and large-capacity processing are made compatible by using a combination of two kinds of MRAMs for the memory for high-speed operation and the memory for low current (large capacity and high integration). A system (memory mounted semiconductor device) can be obtained.

Next, the circuit configuration of the memory cell 301 in the MRAMs 4 and 5 of this embodiment will be described with reference to FIGS. 5A and 5B. 5A and 5B, as the memory cell 301, any one of the magnetoresistance effect element of the spin-polarized current writing type current-induced domain wall motion type, spin-injection magnetization switching type, and current-induced magnetic field writing type may be used. It can also be used.

FIG. 5A is a circuit diagram showing a configuration example of a memory cell in which the magnetoresistive effect element of this embodiment is integrated. FIG. 5A shows a circuit configuration of a single memory cell 301, but it is actually understood by those skilled in the art that a plurality of memory cells 301 are arranged in an array and integrated in the MRAMs 4 and 5. Will be understood.

5A, in the case of a current-induced domain wall motion type magnetoresistive effect element (FIGS. 2A to 2D), a terminal connected to the magnetization fixed layer 30 is connected to a ground line GND for reading through a node N3. The One of the two terminals connected to the magnetization free layer 10 is connected to one source / drain of the MOS transistor M1 via the node N1, and the other is connected to one source / drain of the MOS transistor M2 via the node N2. Connected. The other source / drain of the MOS transistors M1 and M2 are connected to bit lines BL1 and BL2 for writing, respectively. Further, the gate electrodes of the MOS transistors M1 and M2 are connected to the word line WL. That is, 310 in the figure corresponds to the first magnetization free layer 10.

In the case of the spin-injection magnetization reversal type magnetoresistive effect element (FIGS. 3A to 3B), one of the magnetization fixed layer 30 and the first magnetization free layer 10 is connected to one source / drain of the MOS transistor M1 via the node N1. The other is connected to one source / drain of the MOS transistor M2 via a node N2. The other sources / drains of the MOS transistors M1 and M2 are connected to the bit lines BL1 and BL2, respectively. Further, the gate electrodes of the MOS transistors M1 and M2 are connected to the word line WL. 310 in the figure corresponds to the magnetization fixed layer 30, the nonmagnetic layer 20, and the first magnetization free layer 10. In this case, although not shown, one of the magnetization fixed layer 30 and the first magnetization free layer 10 is connected to the ground line GND via the node N1 (not the node N3).

In the case of the current-induced magnetic field writing type magnetoresistive effect element (FIG. 4A), one of two terminals connected to both ends of the magnetization fixed layer 230 is connected to one source / drain of the MOS transistor M1 via the node N1. The other is connected to one source / drain of the MOS transistor M2 via the node N2. A terminal connected to the magnetization free layer 210 is connected to a ground line GND for reading via a node N3. 310 in the figure corresponds to the magnetization fixed layer 230.

In the case of the current-induced magnetic field writing type magnetoresistive effect element (FIG. 4B), one of two terminals connected to both ends of the conductive layer 250 is connected to one source / drain of the MOS transistor M1 via the node N1. The other is connected to one source / drain of the MOS transistor M2 via a node N2. A terminal connected to the magnetization free layer 210 is connected to a ground line GND for reading via a node N3. However, in this case, the magnetization fixed layer 230a and the conductive layer 250 are electrically connected. 310 in the figure corresponds to the conductive layer 250.

In the case of the current-induced magnetic field writing type magnetoresistive effect element (FIG. 4C), one of two terminals connected to both ends of the conductive layer 250 is connected to one source / drain of the MOS transistor M1 via the node N1. The other is connected to one source / drain of the MOS transistor M2 via a node N2. A terminal connected to the magnetization fixed layer 230b is connected to the ground line GND for reading via the node N3. 310 in the figure corresponds to the conductive layer 250.

FIG. 5B is a block diagram showing a configuration example of an MRAM in which the memory cells of this embodiment are integrated. In FIG. 5B, the MRAM 360 includes a memory cell array 361 in which a plurality of memory cells 301 are arranged in a matrix. The memory cell array 361 includes a reference cell 301r that is referred to when data is read, in addition to the memory cell 301 used for data recording described in FIG. 5A. The structure of the reference cell 301r is the same as that of the memory cell 301.

The word line WL is connected to the X selector 362. The X selector 362 selects a word line WL connected to the target memory cell 301s as a selected word line WLs during a data write operation and a read operation. The bit line BL1 is connected to the Y-side current termination circuit 364, and the bit line BL2 is connected to the Y selector 363. The Y selector 363 selects the bit line BL2 connected to the target memory cell 301s as the selected bit line BL2s during the data write operation and the read operation. The Y-side current termination circuit 364 selects the bit line BL1 connected to the target memory cell 301s as the selected bit line BL1s.

The Y-side current source circuit 365 supplies or draws a predetermined write current (Iwrite) to the selected bit line BL2s during the data write operation. The Y-side power supply circuit 366 supplies a predetermined voltage to the Y-side current termination circuit 364 during the data write operation. As a result, the write current (Iwrite) flows into or out of the Y selector 363. These X selector 362, Y selector 363, Y side current termination circuit 364, Y side current source circuit 365, and Y side power supply circuit 366 are “write current supply circuits for supplying a write current (Iwrite) to the memory cell 301. Is comprised.

The read current adding circuit 367 supplies a predetermined read current (Iread) to the selected second bit line BL2s during the data read operation. The Y-side current termination circuit 364 sets the bit line BL1 to “Open”. The read current load circuit 367 supplies a predetermined read current (Iread) to the reference bit line BL2r connected to the reference cell 301r. The sense amplifier 368 reads data from the target memory cell 301s based on the difference between the potential of the reference bit line BL2r and the potential of the selected bit line BL2s, and outputs the data. The X selector 362, Y selector 363, Y-side current termination circuit 364, read current adding circuit 367, and sense amplifier 368 constitute a “read current supply circuit” for supplying a read current (Iread) to the memory cell 301. is doing.

Next, a writing method and a reading method in the MRAM shown in FIGS. 5A and 5B will be described. First, when writing, the word line WL is pulled up to a “high” level, and the MOS transistors M1 and M2 are turned “ON”. One of the bit lines BL1 and BL2 is pulled up to the “high” level, and the other is pulled down to the “low” level. Which of the bit lines BL1 and BL2 is pulled up to the “high” level and which is pulled down to the “low” level is determined by data to be written to the magnetoresistive element. As described above, data “0” and “1” can be written separately.

On the other hand, when reading, the word line WL is pulled up to the “high” level, and the MOS transistors M1 and M2 are turned “ON”. One of the bit lines BL1 and BL2 is pulled up to the “high” level, and the other is set to “open” (floating). At this time, a read current passing through the magnetoresistive effect element flows from one of the bit lines BL1 and BL2 to the ground line GND. The potential of the bit line through which the read current flows or the magnitude of the read current depends on a change in resistance of the magnetoresistive element due to the magnetoresistive effect. By detecting this change in resistance as a voltage signal or a current signal, high-speed reading can be performed.

However, the circuit configurations shown in FIGS. 5A and 5B and the circuit operation described here are merely examples of a method for carrying out the present invention, and can be implemented by other circuit configurations.

It has been reported that when the circuit configuration of FIG. 5A is applied to a current-induced magnetic field writing type magnetoresistive effect element (FIGS. 4A to 4C), operation at 200 MHz or higher is possible (N. Sakimura). et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.42, 2007, pp.830.). However, other circuit configurations as shown in FIG. 6 can be used to perform higher-speed operation.

FIG. 6 is a circuit diagram showing another configuration example of the memory cell in which the magnetoresistive effect element of this embodiment is integrated. FIG. 6 shows a circuit configuration of a single memory cell 302. However, it will be understood by those skilled in the art that a plurality of memory cells 302 are actually arranged in an array and integrated in an MRAM. It will be understood. It has been reported that when the circuit configuration of FIG. 6 is applied to a current-induced magnetic field writing type magnetoresistive effect element (FIGS. 4A to 4C), operation at 500 MHz or more is possible (N. Sakimura). et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.42, 2007, pp.830.).

In FIG. 6, two MTJ1 and MTJ2 are used for one memory cell 302. Complementary data ("0" and "1" or "1" and "0") are stored in MTJ1 and MTJ2. In addition, in the memory cell 302, the read signal is amplified by the MOS transistors M13 and M14.

When the first and second magnetoresistive elements in FIG. 4A are used as MTJ1 and MTJ2, in the second magnetoresistive element (MTJ2), one of the two terminals connected to both ends of the magnetization fixed layer 230 is One source / drain of the MOS transistor M11 is connected via the node N11, and the other is connected to one terminal of the magnetization fixed layer 230 of the first magnetoresistive effect element (MTJ1) via the node N12. A terminal connected to the magnetization free layer 210 is connected to a wiring SPL that supplies a read current via a node N14. In the first magnetoresistance effect element (MTJ1), one of two terminals connected to both ends of the magnetization fixed layer 230 is a node to the other terminal of the magnetization fixed layer 230 of the second magnetoresistance effect element (MTJ2). The other is connected via N12, and the other is connected to one source / drain of MOS transistor M12 via node N13. A terminal connected to the magnetization free layer 210 is connected to a ground line GND for reading via a node N15. That is, 311 and 312 in the figure correspond to the magnetization fixed layer 230 of the second and first magnetoresistance effect elements, respectively.

When the first and second magnetoresistive elements in FIG. 4B are used as MTJ1 and MTJ2, in the second magnetoresistive element (MTJ2), one of the two terminals connected to both ends of the conductive layer 250 is a MOS. One source / drain of the transistor M11 is connected via the node N11, and the other is connected to one terminal of the conductive layer 250 of the first magnetoresistive element (MTJ1) via the node N12. A terminal connected to the magnetization free layer 210 is connected to a wiring SPL that supplies a read current via a node N14. In the first magnetoresistive element (MTJ1), one of two terminals connected to both ends of the conductive layer 250 has a node N12 on the other terminal of the conductive layer 250 of the second magnetoresistive element (MTJ2). The other is connected to one source / drain of the MOS transistor M12 via a node N13. A terminal connected to the magnetization free layer 210 is connected to a ground line GND for reading via a node N15. That is, 311 and 312 in the figure correspond to the conductive layers 250 of the second and first magnetoresistive elements, respectively.

When the first and second magnetoresistive elements in FIG. 4C are used as MTJ1 and MTJ2, in the second magnetoresistive element (MTJ2), one of two terminals connected to both ends of the conductive layer 250 is a MOS. One source / drain of the transistor M11 is connected via the node N11, and the other is connected to one terminal of the conductive layer 250 of the first magnetoresistive element (MTJ1) via the node N12. A terminal connected to the magnetization fixed layer 230b is connected to a wiring SPL for supplying a read current via a node N14. In the first magnetoresistive element (MTJ1), one of two terminals connected to both ends of the conductive layer 250 has a node N12 on the other terminal of the conductive layer 250 of the second magnetoresistive element (MTJ2). The other is connected to one source / drain of the MOS transistor M12 via a node N13. A terminal connected to the magnetization fixed layer 230b is connected to a ground line GND for reading through a node N15. That is, 311 and 312 in the figure correspond to the conductive layers 250 of the second and first magnetoresistive elements, respectively.

When the first and second magnetoresistive elements 9 of FIGS. 2A to 2D are used as MTJ1 and MTJ2, in the second magnetoresistive element (MTJ2), the terminal connected to the magnetization fixed layer 30 is a read current. Is connected to a wiring SPL for supplying One of the two terminals connected to the magnetization free layer 10 is connected to one source / drain of the MOS transistor M11 via the node N11, and the other is connected to the magnetization free layer 10 of the first magnetoresistance effect element (MTJ1). Is connected to one end of this via a node N12. In the first magnetoresistive element (MTJ1), the terminal connected to the magnetization fixed layer 30 is connected to the ground line GND for reading. One of the two terminals connected to the magnetization free layer 10 is connected to the other end of the magnetization free layer 10 of the second magnetoresistive effect element (MTJ2) via the node N12, and the other is one of the MOS transistors M12. The source / drain is connected through node N13. That is, 311 and 312 in the figure correspond to the magnetization free layer 10 of the second and first magnetoresistive elements, respectively.

When the first and second magnetoresistive elements in FIGS. 3A to 3B are used as MTJ1 and MTJ2, in the second magnetoresistive element (MTJ2), one of the magnetization free layer 10 and the magnetization fixed layer 30 is One is connected to one source / drain of the MOS transistor M11 via the node N11, and the other is the same terminal of the magnetization free layer 10 and the magnetization fixed layer 30 in the first magnetoresistive element (MTJ1). To the node N12 through the node N12. In the first magnetoresistive effect element (MTJ1), the same one as the second magnetoresistive effect element (MTJ2) connected to the node N12 of the magnetization free layer 10 and the magnetization fixed layer 30 has the second magnetoresistance effect. The effect element (MTJ2) is connected via the node N12, and the rest of the magnetization free layer 10 and the magnetization fixed layer 30 are connected to one source / drain of the MOS transistor M12 via the node N13. Although not shown, the node N14 of the wiring SPL that supplies the read current is connected to the node N11, and the node N15 of the ground line GND is connected to the node N13. 311 and 312 in the figure correspond to the second and first magnetoresistive elements, respectively.

Next, a writing method and a reading method in the MRAM shown in FIG. 6 will be described. First, when writing, the word line WWL is pulled up to a “high” level, and the MOS transistors M11 and M12 are turned “ON”. One of the bit lines WBLa and WBLb is pulled up to the “high” level, and the other is pulled down to the “low” level. Which of the bit lines WBLa and WBLb is pulled up to the “high” level and which is pulled down to the “low” level is determined by the data to be written in the MTJ1 and MTJ2. Thereby, complementary data ("0" and "1" or "1" and "0") are stored in MTJ2 and MTJ1.

On the other hand, when reading, the word line RWL is pulled up to “high” level, and the MOS transistor M15 is turned “ON”. Further, the read voltage supply line SPL is pulled up to the “high” level. At this time, the read current passing through the paths of the node N14, the nodes N11, MTJ2, the nodes N12, MTJ1, the node N13, and the node N15 flows from the read voltage supply line SPL to the ground line GND via the MTJ1 and MTJ2. At this time, the potential of the node N12 between MTJ2 and MTJ1 depends on complementary data stored in MTJ2 and MTJ1. Therefore, the potential of the node N12 is amplified by the MOS transistors M13 and M14 and detected by the bit line RBL, thereby enabling high-speed reading.

However, the circuit configuration shown in FIG. 6 and the circuit operation described here are merely examples of a method for carrying out the present invention, and can be implemented by other circuit configurations.

(First modification)
Next, the configuration of a first modification of the magnetoresistive effect element in each MRAM according to an embodiment of the present invention will be described. 7A to 7D are schematic views showing the configuration of a first modification of the magnetoresistive effect element in each MRAM according to the embodiment of the present invention. The magnetoresistive effect element 8 and the magnetoresistive effect element 9 according to the embodiment of the present invention are formed on the same chip. However, the white arrow in each component in the figure indicates the direction of magnetization (the same applies hereinafter).

As shown in FIG. 7A, the magnetoresistive effect element 9 is used in a memory cell of the MRAM 5 for high integration and large capacity (low current). This is a spin-polarized current writing type current-induced domain wall motion type magnetoresistive effect element. The magnetoresistive effect element 9 includes a magnetization free layer 10, a magnetization fixed layer 30, and a nonmagnetic layer 20 provided between the magnetization free layer 10 and the magnetization fixed layer 30. The magnetoresistive effect element 9 is the same as the magnetoresistive effect element shown in FIG. 2B. As terminals of the magnetization free layer 10, a contact 41 is connected to the first magnetization fixed region 11a, and a contact 42 is connected to the second magnetization fixed region 11b. Each contact is connected to, for example, a MOS transistor (see FIG. 5A) of the memory cell. The magnetization fixed layer 30 is connected to, for example, the ground line GND (see FIG. 5A). Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

In the magnetoresistive effect element 9, the write current flows through the path of the contact 41, the first magnetization fixed region 11 a, the magnetization free region 12, the second magnetization fixed region 11 b, and the contact 42. Thereby, the domain wall of the magnetization free layer 10 moves according to the write current. The read current flows through a magnetic tunnel junction (MTJ) composed of the magnetization fixed layer 30, the nonmagnetic layer 20, and the magnetization free layer 10 (magnetization free region 12). Other configurations and operations are as described in relation to the magnetoresistive effect element in FIG. 2B. The shape of the magnetization free layer 10 may be any of FIGS. 2A to 2D.

The magnetoresistive effect element 8 is used in a memory cell of the MRAM 4 for high speed operation. This is a current-induced magnetic field writing type magnetoresistive effect element. In particular, the magnetoresistive effect element 8 is of the aforementioned wiring layer writing type. The magnetoresistive effect element 8 includes a magnetization free layer 210, a nonmagnetic layer 220, a magnetization fixed layer 230 a, and a conductive layer 250 provided in the vicinity of the magnetization free layer 210. The magnetoresistive effect element 8 is the same as the magnetoresistive effect element shown in FIG. 4B except that a perpendicular magnetization film is used. The magnetization free layer 210 is connected to the conductive layer 250 through the metal layer 257. The conductive layer 250 has one end connected to the contact 255 and the other end connected to the contact 256. Each contact is connected to, for example, a MOS transistor (see FIG. 5A) of the memory cell. The magnetization fixed layer 230a is connected to the ground line GND (see FIG. 5A), for example. Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

In the example of FIG. 7A, the conductive layer 250 is composed of a stacked body of the same material as the magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230a. The write current may flow through any material layer.

In the magnetoresistive effect element 8, the write current flows through the path of the contact 255, the conductive layer 250, and the contact 256. Thereby, a magnetic field is induced around the conductive layer 250 (a range including the magnetization free layer 210). In addition, the read current flows through a magnetic tunnel junction (MTJ) path formed by the magnetization fixed layer 230a, the nonmagnetic layer 220, and the magnetization free layer 210. Other configurations and operations are as described in relation to the magnetoresistive effect element in FIG. 4B.

The shape of the conductive layer 250 is not particularly limited as long as a desired magnetic field can be induced in a range in which the write current flowing therethrough includes the magnetization free layer 210. For example, FIG. 7B is a plan view of the magnetoresistive effect element 8 of FIG. 7A as viewed from the z direction, but the conductive layer 250 includes magnetic tunnel junctions (the magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230). It may be a substantially C-shape that surrounds. Further, as shown in FIG. 7C, the conductive layer 250 may be a substantially I-shaped conductive layer 250a that linearly extends beside the magnetic tunnel junction. Further, as shown in FIG. 7D, the conductive layer 250 may be a substantially L-shaped conductive layer 250b that passes while bending beside the magnetic tunnel junction.

In the case of this modification, in addition to the effects described above, the following effects are obtained.
The magnetoresistive effect element 8 and the magnetoresistive effect element 9 according to the embodiment of the invention are formed on the same chip. The magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230a of the magnetoresistive effect element 8 are the same as the magnetization free layer 10, the nonmagnetic layer 20, and the magnetization fixed layer 30 of the magnetoresistive effect element 9, respectively. It can be formed simultaneously with the material. That is, the MRAM 4 and the MRAM 5 can be formed by the same process, and the number of processes does not increase. As a result, the semiconductor device 1 can be manufactured at a low cost and in a short time. 7A to 7D, the conductive layer 250 is also formed of the same material as the magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230a. The semiconductor device 1 can be manufactured at a lower cost and in a shorter time.

(Second modification)
Next, the configuration of the second modification of the magnetoresistive effect element in each MRAM according to the embodiment of the present invention will be described. FIG. 8 is a perspective view showing a configuration of a second modification of the magnetoresistive effect element in each MRAM according to the embodiment of the present invention. The magnetoresistive effect element 8a and the magnetoresistive effect element 9a according to the second modification of the embodiment of the present invention are formed on the same chip.

As shown in FIG. 8, the magnetoresistive effect element 9a is used in a memory cell of the MRAM 5 for high integration and large capacity (low current). This is a spin-polarized current writing type current-induced domain wall motion type magnetoresistive effect element. The magnetoresistive effect element 9 a includes a magnetization free layer 10, a magnetization fixed layer 30, and a nonmagnetic layer 20 provided between the magnetization free layer 10 and the magnetization fixed layer 30. The magnetoresistive effect element 9a is the same as the magnetoresistive effect element shown in FIG. 2A. As terminals of the magnetization free layer 10, a contact 41 is connected to the first magnetization fixed region 11a, and a contact 42 is connected to the second magnetization fixed region 11b. Each contact is connected to, for example, a MOS transistor (see FIG. 5A) of the memory cell. The magnetization fixed layer 30 is connected to, for example, the ground line GND (see FIG. 5A). Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

In the magnetoresistive effect element 9a, the write current flows through the path of the contact 41 (+ 41a), the first magnetization fixed region 11a, the magnetization free region 12, the second magnetization fixed region 11b, and the contact 42 (+ 42a). Thereby, the domain wall of the magnetization free layer 10 moves according to the write current. The read current flows through a magnetic tunnel junction (MTJ) composed of the magnetization fixed layer 30, the nonmagnetic layer 20, and the magnetization free layer 10 (magnetization free region 12). Other configurations and operations are as described in relation to the magnetoresistive effect element in FIG. 2A. The shape of the magnetization free layer 10 may be any of FIGS. 2A to 2D.

The magnetoresistive effect element 8a is used in a memory cell of the MRAM 4 for high speed operation. This is a current-induced magnetic field writing type magnetoresistive effect element. In particular, the magnetoresistive effect element 8a is the above-described intermediate layer wiring write type. The magnetoresistive effect element 8a includes a magnetization fixed layer 230b, a nonmagnetic layer 220, a magnetization free layer 210, a conductive layer 250, and a magnetization free layer 210b. The magnetoresistive effect element 8a is the same as the magnetoresistive effect element shown in FIG. 4C. The conductive layer 250 has terminals at both ends connected to, for example, MOS transistors of two memory cells (see FIG. 5A). The magnetization fixed layer 230b is connected to, for example, the ground line GND (see FIG. 5A). Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

In the magnetoresistive effect element 8a, the write current flows through the conductive layer 250. Thereby, a magnetic field is induced around the conductive layer 250 (a range including the magnetization free layer 210 and the magnetization free layer 210a). Further, the read current flows through a magnetic tunnel junction (MTJ) path composed of the magnetization fixed layer 230b, the nonmagnetic layer 220, and the magnetization free layer 210. Other configurations and operations are as described in relation to the magnetoresistive effect element in FIG. 4C.

In the case of this modification, in addition to the effects described above, the following effects are obtained.
The magnetoresistive effect element 8a and the magnetoresistive effect element 9a according to the embodiment of the present invention are formed on the same chip. The magnetization free layer 210a, the conductive layer 250a, the magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230b of the magnetoresistive effect element 8a are respectively connected to the

contacts

41a and 42a,

contacts

41, 42, and The magnetization free layer 10, the nonmagnetic layer 20, and the magnetization fixed layer 30 can be simultaneously formed in the same layer with the same material. That is, the MRAM 4 and the MRAM 5 can be formed by the same process, and the number of processes does not increase. As a result, the semiconductor device 1 can be manufactured at a low cost and in a short time.

(Third Modification)
Next, the configuration of a third modification of the magnetoresistive element in each MRAM according to the embodiment of the present invention will be described. FIG. 9 is a perspective view showing a configuration of a third modification of the magnetoresistive element in each MRAM according to the embodiment of the present invention. The magnetoresistive effect element 8b and the magnetoresistive effect element 9b according to the third modification of the embodiment of the present invention are formed on the same chip.

As shown in FIG. 9, the magnetoresistive effect element 9b is used in a memory cell of the MRAM 5 for high integration and large capacity (low current). This is a spin-polarization current writing type spin-injection magnetization reversal type magnetoresistive effect element. The magnetoresistive effect element 9 b includes a magnetization free layer 10, a magnetization fixed layer 30, and a nonmagnetic layer 20 provided between the magnetization free layer 10 and the magnetization fixed layer 30. The magnetoresistive effect element 9b is the same as the magnetoresistive effect element shown in FIG. 3A. A contact 94 and a wiring layer 95 are connected as terminals of the magnetization free layer 10, and a contact 91 and a wiring layer 92 are connected to the magnetization fixed layer 30. Each contact and wiring layer is connected to, for example, a MOS transistor (see FIG. 5A) of the memory cell. Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

In the magnetoresistive effect element 9b, the write current flows through the path of the contact 91, the magnetization fixed layer 30, the nonmagnetic layer 20, the magnetization free layer 10, and the contact 94. Thereby, the magnetization direction of the magnetization free layer 10 changes according to the write current. The read current flows through a magnetic tunnel junction (MTJ) composed of the magnetization fixed layer 30, the nonmagnetic layer 20, and the magnetization free layer 10. Other configurations and operations are as described in connection with the magnetoresistive effect element of FIG. 3A.

The magnetoresistive effect element 8b is used in a memory cell of the MRAM 4 for high speed operation. This is a current-induced magnetic field writing type magnetoresistive effect element. In particular, the magnetoresistive effect element 8b is the above-described base write type. The magnetoresistive element 8 b includes a magnetization fixed layer 230, a nonmagnetic layer 220, and a magnetization free layer 210. The magnetoresistive effect element 8b is the same as the magnetoresistive effect element shown in FIG. 4A. A contact 258 and a wiring layer 259 are connected as terminals of the magnetization free layer 210. Further, the contact 260 and the wiring layer 261 are connected as one terminal of the magnetization fixed layer 230, and the contact 262 and the wiring layer 263 are connected as the other terminal. The terminals of both ends of the magnetization fixed layer 230 are connected to, for example, MOS transistors (see FIG. 5A) of two memory cells. The magnetization free layer 210 is connected to the ground line GND (see FIG. 5A), for example. Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

In the magnetoresistive effect element 8b, the write current flows through the magnetization fixed layer 230. Thereby, a magnetic field is induced around the magnetization fixed layer 230 (a range including the magnetization free layer 210). In addition, the read current flows through a magnetic tunnel junction (MTJ) path constituted by the magnetization fixed layer 230, the nonmagnetic layer 220, and the magnetization free layer 210. Other configurations and operations are as described in relation to the magnetoresistive element of FIG. 4A.

In the case of this modification, in addition to the effects described above, the following effects are obtained.
The magnetoresistive effect element 8b and the magnetoresistive effect element 9b according to the embodiment of the present invention are formed on the same chip. The magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230 of the magnetoresistive effect element 8b are the same layer as the magnetization free layer 10, the nonmagnetic layer 20, and the magnetization fixed layer 30 of the magnetoresistance effect element 9b, respectively. It can be formed simultaneously with the material. That is, the MRAM 4 and the MRAM 5 can be formed by the same process, and the number of processes does not increase. As a result, the semiconductor device 1 can be manufactured at a low cost and in a short time.

(Fourth modification)
Next, the configuration of a fourth modification of the magnetoresistive element in each MRAM according to the embodiment of the present invention will be described. FIG. 10 is a perspective view showing a configuration of a fourth modification of the magnetoresistive effect element in each MRAM according to the embodiment of the present invention. The magnetoresistive effect element 8c and the magnetoresistive effect element 9c according to the fourth modification of the embodiment of the present invention are formed on the same chip.

As shown in FIG. 10, the magnetoresistive effect element 9c is used for a memory cell of the MRAM 5 for high integration and large capacity (low current). This is a spin-polarization current writing type spin-injection magnetization reversal type magnetoresistive effect element. The magnetoresistive effect element 9 c includes a magnetization free layer 10, a magnetization fixed layer 30, and a nonmagnetic layer 20 provided between the magnetization free layer 10 and the magnetization fixed layer 30. The magnetoresistive effect element 9c is the same as the magnetoresistive effect element shown in FIG. 3B. A contact 94 and a wiring layer 95 are connected as terminals of the magnetization free layer 10, and a contact 91 and a wiring layer 92 are connected to the magnetization fixed layer 30. Each contact and wiring layer is connected to, for example, a MOS transistor (see FIG. 5A) of the memory cell. Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

In the magnetoresistive effect element 9 c, the write current flows through the path of the contact 91, the magnetization fixed layer 30, the nonmagnetic layer 20, the magnetization free layer 10, and the contact 94. Thereby, the magnetization direction of the magnetization free layer 10 changes according to the write current. The read current flows through a magnetic tunnel junction (MTJ) composed of the magnetization fixed layer 30, the nonmagnetic layer 20, and the magnetization free layer 10. Other configurations and operations are as described in relation to the magnetoresistive effect element in FIG. 3B.

The magnetoresistive effect element 8c is used in a memory cell of the MRAM 4 for high speed operation. This is a current-induced magnetic field writing type magnetoresistive effect element. In particular, the magnetoresistive effect element 8c is the above-described wiring layer writing type. The magnetoresistive element 8 c includes a magnetization free layer 210, a nonmagnetic layer 220, a magnetization fixed layer 230 a, and a conductive layer 250 a provided in the vicinity of the magnetization free layer 210. The magnetoresistive effect element 8c is the same as the magnetoresistive effect element shown in FIG. 4B except that a perpendicular magnetization film is used. The conductive layer 250a is the same as the conductive layer 250a in FIG. 7C. The magnetization fixed layer 230a is connected to the conductive layer 250a through a contact 267, a metal layer 268, and a contact 269. The conductive layer 250 a has one end connected to the contact 270 and the wiring layer 271, and the other end connected to the contact 272 and the wiring layer 273. The

contacts

270 and 272 are connected to, for example, a MOS transistor (see FIG. 5A) of the memory cell. The magnetization free layer 210 is connected to the ground line GND (see FIG. 5A), for example. Although not shown, in addition to the above-described layers, it is desirable that an electrode layer, a diffusion prevention layer, a base layer, and the like are appropriately provided.

In the example of FIG. 10, the conductive layer 250a is formed of a stacked body made of the same material as the magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230a. The write current may flow through any material layer.

In the magnetoresistive effect element 8c, the write current flows through the path of the contact 270, the conductive layer 250a, and the contact 272. As a result, a magnetic field is induced around the conductive layer 250a (a range including the magnetization free layer 210). In addition, the read current flows through a magnetic tunnel junction (MTJ) path formed by the magnetization fixed layer 230a, the nonmagnetic layer 220, and the magnetization free layer 210. Other configurations and operations are as described in relation to the magnetoresistive effect element in FIG. 4B.

In the case of this modification, in addition to the effects described above, the following effects are obtained.
The magnetoresistive effect element 8c and the magnetoresistive effect element 9c according to the embodiment of the present invention are formed on the same chip. The magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230a of the magnetoresistive effect element 8c are the same layer as the magnetization free layer 10, the nonmagnetic layer 20, and the magnetization fixed layer 30 of the magnetoresistive effect element 9c, respectively. It can be formed simultaneously with the material. That is, the MRAM 4 and the MRAM 5 can be formed by the same process, and the number of processes does not increase. As a result, the semiconductor device 1 can be manufactured at a low cost and in a short time. In the case of FIG. 10, the conductive layer 250a is also formed of the same material as that of the magnetization free layer 210, the nonmagnetic layer 220, and the magnetization fixed layer 230a, and thus can be formed in the same process. Thus, the semiconductor device 1 can be manufactured at a lower cost and in a shorter time.

(5th modification)
Next, the configuration of the fifth modification example of the magnetoresistive effect element in each MRAM according to the embodiment of the present invention will be described. 11A to 11C are schematic views schematically showing the configuration of the fifth modification example of the magnetoresistance effect element according to this example. FIG. 11A is a perspective view, and FIGS. 11B and 11C are xy plan views. However, the combination of FIG. 11A and FIG. 11B shows a case having perpendicular magnetic anisotropy, and the combination of FIG. 11A and FIG. 11C shows a case having in-plane magnetic anisotropy.

The magnetoresistive effect element 9d is used in a memory cell of the MRAM 5 for high integration and large capacity (low current). This is a spin-polarized current writing type current-induced domain wall motion type magnetoresistive effect element.

In the current-induced domain wall motion type magnetoresistive effect element 9d having the structure of FIGS. 11A and 11B or FIGS. 11A and 11C, the first magnetization free layer 10 includes a first magnetization fixed region 11a and a second magnetization fixed region. 11b and a magnetization free region 12. However, the first magnetization fixed region 11a is connected to one end of the magnetization free region 12 as shown in FIGS. 2A to 2D, and the second magnetization fixed region 11b is connected to the other end. Instead of being provided, the first magnetization fixed region 11 a and the second magnetization fixed region 11 b are connected to one end of the magnetization free region 12. That is, the first magnetization fixed region 11a, the second magnetization fixed region 11b, and the magnetization free region 12 form a three-forked path (three-forked, substantially Y-shaped). The magnetic pinned layer 30, the nonmagnetic layer 20, and the magnetization free region 20 constitute a magnetic tunnel junction (MTJ).

In the case of FIG. 11B, in the magnetoresistive effect element 9d, the first magnetization free layer 10 and the magnetization fixed layer 30 have magnetic anisotropy in the film thickness direction (perpendicular magnetic anisotropy). And the magnetization of the 1st magnetization fixed area | region 11a and the 2nd magnetization fixed area | region 11b which comprises the 1st magnetization free layer 10 is being fixed to the antiparallel direction mutually in the film thickness direction. The magnetization free region 12 can take magnetization parallel to one of the magnetizations of the first magnetization fixed region 11a and the second magnetization fixed region 11b. The magnetization of the magnetization fixed layer 30 is fixed in the film thickness direction. For example, the magnetization of the first magnetization fixed region 11a is fixed in the + z direction, and the magnetization of the second magnetization fixed region 11b is fixed in the −z direction. The magnetization free region 12 can take magnetization in either the + z direction or the −z direction. The magnetization fixed layer 30 has magnetization fixed in the −z direction.

In the case of FIG. 11C, in the magnetoresistive effect element 9d, the first magnetization free layer 10 and the magnetization fixed layer 30 have magnetic anisotropy in the in-plane direction (in-plane magnetic anisotropy). The magnetizations of the first magnetization fixed region 11a and the second magnetization fixed region 11b constituting the first magnetization free layer 10 are in the in-plane direction, one is in the direction toward the magnetization free region 12, and the other is from the magnetization free region 12. It is fixed in the direction of leaving. The magnetization free region 12 can take magnetization in a direction toward the connection portion between the first magnetization fixed region 11a and the second magnetization fixed region 11b or in the opposite direction. The magnetization of the magnetization fixed layer 30 is fixed in the in-plane direction substantially parallel to the magnetization of the magnetization free region 12. For example, the magnetization of the first magnetization fixed region 11 a is fixed in the direction toward the magnetization free region 12, and the magnetization of the second magnetization fixed region 11 b is fixed in the direction away from the magnetization free region 12. The magnetization free region 12 can take magnetization in either the + x direction or the −x direction. The magnetization fixed layer 30 has magnetization fixed in the + x direction.

The magnetoresistive effect element 9d having the structure of FIGS. 11A and 11B or FIGS. 11A and 11C is a four-terminal element. One of the four terminals is provided in the magnetization fixed layer 30, the other two terminals are provided in the first magnetization fixed region 11 a and the second magnetization fixed region 11 b, and the remaining one terminal is the magnetization free region 12. Provided. In the magnetoresistive effect element 9 d, a domain wall is formed either near the boundary between the first magnetization fixed region 11 a and the magnetization free region 12 or near the boundary between the second magnetization fixed region 11 b and the magnetization free region 12. In the magnetoresistive element 9d, writing is performed by passing a current between the first magnetization fixed region 11a and the magnetization free region 12 or between the second magnetization fixed region 11b and the magnetization free region 12. In this case, the magnetic domain wall starts from the boundary between the first magnetization fixed region 11 a or the second magnetization fixed region 11 b and the magnetization free region 12, and is written by exiting from the other end of the magnetization free region 12. Is called.

12A to 12B are circuit diagrams showing a configuration example of a memory cell in which a fifth modification of the magnetoresistive effect element of this embodiment is integrated. These show two examples of circuit configurations adopted when the magnetoresistive effect element 9d has the configurations of FIGS. 11A and 11B or FIGS. 11A and 11C.
In FIG. 12A, two MOS transistors M21 and M22 are provided for one memory cell 303. One of the source / drain of the MOS transistor M21 is connected to the ground line GND, and the other is connected to one end of the first magnetization fixed region 11a (the side opposite to the boundary with the magnetization free region 12). In addition, one of the source / drain of the MOS transistor M22 is connected to the ground line GND, and the other is connected to one end of the second magnetization fixed region 11b (the side opposite to the boundary with the magnetization free region 12). The gate of the MOS transistor M21 is connected to the word line WLa, and the gate of the MOS transistor M22 is connected to the word line WLb.

Further, a bit line BLa is connected to the end of the magnetization free region 12 (on the opposite side to the boundary between the first magnetization fixed region 11a and the second magnetization fixed region 11b). The bit line BLa is a write wiring for supplying a write current to the magnetization free layer 10. A bit line BLb is connected to the magnetization fixed layer 30 that is one end of the magnetic tunnel junction (MTJ). The bit line BLb is a read wiring for supplying a read current to the magnetic tunnel junction (MTJ).

Data write and read operations in the circuit configuration as shown in FIG. 12A will be described.
Data can be written according to which of the word line WLa and the word line WLb is pulled up to the “high” level and which is pulled down to the “low” level. For example, when the word line WLa is set to the “low” level, the word line WLb is set to the “high” level, the bit line BLa is set to the “high” level, and the ground line GND is set to the “low” level, the MOS transistor M21 is On the other hand, the MOS transistor M22 is turned “ON”. As a result, a write current flows from the bit line BLa to the ground line GND through the magnetization free region 12, the second magnetization fixed region 11b, and the MOS transistor M22. When the word line WLb is set to “low” level, the word line WLa is set to “high”, the bit line BLa is set to “high”, and the ground line GND is set to “low” level, the MOS transistor M22 is set to “OFF”. On the other hand, the MOS transistor M21 is turned "ON". As a result, a write current flows from the bit line BLa to the ground line GND through the magnetization free region 12, the first magnetization fixed region 11a, and the MOS transistor M21. In this way, data can be written separately.

In addition, data can be read out by the first method described below, for example. In the first method, the word line WLa and the word line WLb are set to “Low”, the bit line BLb is set to “High”, and the bit line BLa is set to “Ground”. At this time, the MOS transistors M21 and M22 are “OFF”, and current flows from the bit line BLb through the MTJ to the bit line BLa. As a result, the resistance of the magnetic tunnel junction (MTJ) can be read, and the data of the magnetoresistive effect element can be read. In this case, the information of the memory cell 303 at the intersection of the bit line BLa and the bit line BLb is read, that is, cross-point reading is performed.

Also, the second method as described below may be used for reading data from the memory cell 303 shown in FIG. 12A. First, the word line WLa is set to “high” level and the word line WLb is set to “low” level, whereby the MOS transistor M21 is turned “ON” and the MOS transistor M22 is turned “OFF”. The ground line GND is set to the “low” level, and the bit line BLb is set to the “high” level. Further, the bit line BLa is set to an appropriate potential. At this time, the read current passes through the MTJ from the bit line BLb and flows to the ground line GND via the MOS transistor M21 without flowing to the bit line BLa. This can also read the resistance value of the magnetic tunnel junction (MTJ). Unlike the read method used in the first method, the second method selects one memory cell 303 by the MOS transistor M21, so that high-speed read is possible.

In this embodiment, other circuit configurations as shown in FIG. 12B may be applied. The difference between FIG. 12A and FIG. 12B is that the memory cell 304 of FIG. 12B is provided with three MOS transistors. Specifically, one of the source / drain of the MOS transistor M23 is connected to the end of the magnetization free region 12 (on the side opposite to the first magnetization fixed region 11a and the second magnetization fixed region 11b), and the MOS transistor M23 The other source / drain is connected to the bit line BLc. The gate of the MOS transistor M23 is connected to the word line WLc.

Data write and read operations in the circuit configuration as shown in FIG. 12B will be described.
Data can be written according to which of the first word line WLa and the word line WLb is set to the “low” level and which is set to the “high” level. For example, when the word line WLa is set to the “low” level, the word line WLb is set to the “high” level, and the word line WLc is set to the “high” level, the MOS transistor M21 is set to “OFF”, and the MOS transistor M22 is set to “ The MOS transistor M23 is turned “ON”. Here, when the bit line BLc is set to the “high” level and the ground line GND is set to the “low” level, the bit line BLc passes through the MOS transistor M23, the magnetization free region 12, the second magnetization fixed region 11b, and the MOS transistor M22. Thus, a write current flows to the ground line GND. When the word line WLb is set to “low” level, the word line WLa is set to “high”, and the word line WLc is set to “high”, the MOS transistor M22 is set to “OFF” and the MOS transistor M21 is set to “ON”. The MOS transistor M23 is turned “ON”. Here, when the bit line BLc is set to the “high” level and the ground line GND is set to the “low” level, the bit line BLc passes through the MOS transistor M23, the magnetization free region 12, the first magnetization fixed region 11a, and the MOS transistor M21. Thus, a write current flows to the ground line GND. In this way, data can be written separately.

In addition, data can be read out as follows, for example. First, the word line WLa is set to the “low” level, the word line WLb is set to the “low” level, and the word line WLc is set to the “high” level. At this time, the MOS transistors M21 and M22 are “OFF” and the MOS transistor M23 is “ON”. Here, when the bit line BLb is set to the “high” level and the bit line BLc is set to “low”, the read current passes from the bit line Blb to the MTJ and flows to the bit line BLc via the MOS transistor M23. As a result, data can be read out.

Note that the circuit configuration and circuit operation described here are merely examples, and the magnetoresistive effect element 9d having the structure shown in FIGS. 11A and 11B can be replaced by a memory cell even when other circuit configurations and circuit settings are used. Can be integrated.

The magnetoresistive effect element 9d having the structure of FIG. 11B can be used in place of the magnetoresistive effect element 9 of FIG. 7A. In that case, the magnetoresistive effect element 9d and the magnetoresistive effect element 8 can be simultaneously formed of the same material by the same process. That is, the MRAM 4 and the MRAM 5 can be formed by the same process, and the number of processes does not increase. As a result, the semiconductor device 1 can be manufactured at a low cost and in a short time.

Further, the magnetoresistive effect element 9d having the structure of FIG. 11C can be used in place of the magnetoresistive effect element 9a of FIG. In that case, the magnetoresistive effect element 9d and the magnetoresistive effect element 8a can be simultaneously formed of the same material by the same process. That is, the MRAM 4 and the MRAM 5 can be formed by the same process, and the number of processes does not increase. As a result, the semiconductor device 1 can be manufactured at a low cost and in a short time.

In addition, although the Example of this invention and its various modifications are described above, this invention should not be limited to the above-mentioned Example and modification. Those skilled in the art will readily understand that a plurality of the above-described modified examples can be applied in combination as long as there is no contradiction.

Although the present invention has been described above with reference to the embodiment, the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

The semiconductor device of the present invention can achieve both high-speed processing and large-capacity processing in the internal memory as a memory-embedded semiconductor device.

This application is based on Japanese Patent Application No. 2008-058792 filed on Mar. 7, 2008, claiming the benefit of priority from that application, the disclosure of that application should be cited Is incorporated here as it is.

Claims

A first magnetic random access memory having first memory cells;
A second magnetic random access memory having a second memory cell operating at a higher speed than the first memory cell, and provided in the same chip as the first magnetic random access memory;
The first memory cell includes
A first magnetization fixed layer having a fixed magnetization direction;
A first magnetization free layer whose magnetization direction is reversible;
A first nonmagnetic layer sandwiched between the first magnetization fixed layer and the first magnetization free layer;
The first magnetization free layer and the first magnetization fixed layer are made of a ferromagnetic material,
A write current flows through at least the first magnetization free layer;
The second memory cell includes
A second magnetization free layer;
A second magnetization fixed layer;
A second nonmagnetic layer provided between the second magnetization free layer and the second magnetization fixed layer;
Write current does not flow through the second magnetization free layer,
The second magnetization free layer and the second magnetization fixed layer are made of a ferromagnetic material.
A semiconductor device according to claim 1,
The first magnetization free layer and the second magnetization free layer are provided in the same layer,
The first magnetization fixed layer and the second magnetization fixed layer are provided in different same layers.
A semiconductor device according to claim 1 or 2,
The first magnetization free layer comprises:
A first magnetization fixed region in which magnetization is fixed; a second magnetization fixed region in which magnetization is fixed; a magnetization free region connected to the first magnetization fixed region and the second magnetization fixed region and capable of reversing magnetization; Including
The first nonmagnetic layer is provided between the magnetization free region and the first magnetization fixed layer,
The semiconductor device, wherein the write current flows through the first magnetization fixed region, the magnetization free region, and the second magnetization fixed region.
A semiconductor device according to any one of claims 1 to 3,
The first magnetization fixed region is provided adjacent to one end of the magnetization free region;
The second magnetization fixed region is provided adjacent to the other end of the magnetization free region;
The semiconductor device, wherein the first magnetization fixed region, the second magnetization fixed region, and the magnetization free region form a substantially U-shape.
A semiconductor device according to claim 3,
The first magnetization fixed region is provided adjacent to one end of the magnetization free region;
The second magnetization fixed region is provided adjacent to the one end of the magnetization free region;
The semiconductor device, wherein the first magnetization fixed region, the second magnetization fixed region, and the magnetization free region form a substantially Y shape.
A semiconductor device according to claim 1 or 2,
In the first memory cell, the write current flows through the first magnetization free layer, the first nonmagnetic layer, and the first magnetization fixed layer.
A semiconductor device according to any one of claims 1 to 6,
The first magnetization fixed layer and the first magnetization free layer have one of in-plane magnetic anisotropy and perpendicular magnetic anisotropy.
A semiconductor device according to any one of claims 1 to 7,
In the second memory cell, a write current flows through the second magnetization fixed layer.
A semiconductor device according to any one of claims 1 to 7,
The second memory cell further includes a write wiring provided in the vicinity of the second magnetization free layer and through which a write current flows.
A semiconductor device according to any one of claims 1 to 7,
The second memory cell includes
A conductive layer provided on the opposite side of the second nonmagnetic layer across the second magnetization free layer;
A lower magnetization free layer provided on the opposite side of the second magnetization free layer across the conductive layer;
A semiconductor device in which a write current flows in the conductive layer.
A semiconductor device according to any one of claims 1 to 10,
In the first memory cell, the first nonmagnetic layer contains MgO.
A semiconductor device according to any one of claims 1 to 11,
In the first memory cell, at least one of the first magnetization free layer and the first magnetization fixed layer contains Co—Fe—B.