WO2009105282A1

WO2009105282A1 - Multiple interface memory with segmented i/o columns reconfigurable with respect to the interfaces

Info

Publication number: WO2009105282A1
Application number: PCT/US2009/001160
Authority: WO
Inventors: Frederick A. Ware; Venu Madhav Kuchibhotla
Original assignee: Rambus, Inc.
Priority date: 2008-02-20
Filing date: 2009-02-20
Publication date: 2009-08-27

Abstract

A memory (102) includes segmented I/O columns to provide access to data storage elements (105) in memory segments via multiple data I/O interfaces. A column segment control (107) in each column I/O path enables access to the data storage elements in a first mode by a first processor interface (108A). In a second mode, the column segment controls are used to partition the array and provide mutually exclusive access to subsets of the array to different interfaces (108A, 108B).

Description

MULTIPLE INTERFACE MEMORY WITH SEGMENTED I/O COLUMNS RECONFIGURABLE WITH RESPECT TO THE INTERFACES

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of Application Serial No. 61/066,337, filed February 20, 2008, entitled MULTIPLE INTERFACE MEMORY COMPONENT WITH SEGMENTED I/O COLUMNS, the disclosure of which is hereby incorporated herein by reference. BACKGROUND OF THE TECHNOLOGY

[0002] Memory devices are important components of digital systems. For example, digital information (e.g., software programs or user-specific electronic information) may be stored as data in the storage cells of a memory device. In random access memory ("RAM") devices, these storage cells are typically organized in rows and columns and may be randomly accessed by a processor via an interface of the memory component using particular row and column addresses of the storage cells. The storage cells may be arranged in banks, and different banks of such storage cells may be accessed with the further inclusion of bank address. When the processor is coupled to the RAM device via the interface, the processor may cause the digital information to be written to and/or read from the storage cells of the memory component as needed to perform the desired functions of the processor.

[0003] While typical digital systems have a single processor, in some digital systems it may be beneficial to provide more than one. For example, a "PDA" (Personal Digital Assistant) is a handheld computer system that provides communications functions and many other user data functions, such as storing schedules and contact information. In such systems, the operations may be divided between an applications processor and a communications processor. Both processors need memory to perform operations. It may be beneficial to provide a memory device that can efficiently maximize the use of the system for two or more processors . BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present technology is illustrated by way of example, and "not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements including:

[0005] FIG. 1 is an example memory component having memory segmenting technology;

[0006] FIG. IA is an example memory component of the present technology coupled with multiple processors;

[0007] FIG. 2 shows elements of the memory component of FIG. 1;

[0008] FIG. 3A, 3B and 3C illustrates various elements that may be implemented to form a column segment control unit;

[0009] FIGs. 4A, 4B and 4C illustrate various modes of a memory component implementing an embodiment of a column segment array;

[0010] FIGs. 5A, 5B, 5C and 5D illustrate various modes of an embodiment of a memory component implementing several column segment arrays ;

[0011] FIG. 6 shows an alternative embodiment of a column segment array implemented with elements of a memory component; and

[0012] FIG. 7A and 7B show several modes of operation of another memory component embodiment employing centric interfaces and boundary input-output ("I/O") interfaces with column segment arrays . DETAILED DESCRIPTION

[0013] A memory component 102 according to one example embodiment of the present technology is illustrated in Fig. 1. The memory component 102 will typically include a data storage element array 104, a column segment control array 106 and two or more input-output (I/O) interfaces 108. As will be described in more detail herein, the data storage array 104 will include a number of data storage elements 105, the column segment control array 106 will include a number of column segment control units 107 and each input-output interface 108 will include a number of column interface cells 109. In the illustrated embodiment, data storage array 104 is formed by one thousand and twenty four (1,024) data storage elements 105 in a 16 by 32 matrix on each half of the memory component 102. In addition, the column segment control array 106 is formed by thirty two (32) column segment control units 107 with half of the units on each half of the memory component 102. Finally, each input-output (I/O) interface 108A, 108B includes sixteen (16) column interface cells 109. Nevertheless, it will be understood that fewer or more such elements, units and cells may also be implemented. As will be discussed in more detail herein, each column interface cell 109 of each the I/O interface 108A, 108B may couple to one column of storage elements 105 for signal communication, or, as intended in the embodiment of FIG. 1, each such column interface cell 109 may so couple to two columns. However, in other embodiments, each such column interface cell 109 may be so coupled to more than two columns .

[0014] As further depicted in Fig. 1, memory component 102 includes two column segment control arrays, 106A and 106B, and two I/O interfaces, 108A and 108B. The data storage element array 104 of the memory component 102 may also be characterized by data storage element sub-arrays 104A, 104B, 104C and 104D. As illustrated in the embodiment of FIG. 1, each data storage element sub-array resides on a portion of the memory component 102. For example, data storage element sub-array 104A resides in an upper left quadrant of the memory component 102. Data storage element sub-array 104B resides in an upper right quadrant of the memory component 102. Data storage element sub-array 104C resides in a lower left quadrant of the memory component 102. Data storage element sub-array 104D resides in a lower right quadrant of the memory component 102. While four such sub-arrays in quadrants are illustrated in FIG. 1, it will be understood that other portioning of the data storage element array 104 into any number of sub-arrays may be implemented.

[0015] In addition, each data storage element sub-array 104A, 104B, 104C, 104D may be further characterized by banks 111 of data storage elements 105. As illustrated in FIG. 1, data storage element sub- array 104A is formed by four banks shown as banks HlA, HlB, lllC and HID. In this embodiment, each bank includes a 17 by 4 matrix of data storage elements 105. Similarly, remaining data storage element sub-arrays 104B, 104C and 104D may be formed by four banks. Although four banks are shown in each sub-array, additional numbers of banks may also be implemented.

[0016] As will be discussed in more detail herein, each data storage element 105 will typically include a matrix of memory cells and addressing control elements for selectively controlling read and write access to each particular cell of the data storage element 105. In the example embodiment, the data storage elements 105 are formed with dynamic random access memory cells. Moreover, each column segment control unit will typically include a series pass device such as one or more transistors and may form a switch circuit . Additional embodiments will be discussed in more detail herein with respect to FIGS. 3A, 3B and 3C. [0017] Each of the I/O interfaces 108A, 108B provides a connection for a processor, such as a digital processor, to obtain access to the data storage elements 105 of the memory component 102 via one or more common column I/O (not shown in FIG. 1) . Thus, each interface cell 109 will typically include an external contact or contact pad for coupling with an external data bus. Such connection is typically an electrical coupling between a processor and the plurality of interface cells. In the example configuration of the memory component of FIG. 1, each interface 108 is disposed with its interface cells adjacent to an edge or boundary to serve as external contacts that permit convenient connection with a coupling element of a processor. In this case, the I/O interfaces 108 are edge aligned on opposing sides of the memory component 102. Thus, the cells may be used by, for example, general -purpose processors (e.g., application processors) capable of running operating system software and application software, as well as special-purpose processors (e.g., baseband processors) capable of running specialized software such as DSP (digital signal processing) software. [0018] In one embodiment, the structure described above may be used to permit multi -modal operations where a processor communicates with the memory device using a data bus width of X. That is to say, in a first mode of such an embodiment, the processor may be use X signal lines of the data bus to communicate data with the entire memory array through I/O interface 108A. In a second mode of such an embodiment, the memory array may be partitioned, using the segment control devices, to permit the processor to use a data bus width of 2X and communicate data through both of I/O interfaces 108A and 108B, with the array effectively being automatically and electrically partitioned to half depth to accommodate a larger width of data array. An advantage of this structure is that the array may be partitioned, effectively in half in this example, without extra or unnecessary on-chip routing. Otherwise put, the effect of the segment control devices in this embodiment is to selectively partition the array but do so without appreciably increasing column length or the length of array routing. As discussed herein, the interfaces may also be used in a system where each interface 108A or 108B communicates with a different processor .

[0019] For example, I/O interface 108A includes a plurality of interface cells 109 and I/O interface 108B includes a plurality of interface cells 109. While the processor may be coupled to I/O interface 108A by a connection with one or more of interface cells 109 of I/O interface 108A, in a typical embodiment, the processor will be coupled to I/O interface 108A via all of the interface cells 109 of I/O interface 108A. Similarly, another processor may be coupled to the I/O interface 108B by connection with one, more or all of the interface cells 109 of I/O interface 108B. In some embodiments, each I/O interface can permit parallel signaling with respect to the data storage elements coupled with the I/O interface.

[0020] For example, in a communications device an applications processor may be coupled with I/O interface 108A for accessing the memory cells of the memory component 102 and a baseband processor may be coupled with I/O interface 108B for accessing the memory cells of the memory component 102. Such an embodiment is illustrated in FIG. IA. Although not shown, the access by the processor with the I/O interface in some embodiments may optionally be made via a memory controller that communicates with or is under control of the processor (s) .

[0021] Each interface cell 109 will typically be coupled with a column I/O. The column I/O may be a signal path coupled with a collection of data storage elements 105 of the memory component 102. It will be typical for each column I/O to be coupled with an interface cell 109 of I/O interface 108A and also an interface cell 109 of I/O interface 108B. Thus, a first processor coupled with an interface cell 109 of I/O interface 108A may read and write data of particular data storage elements 105 coupled with a particular column I/O. Furthermore, a second processor coupled with an interface cell 109 of I/O interface 108B may read and write data of those particular data storage elements 105 from that same particular column I/O.

[0022] As shown in FIG. 1, the column segment array 106A may segment the plurality of data storage elements into a first group of data storage elements 105 in data storage element sub-array 104A and a second group of data storage elements 105in data storage element sub-array 104B. The column segment array 106B also divides a first group of data storage elements 105 in data storage element sub-array 104C and a second group of data storage elements 105 in data storage element sub-array 104D. For this purpose, each column segment array 106A, 106B will typically include at least one column segment control unit 107 implemented along a column I/O of the memory component that is common to each I/O interface 108A, 108B.

[0023] Each column segment control unit 107 is operable to limit access to a particular group of data storage elements by segmenting a column input -output of the memory component to couple and uncouple those elements from and to the interfaces in a symmetrical fashion. For example, access to a part of a first group of data storage elements 105 in data storage element sub- array 104C by second I/O interface 108B may be permitted by enabling a particular column segment control unit 107 of column segment control array 106B. Moreover, access to a part of a second group of data storage elements 105 in data storage element sub-array 104D by first I/O interface 108A may be permitted by enabling the same column segment control unit 107 in column segment control array 106B. Similarly, access to a part of a first group of data storage elements 105 in data storage element sub-array 104C by second I/O interface 108B may be refused by disabling a same column segment control unit 107. Moreover, access to a part of a second group of data storage elements 107 in data storage element sub-array 104D by first I/O interface 108A may be refused by disabling the same column segment control unit 107 of column segment control array 106B. Furthermore, due to its nature and location, the column segment control array 106B would not disable access to any of the first group of data storage elements 105 in data storage element sub-array 104C by first I/O interface 108A even though it is along the column I/O. Similarly, the column segment control array 106B would not disable access to any parts of the second group of data storage elements 105 of data storage element sub-array 104D by second I/O interface 108B.

[0024] FIG. 2 further illustrates an arrangement of the circuit elements of the example memory component 102 of FIG. 1. In this embodiment, data storage element 205 includes a storage cell array 210 with storage cells (each shown as block C) , a row decode block 214, a sense amplifier and column decode block 212 and an access control block 216. Each cell C may include a memory cell such as a dynamic random access memory cell that may include a transistor and capacitor configured to store data. Alternatively, other types of memory cells may also be implemented in each cell C. The row decode block may include logic circuits for activating a particular row of cells of the data storage element 205 for read or write access based on row control signals from the row addressing circuit 218 of the access control block 216. Sense amplifiers (shown as SA) coupled with column decode logic permit sensing of a particular column of cells under the control of column address signals from column addressing circuit 220 of the access control block 216. The access control block may also include an equalization/selection VPs/Vns circuit 220 to control the sense amplifiers (SA) of the sense amplifier and column decode block 212. The column addressing circuit 220 may also include logic circuits for controlling the output of the sense amplifier and column decode block 212 to activate or deactivate the output of the data storage with the column I/O.

[0025] In this embodiment, the access control block 216 optionally includes a column segment control unit 207 to form a part of a column segment control array of the memory component. In this way, several data storage elements 205 with access control blocks having column segment control units can form a column segment control array. Such a data storage element 105 having a column segment control unit is generally shown in FIG. 1 as the data storage elements that form a part of the column segment control arrays 106A, 106B. However, a memory component of the present technology may also include other data storage elements with access control blocks that do not have the column segment control units. For example, such a data storage element 105 is shown as data storage elements that form a part of bank HlA of data storage element sub-array 104A in FIG. 1. These later types of data storage elements would not form part of a column segment control array. Thus, in certain embodiments, a column of data storage elements (e.g., a column of 32 data storage elements 105) may only have one or a few data storage elements (e.g., 1, 2, 3 or even more in various embodiments) that include a column segment control unit 207 while the remaining data storage elements 105 do not have such a column segment control unit 207. However, in still further embodiments as will be explained in more detail herein at least with respect to FIG. 6, the data storage elements of a column may include no column segment control unit 207. In such embodiments, one or more column segment control units (e.g., 1, 2, 3 or more in various embodiments) that are associated with the particular column may be implemented separately by special mats with such devices in between distinct groups of data storage elements that share a column I/O.

[0026] In this embodiment of FIG. 2, the column segment control unit 207 is a series pass device on a differential signal column I/O. The column segment control unit 207 is located on a column I/O that is common to more than one interface, in this case I/O interface cells 209A and 209B. For example, I/O interface cell 209A may form a part of I/O interface 108A of FIG. 1 and I/O interface cell 209B may form a part of I/O interface 108B of FIG. 1. The column segment control unit 207 may be formed by two transistors and controlled by a common enable signal that is coupled to the gates of the transistors of the series pass device. The series pass device permits a data signal from the storage cells and the sense amplifiers and column decode block to pass along the column I/O to a second I/O interface cell 209B at a second interface end 224B of the column I/O when it is enabled by setting the enable signal high. When it is disabled by setting the enable signal low, the series pass device prevents access to the storage cells C of storage element 205 by the second I/O interface cell 209B. Similarly, the column segment control unit 207 would permit or deny access by the second I/O interface cell 209B to other data storage elements (not shown in FIG. 2) that would be coupled to the column I/O at a first interface end 224A of the column I/O. The column segment control unit 207 would permit or deny access by the first I/O interface cell 209A to other data storage elements (not shown in FIG. 2) that would be coupled to the column I/O at a second interface end 224B of the column I/O (e.g., on the opposite side of the column segment control unit 207 of the first I/O interface cell.) [0027] As evident from its position along the column I/O, the column segment control unit 207 cannot enable or disable access to the storage cells of the data storage element 205 by a first interface end 224A of the column I/O. Thus, first I/O interface cell 209A may access data storage element 205 regardless of the setting of column segment control unit 207. Similarly, the column segment control 209A could not permit or deny access by the first I/O interface cell 209A to other data storage elements coupled to the column I/O at a first interface end 224A of the column I/O. Likewise, the column segment control 207 could not permit or deny access by the second I/O interface cell 209B to other data storage elements coupled to the column I/O at a second interface end 224B of the column I/O.

[0028] In this embodiment, the I/O interface cells 209A, 209B are both implemented respectively with equalization elements 226A, 226B and column amplification elements 228A, 228B. These elements permit reception/transmission of data along the column I/O for reading and writing access to the data storage elements of the column I/O.

[0029] FIGS. 3A, 3B and 3C illustrate some suitable embodiments for the series pass device of the column segment control units of the present technology. FIG. 3A shows an N-type dual transistor example of a column segment control unit 307 like the one discussed with respect to the differential signaling column I/O of FIG. 2. The embodiment employs two transistors controlled by an enable signal at its gate to pass the data signal of the column I/O. This dual transistor embodiment may be implemented for differential signaling using differential signal transmitters and receivers on the ends of the column I/O. However, if the column I/O was not of a differential type such that it only required a single data signal to transmit a data bit to and from the data storage element, then only one of the transistors need be implemented for the series pass device of the column segment control unit .

[0030] The series pass device of FIG. 3B may also be implemented as a column segment control unit 307 of the present technology. Like the embodiment shown in FIG. 3A, this version may be implemented for differential signaling along the column I/O. However, the transistors of the present embodiment are formed as a CMOS type series pass device. When the enable signal is high, the transistors permit data signals to traverse the column I/O in either direction (indicated by arrows of FIG. 3B) .

[0031] Unlike the passive versions shown in FIGs. 3A and 3B, the bidirectional buffer device of FIG. 3C is an active device that may serve as the column segment control unit 307. The control logic of the bidirectional buffer device may be driven with an enable signal and a directional down signal to control the device. When the enable signal is high, data of the column I/O may pass through the device. The down signal is implemented depending on whether a read or write operation is being made and depending on which interface is attempting to access a particular data storage element via the column segment control unit 307. In this embodiment, the column segment control unit is not implemented for differential signaling. However, it may be modified to do so by adding two additional buffers for the additional signal line of a differential signal path. The additional amplifiers may be controlled by the same control logic as those shown in FIG. 3C. Although the control logic for the bidirectional buffer is illustrated with a NAND gate and an AND gate in the embodiment of FIG. 3C, it will be understood that other gate combinations may be implemented for the control of the bidirectional buffer(s) .

[0032] Segmenting of the data storage elements of the memory component utilizing a single column segment control array 406A, 406B in various modes is illustrated in FIGs. 4A, 4B and 4C. These figures depict a memory component with data storage elements 405 configured in sixteen banks. Fewer or more such banks may be implemented. In FIG. 4A, the example memory component includes I/O interfaces A, B, C, and D. When the column segment control array 406B is disabled, banks 0-3 are only accessible to interface A and banks 4-7 are only accessible to interface B. Accesses to these banks by each interface may be performed simultaneously. Optionally, the column segment control array 406A associated with banks 8-15 may operate dependentIy with column segment control array 406B. However, it may also be operated independently. Similarly, banks 0-7 and banks 8-15 may be operated dependentIy or independently.

[0033] In FIGs. 4B and 4C, the column segment control array 406B is enabled. While it is enabled, only one of interfaces A or interface C may access banks 0-7. In FIG. 4B only interface A accesses banks 0-7 and the interface B remains idle or unused. In FIG. 4B only interface B accesses banks 0-7 and the interface A remains idle or unused. Thus, 4B and 4C illustrate an allocation of all of the memory to either the top interface A or the lower interface B, depending on the activation of the column segment control array. Moreover, while the memory component embodiment of FIG. 4A illustrates the potential for division of half of the memory between each interface (50% and 50%) (e.g., a column segment control array at a midpoint of the banks of the memory component) depending on the activation of the column segment control array, the column segment control array may be formed in a different location to segment the memory by a different allocation. For example, the column segment control array may be located to allocate the memory to interface A by 25% and interface B by 75%. Other allocations may also be implemented as desired depending on the placement of the column segment control array (s) .

[0034] Furthermore, multiple column segment control arrays may be implemented in a memory component to provide more flexible segmenting of the data storage elements between multiple interfaces. An example of an implementation of multiple column segment control arrays is shown in FIGs. 5A, 5B, 5C and 5D . In the memory component embodiment of these figures, three column segment control arrays are implemented between two interfaces. Column segment control arrays 506B-A, 506B-B, 506B-C are formed as part of data storage elements of bank 1, bank 3 and bank 5. The column segment control arrays may be similarly formed for the segmenting of the data storage elements of interfaces C and D. However, they may also be formed to differently segment the data storage elements for interfaces C and D. [0035] With these three column segment control arrays in the example memory component, the data storage elements may be allocated into four segments, each with two banks of memory. The memory component may then have various modes of operation. As illustrated in FIG. 5A, when all of the column segment control arrays are enabled, one or the other of interface A and interface B may be used to access the data storage elements of banks 0-7. FIG. 5B illustrates a mode where a first and third column segment control arrays (i.e., 506B-A and 506B-C) are enabled and a middle or second column segment control array (i.e., 506B-B) is disabled. In this mode, interface A may be used to access the data storage elements of banks 0-3 and interface B may be used to access the data storage elements of banks 4-7. This access may be simultaneous.

[0036] In another mode of operation shown in FIG. 5C, the first column segment control array 506B-A is disabled while the remaining two column segment control arrays 506B-B and 506B-C are enabled. This permits interface A to access data storage elements of banks 0-1. It also permits interface B to access data storage elements of banks 2-7.

[0037] Similarly, in the mode of operation shown in FIG. 5D, the first and second column segment control arrays (i.e., 506B-A and 506B-B) are enabled while the remaining column segment control array 506B-C is disabled. This permits interface A to access data storage elements of banks 0-5. It also permits interface B to access data storage elements of banks 6-7.

[0038] By controlling the column segment control arrays to only the simultaneous enable/disable states indicated in the modes of FIGs. 5B through 5D, the memory component may provide multiple interface access to a common portion of the data storage elements of the memory component and exclusive single interface access to certain other data storage elements for each interface. Thus, the modes may ensure that each interface will have a minimum exclusive data storage region for operation and additional memory as necessary. [0039] These modes and the setting of the column segment control arrays associated therewith may be performed at system set up and may be statically maintained. Alternatively, these arrays may be dynamically controlled by a further system process to dynamically segment the memory during operation depending on the needs of the processors using the interfaces. For example, a segment regulator (not shown) formed by hardware logic and/or software may control the setting of the column segment control arrays. For example, in addition to the bank, row and column address used by a processor via one of the interfaces to access a certain data storage element of the memory component, a segment control bit may be added to the memory addressing scheme. The additional segment control bit (in the example case of the memory component of FIGs. 4A-4C) or bits (in the example case of the memory component of FIGs. 5A-5D) may be supplied by each processor on each interface for access to a particular storage cell depending on the particular segment, bank, column and row supplied. The address may be supplied by a processor to the access control block and logic circuits of a segment regulator that control the column segment control units. Additional hardware and/or software may control the availability of addresses for commonly accessed memory areas by more than one processor to avoid conflicts given the potential for simultaneous accesses to a potential memory location by more than one processor. In another embodiment, the column segment control units of the column segment control arrays may be set via special memory registers (not shown) (e.g., latches or flip-flops) that control the state of the column segment control units. These memory registers may be set for a particular data operation or they may be set as part of a set up configuration operation for several or all data operations .

[0040] Another embodiment of a configuration of the column segment control units of the present technology is illustrated in a memory component of FIG. 6. The memory component of FIG. 6 is similar to the memory component of FIG. 2. Thus, the memory component will have I/O interface cells 609A, 609B connected by column I/O at a first column I/O end 624A and second column I/O end 624B like that of FIG. 2. The memory component will also have data storage elements 605. Each data storage element will also include a storage cell array 610, row decode block 614, sense amplifiers and column decode block 612 and access control block 616. In this embodiment, the data storage elements 605 do not directly include column segment control units.

[0041] The memory component of FIG. 6 will also have one or more column segment controls units 607 to form a column segment control array. However, in FIG. 6, the column segment control unit 607 is not formed as part of the access control block of the data storage element. Rather, in FIG. 6, an additional mat of series pass devices along the column I/O lines will be implemented to form the column segment control array 606. Thus, conventional data storage elements may be implemented and may be added to the column segment control arrays to implement the present technology and may implement the operating modes illustrated in FIGs. 4A-4C and FIGs. 5A- 5D .

[0042] FIGS. 7A and 7B illustrate an alternative embodiment of a memory component 702 of the present column segment control technology. In this embodiment, the memory components, data storage elements, I/O interfaces, column segment control units, and column segment control arrays are formed and function like the elements of the embodiments of FIGs. 2 or 6. However, in this embodiment, the memory component includes additional I/O interfaces and interface cells. In addition to interfaces (shown as interfaces C and D) which are like the I/O interfaces of FIG. 2, FIGs. 4 (A-C) and/or 5 (A-D) and which are adjacent to the opposing boundaries of the memory component, additional I/O interfaces (shown as interfaces A and B) are provided. These additional interfaces are implemented in a central fashion such as being disposed along a center line between the opposing interfaces C and D which are adjacent to the memory component edges. These centrally disposed interfaces may be referred to as centric interfaces and are shown as interfaces A and B) . These centric interfaces are typically disposed centrally between memory storage elements. In this embodiment, interfaces A and C may selectively access the data storage elements of banks 0-3 while interfaces B and D may selectively access the data storage elements of banks 4-7. In operation, column segment control array 706B-A may control modes of operation to segment the data storage elements of banks 0-3 between interfaces A and C. Similarly, column segment control array 706B-B may control . modes of operation to segment the data storage elements of banks 4-7 between interfaces B and D.

[0043] For example, as shown in FIG. 7A, by enabling both column segment control arrays 706B-A, either of the processors coupled to the centric I/O interfaces (e.g., interfaces A or B) or the I/O interfaces at the edge boundary (e.g., interfaces C or D) may be used. For example, as illustrated, interface C may be unused or idle while interface A accesses banks 0-3. Moreover, interface D may be unused or idle while interface B accesses banks 4-7. These accesses to banks 0-3 and banks 4-7 by interfaces A and B may be simultaneous.

[0044] As illustrated in FIG. 7B, the column segment control units may also implement a mode of simultaneous access to data storage elements by four interfaces A, B, C and D. As shown in FIG. 7B the column segment control arrays 706B-A, 706B-B are both disabled. Thus, interface C may access the data storage elements of banks 0-1, interface A may access the data storage elements of banks 2-3, interface B may access the data storage elements of banks 4-5 and interface D may access the data storage elements of banks 6-7. Thus, in this embodiment at least four processors may access data storage elements of the memory component simultaneously. A comparable operation may be implemented with banks 8-15 using interfaces E, F, G and H to yield additional access to the memory component with as few as two processors and as many as eight processors. In other words, they may then jointly utilize the storage capacity of the memory component. Other modes of operation are also possible by varying the coupling/uncoupling states of the column segment control arrays and the use of the banks by their respective interfaces. [0045] In general, each of the circuits implemented in the I/O column segmenting technology presented herein may be constructed with electrical elements such as traces, capacitors, resistors, transistors, etc. that are based on metal oxide semiconductor (MOS) technology, but may also be implemented using other technology such as bipolar technology or any other technology in which a signal -controlled current flow may be achieved. [0046] Furthermore, these circuits may be constructed using automated systems that fabricate integrated circuits. For example, the components and systems described may be designed as one or more integrated circuits, or a portion (s) of an integrated circuit, based on design control instructions for doing so with circuit -forming apparatus that controls the fabrication of the blocks of the integrated circuits. The instructions may be in the form of data stored in, for example, a computer-readable medium such as a magnetic tape or an optical or magnetic disk. The design control instructions typically encode data structures or other information describing the circuitry that can be physically created as the blocks of the integrated circuits. Although any appropriate format may be used for such encoding, such data structures are commonly written in Caltech Intermediate Format (CIF) , Calma GDS II Stream Format (GDSII) , or Electronic Design Interchange Format (EDIF) . Those of skill in the art of integrated circuit design can develop such data structures from schematic diagrams of the type detailed above and the corresponding descriptions and encode the data structures on computer readable medium. Those of skill in the art of integrated circuit fabrication can then use such encoded data to fabricate integrated circuits comprising one or more of the circuits described herein.

[0047] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present technology. In some instances, the terminology and symbols may imply specific details that are not required to practice the technology. For example, although the terms "first" and "second" have been used herein, unless otherwise specified, the language is not intended to provide any specified order but merely to assist in explaining elements of the technology.

[0048] Moreover, although the technology herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the technology. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the technology. For example, the memory components may be implemented as static random access memory or any other random access memory and may be configured for use in portable communications digital systems or any other type of digital system the may benefit from multiple processor access to a memory component .

Claims

CLAIMS :

1. A memory device, comprising: a plurality of data storage cells; a column input -output (10) path coupled with the data storage cells, the column IO path having a length; a first data interface coupled to the column IO path to communicate input data and output data between the path and an external data bus,- a second data interface coupled to the column IO path to communicate input data and output data between the path and an external data bus; and a switch in the column 10 path between the first data interface and the second data interface; where the memory device has a first mode, in which the switch couples the first data interface with the entire length of the column IO path, and a second mode in which the switch isolates the first data interface from at least part of the length of the column IO path.

2. The memory device of claim 1, where: the data storage cells are distributed along the length of the column 10 path; and the switch is positioned along the length of the column 10 path to

(i) in the first mode, electrically couple all of the data storage cells along the length with the first interface, and

(ii) in the second mode, partition the data storage cells such that some of the data storage cells are coupled with the first interface and the remaining data storage cells are coupled with the second interface and are isolated from the first interface.

3. The memory device of claim 1, further comprising an externally-programmable register to store a mode setting, the register to control the switch.

4. The memory device of claim 3, where the register is dynamically programmable.

5. The memory device of claim 1, further comprising an array of data storage cells arranged in rows and columns, where: each column has an associated data IO path (i) with a substantially common length, (ii) coupled between the first data interface and the second data interface, (iii) with number plurality of data storage cells, and (iv) with a switch along the associated length to selectively segment the associated data IO path; and the switches operated as a group to selectively couple all data storage cells in the array with the first data interface, and to selectively partition half of the array to couple one half of the array of data storage cells to the first data interface and a second half of the array of data storage cells to the second data interface.

6. The memory device of claim 1, where the first interface and second interface each comprise an edge aligned interface.

7. The memory device of claim 1, where the switch is a bidirectional switch.

8. The memory device of claim 1, where the switch includes an amplifier.

9. The memory device of claim 1, where the plurality of data storage cells are coupled to one of the first data interface or the second data interface irrespective of the mode.

10. The memory device of claim 1, further comprising a plurality of switches disposed along the length and a register, where (i) in the first mode, the plurality of switches couple the at least one of the first data interface or second data interface with entire length of the column IO path, (ii) in the second mode, the plurality of switches isolates the at least one of the first data interface or second data interface from at least part of the entire length of the column IO path, and (iii) where the switches are responsive to register contents to vary size of the at least part of the entire length isolated from the first data interface in the second mode .

11. A memory device, comprising: an array of data storage cells, the array having a plurality of column IO paths, each column IO path having a length; two data 10 interfaces, each adapted to couple an external data bus with the plurality of column 10 paths at opposite ends of the length of each column 10 path; and a switch at the logical middle each 10 path and adapted to partition the array into two subdivisions of approximately equal size; where the memory device has a first mode, in which the data bus uses one of the data interfaces to communicate with the array using a word length of X and an array depth of D, and a second mode, in which the data bus uses both data interfaces to communicate with the array using a word length of 2X and an array depth of D/2.

12. An apparatus comprising data stored on machine-readable media, the data forming a circuit description adapted to be used in the automated fabrication of an integrated circuit memory device, the circuit description encompassing a memory device characterized by: an array of data storage cells, the array having a plurality of column 10 paths, each column 10 path having a length; two data 10 interfaces, each adapted to couple an external data bus with the plurality of column 10 paths at opposite ends of the length of each column 10 path; and a switch at the logical middle each IO path and adapted to partition the array into two subdivisions of approximately equal size; where the memory device has a first mode, in which the data bus uses one of the data interfaces to communicate with the array using a word length of X and an array depth of D, and a second mode, in which the data bus uses both data interfaces to communicate with the array using a word length of 2X and an array depth of D/2.

13. A method comprising: providing a memory component with data storage cells, the memory component having a first interface and a second interface, each interface coupled to a column input -output (I/O) to input and output data, the data storage cells logically partitioned into two segments; controlling the memory component to implement access (i) in a first mode, by the first interface to each of the two segments, and (ii) in a second mode, by the first interface to one of the two segments and by the second interface to the other of the two segments .

14. The method of claim 13, in which each of the segments are identical in logical size.

15. The method of claim 13, where controlling the memory component includes dynamically controlling the memory component during run- time of the memory component.

16. The method of claim 13, further comprising disabling access by the second interface to either of the two segments during the first mode.

17. The method of claim 13, further comprising disabling access by the first interface to one of the segments during the second mode .

18. The method of claim 13, where the memory component includes an integrated circuit memory device adapted to communicate with an external data bus and where each interface is to couple to an equal number of mutually-exclusive data bus input-output (10) pins with different portions of the data^' bus, the method further comprising: in the first mode adapting the integrated circuit memory device to interact with the data bus using a word length of X, via the first interface only; and in the second mode adapting the integrated circuit memory device to interact with the data bus using a word length of 2X, via concurrent use of both the first interface and the second interface to communicate with the data bus .

19. The method of claim 18, further comprising determining mode according to a register setting of the integrated circuit memory device.

20. The method of claim 13, where controlling the memory component to implement access in the first and second modes includes implementing access without changing column input-output (10) length, such that in the first mode, access by the first interface to each of the two segments is routed through the column IO length, and such that in the second mode, access by the first interface and by the second interface are partitioned within the column IO length.

21. An integrated circuit, comprising: an I/O path; a plurality of data storage cells coupled to the I/O path, the plurality including a first set of data storage cells and a second set of data storage cells; a first interface coupled with the I/O path; and a second interface coupled with the I/O path; the integrated circuit having a first state to couple each of the first set of data storage cells with the first interface and the second set of data storage cells with the first interface, and a second state to partition the sets of data storage cells and to decouple the second set of data storage cells from the first interface.

22. The integrated circuit of claim 21, where in the first state the second interface is also coupled with each of the first set of data storage cells and the second set of data storage cells, and where in the second state, the second interface is decoupled from the first set of data storage cells.

23. The integrated circuit of claim 21, where in the first state the second interface is decoupled from both of the first set of data storage cells and the second set of data storage cells .

24. The integrated circuit of claim 21, where external contacts of the first interface and the second interface are edge aligned on the integrated circuit.

25. The integrated circuit of claim 21, where the plurality of data storage cells comprise dynamic random access memory cells .