WO2009095812A1 - Systèmes d'exploitation doubles fonctionnant sur un unique processeur - Google Patents

Systèmes d'exploitation doubles fonctionnant sur un unique processeur Download PDF

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Publication number
WO2009095812A1
WO2009095812A1 PCT/IB2009/050196 IB2009050196W WO2009095812A1 WO 2009095812 A1 WO2009095812 A1 WO 2009095812A1 IB 2009050196 W IB2009050196 W IB 2009050196W WO 2009095812 A1 WO2009095812 A1 WO 2009095812A1
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WO
WIPO (PCT)
Prior art keywords
operating system
real
type
interrupt signal
time operating
Prior art date
Application number
PCT/IB2009/050196
Other languages
English (en)
Inventor
Arnaud C. B. Troel
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2009095812A1 publication Critical patent/WO2009095812A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45537—Provision of facilities of other operating environments, e.g. WINE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Definitions

  • the invention relates to a processing system for executing alternately a real-time operating system and a non-real-time operating system, and to a method of operating such a processing system.
  • Communication devices such as mobile phones, have an increasing number of features embedded in them which are provided by software, with the result that the software is becoming increasingly complex.
  • proprietary dedicated real-time operating systems have been developed by manufacturers of such devices.
  • General-purpose operating systems may be able to handle the software more easily than proprietary dedicated real-time operating systems.
  • the proprietary private real-time operating systems continue to be used for two particular reasons. First, it is time- consuming and expensive to re-develop legacy software, such as communication stacks. Second, is the need to maintain security; nesting security features and related data in a proprietary operating system contributes to ensuring secure software.
  • RTOS real-time operating system
  • GPOS general-purpose operating system
  • Figure 1 depicts, in a general manner, such a dual-OS mono-core architecture, where a RTOS and a GPOS communicate with each other using a shared memory controlled by dedicated signals. This approach is the so-called para-virtualisation. For the sake of efficiency, not all the hardware has been virtualised in Figure 1 , only mandatory parts.
  • Figure 2 depicts the system of Figure 1 in more detail, based on a virtualized memory and a virtualized interrupt controller.
  • Data is stored in a shared memory and control is provided by cross-interrupt signals, for example software interrupt signals raised from one operating system to the other.
  • Hardware related interrupt signals are distributed to one operating system or the other, generally in a static manner. This system can be considered to be equivalent to nesting the GPOS inside the RTOS.
  • the majority of the boxes in Figure 2 denote software that is the same for dual-OS operation as for the operation of a single operating system.
  • the inter-OS device drivers interfaces have been added, as has the virtualized interrupt controller.
  • software for managing the shared memory is included for dual-OS operation and the GPOS interrupt controller is adapted.
  • Figure 3 shows, in a corresponding manner, another dual-OS mono- core system in which the RTOS is nested inside the GPOS. Interrupt signals, both hardware and software related, are forwarded to the RTOS using GPOS signals and data are stored in a shared memory.
  • the majority of the boxes in Figure 3 denote software that is the same for dual-OS operation as for the operation of a single operating system.
  • the high priority RTOS legacy task requires an adapter to be added, the interrupt framework requires to be adapted, and a bridge is provided to the RTOS interrupt framework.
  • the interconnections labelled "IT" indicate the path of interrupt signals
  • those labelled "sig” indicate the path of data signals
  • those labelled “mem” indicate the path of signals for controlling the shared memory.
  • both of operating systems exchange data across a shared memory controlled by signals. As soon as one operating system wants to send information to the other one, it first writes related data in a shared memory buffer and then sends a signal to inform the other operating system of the presence of that data in the shared memory buffer.
  • the RTOS To meet the real-time deadlines of the RTOS, the RTOS must be able to acquire the use of the processor as soon as it needs to. This has the following two consequences:
  • the RTOS must automatically re-gain the processor whatever the GPOS is doing.
  • GPOS is only activated when the RTOS has completed its execution, that is when the RTOS scheduler reaches an idle loop.
  • the RTOS in order to ensure good quality audio, the RTOS must maintain audio frame timing, and the GPOS must supply the RTOS with audio samples, so it is important that the related signals are handled in a synchronous manner.
  • system switch The cost of switching from one operating system to another, which is known as system switch, depends on the underlying hardware platform and on the operation of the operating systems. If one operating system acts as a trusted zone for security purposes, processor caches must be flushed at each switch, which can severely reduce performance. Conversely, if caches can be preserved, a system switch is less expensive, but can still reduce performance if executed too many times. As a result, signal storms must be avoided so as not to scatter runtimes.
  • a communication stack is typically executed by the RTOS and is connected with the GPOS through several AT command channels, AT commands being a type of command standardised in the UMTS standard.
  • the sending of an AT command can wait until the execution of the GPOS is completed, that is until the GPOS reaches an idle loop, before restarting the RTOS.
  • FIG. 4 The runtime scattering in such a system is depicted in Figure 4.
  • a GPOS comprising man-machine interface (MMI) software, three AT command channels and an audio driver.
  • MMI man-machine interface
  • the audio driver loads an audio sample into shared memory, then an interrupt signal is passed to the RTOS which uses the audio sample in the shared memory to update a digital signal processor (DSP).
  • DSP digital signal processor
  • the MMI software is executed, and then AT channel number 3 sends an AT command, with an interrupt signal to the RTOS, following which the RTOS executes that command.
  • the MMI software is executed again, and then AT channel number 1 sends an IP packet, with an interrupt signal to the RTOS, following which the RTOS executes the IP packet.
  • the present invention seeks to provide improved operation of such operating systems.
  • a method of operating a processing system having a processor for executing in turn a real-time operating system and a non-real-time operating system comprising: executing a non-real-time operating system; the non-real-time operating system generating an interrupt signal signifying a pending task requiring execution by a real-time operating system; categorising the interrupt signal as a first type or a second type; storing interrupt signals of the first type in a storage means; in response to the generation of an interrupt signal of the second type, ceasing execution of the non-real-time operating system and commencing execution by the real-time operating system of the task signified by the interrupt signal of the second type and any pending tasks signified by stored interrupt signals of the first type before resuming execution of the non-realtime operating system.
  • a processing system for executing in turn a real-time operating system and a non-real-time operating system
  • the processing system comprising: a processor for executing alternately a real-time operating system and a non- real-time operating system; wherein the non-real-time operating system is adapted to, during execution, generate an interrupt signal signifying a pending task requiring execution by the real-time operating system, and is further adapted to categorise the interrupt signal as a first type or a second type; a store for storing interrupt signals of the first type; a controller adapted to, in response to the generation of an interrupt signal of the second type, inhibit execution of the non-real-time operating system, enable execution by the real-time operating system of the task signified by the interrupt signal of the second type and any pending tasks signified by stored interrupt signals of the first type, and, after completion of the task or tasks, enable execution of the non-real-time operating system.
  • interrupt signals generated by a non- real-time operating system that indicate a task to be performed by a real-time operating system are categorised into one of two types.
  • a task indicated by an interrupt signal of the first type need not be executed immediately, but that interrupt signal is stored for later execution of the task.
  • a task indicated by an interrupt signal of the second type is executed immediately by the real-time operating system, and also the tasks indicated by any stored interrupt signals of the second type are executed.
  • interrupt signals of the first type are referred to as "delayed" interrupt signals
  • interrupt signals of the second type are referred to a "immediate" interrupt signals.
  • the invention therefore, provides a way of reducing the amount of switching between operating systems, thereby reducing the overhead and inefficiency of switching between operating systems.
  • execution of the non-real-time operating system ceases and the real-time operating system executes the pending task signified by the stored interrupt signal of the first type. This can prevent starvation of the pending task signified by stored interrupt signal of the first type.
  • the period of time is measured from the generation of the most recent interrupt signal of the second type, or is measured from the storage of the oldest stored interrupt signal of the first type.
  • This provides a simple scheme in which the period of time can be determined by, for example, a timer or counter.
  • the period of time is determined by a scheduler. This provides flexibility to coordinate the period of time with other pending tasks.
  • the invention also provides computer program code adapted to carry out the method according to the first aspect of the invention.
  • Figure 1 depicts two operating systems sharing a single processor core in accordance with the prior art
  • Figure 2 depicts two operating systems sharing a single processor core based on virtualised memory and an interrupt controller in accordance with the prior art
  • Figure 3 depicts two operating systems sharing a single processor core based on nesting a real-time operating system in a non-real-time operating system in accordance with the prior art
  • FIG. 4 depicts the system switches required by the prior art
  • FIG. 5 depicts the system switches required by an embodiment of the invention
  • Figure 6 is a flow chart illustrating a method of operating a processing system
  • Figure 7 depicts an architecture of a processing system
  • Figure 8 is a schematic block diagram of a processing system
  • Figure 9 is a block schematic diagram of a wireless device.
  • Figure 5 illustrates the systems switches which take place between operating systems in an embodiment of the invention, for executing the same tasks as illustrated in Figure 4 according to the prior art.
  • a GPOS comprising, man-machine interface (MMI) software, three AT command channels and an audio driver, and also a Trigger routine.
  • MMI man-machine interface
  • the audio driver loads an audio sample into shared memory, then generates an interrupt signal.
  • This interrupt signal is designated as the "immediate” type and therefore is passed immediately to the RTOS which uses the audio sample in the shared memory to update a digital signal processor (DSP).
  • DSP digital signal processor
  • AT channel number 3 generates an AT command with an interrupt signal which is designated as the "delayed” type and therefore is stored into memory, following which the MMI software is executed again.
  • AT channel number 1 generates an IP packet with an interrupt signal which is designated as the "delayed” type and therefore is stored into memory, following which the MMI software is executed again.
  • AT channel number 2 generates an AT command and interrupt signal which is designated as the "delayed” type and therefore is stored into memory, following which the MMI software is executed again.
  • the storing of further delayed interrupt signals will continue in the same manner until the GPOS generates an interrupt signal which is designated as the "immediate” type, and at that time execution of the GPOS ceases and the RTOS executes the task indicated by the immediate interrupt signal and the pending tasks indicated by the stored delayed interrupts. After that, execution of the GPOS resumes. In this way, the amount of switching between the operating systems is reduced, compared with the prior art scheme illustrated in Figure 4.
  • the Trigger routine is optional. If present, the Trigger routine can initiate an "immediate" interrupt signal, and as a result execution of the GPOS ceases and the RTOS executes the pending tasks indicated by the delayed interrupt signal which are stored in the memory, namely the AT commands generated by AT channels number 2 and 3, and the IP packet. Following execution of these tasks, execution of the RTOS ceases and execution of the GPOS resumes.
  • the Trigger routine may comprise a timer for initiating the immediate interrupt signal. This may occur, for example, when a predetermined or dynamically chosen period of time has elapsed since the previous execution of pending delayed tasks, or since the previous execution of an immediate interrupt signal. Alternatively, the timer may initiate the immediate interrupt signal when a predetermined or dynamically chosen period of time has elapsed since the oldest stored delayed interrupt signal was stored in the shared memory. Other timing criteria may be used. Thus the Trigger routine can prevent starvation of the pending tasks corresponding to the stored delayed interrupt signals.
  • the Trigger routine may comprise a scheduler for constraining the initiation of the immediate interrupt signal to occur at a convenient time dependent on what other tasks are pending or currently being executed. This can ensure, for example, that disruption to such tasks is minimised.
  • the scheduler of the Trigger routine may employ scheduling facilities of the GPOS to achieve its scheduling.
  • FIG. 6 is a flow chart illustrating the method steps of an embodiment of the invention.
  • a GPOS is being executed.
  • a task for a RTOS is generated by the GPOS with an interrupt signal.
  • the interrupt signal is categorised as a first type, corresponding to a "delayed interrupt signal, or a second type, corresponding to an "immediate" interrupt signal.
  • a test determines which type of interrupt signal has been generated. If the interrupt signal is of the first type, at step 40 the interrupt signal is stored in a store.
  • step 50 the execution of the GPOS continues until either a new task for the RTOS is generated, in which case flow returns to step 10, or until a period of time elapses without the occurrence of an interrupt signal of the second type and also there is a stored interrupt signal of the first type. In the latter case, flow proceeds to step 60.
  • the period of time may be measured from the occurrence of the previous interrupt signal of the second type, or from the storage of the oldest stored interrupt signal of the first type.
  • step 30 if the interrupt signal is of the second type, flow proceeds to step 60.
  • step 60 execution of the GPOS ceases and any pending tasks, whether they correspond to interrupt signals of the first or second type, are executed by the RTOS. After step 60, execution of the RTOS ceases and flow proceeds to step 50 where execution of the GPOS resumes.
  • the invention may be implemented by adapting operating systems used in the prior art, by extending the inter-operating system services. This may be done in a transparent manner by providing a new inter-operating service to supplement existing services.
  • the inter-operating system services may allow drivers to register immediate and delayed interrupt signals, may record the interrupts in inter-operating system memory, and may trigger immediate and delayed interrupt signals.
  • the invention can be implemented in a transparent manner with respect to the RTOS; the RTOS executes tasks when it receives an interrupt signal and it need not be aware of whether an interrupt signal is of the immediate type or the delayed type. Following the execution of the RTOS tasks, execution of the GPOS may resume.
  • the Trigger routine may be implemented in a driver, for example as a low priority task on the GPOS.
  • Figure 7 depicts an architecture of a processing system according to the invention.
  • Both the RTOS and the GPOS are provided with drivers for inter-operating system devices that operate with "immediate” interrupt signals and for inter-operating system devices that operate with “delayed” interrupt signals, and are provided with an inter-operating system enhanced signal interface.
  • the GPOS software includes software for providing the Trigger routine.
  • the boxes labelled "Inter-OS device drivers services” and “Inter-OS signals” together provide inter-operating system control.
  • the shared memory provides transfer of inter-operating system data.
  • the notation used in Figure 7 is the same as in Figures 2 and 3, except that the signal paths are differentiated as "dsig” for delayed interrupt signals and as "isig" for immediate interrupt signals.
  • Figure 8 is a block schematic diagram of a processing system 100 according to an embodiment of the invention, comprising a processor 110, a store 120 and a controller 130 adapted to operate in accordance with the invention.
  • the processor 110 can execute alternately a real-time operating system and a non-real-time operating system.
  • the non-real-time operating system is adapted to, during execution, generate an interrupt signal signifying a pending task requiring execution by the real-time operating system, and is further adapted to categorise the interrupt signal as a first type or a second type.
  • the store 120 is for storing interrupt signals of the first type.
  • the controller 130 is adapted to, in response to the generation of an interrupt signal of the second type, inhibit execution of the non-real-time operating system, enable execution by the real-time operating system of the task signified by the interrupt signal of the second type and any pending tasks signified by stored interrupt signals of the first type, and, after completion of the task or tasks, enable execution of the non-real-time operating system.
  • the controller 130 has an optional timer 135 and an optional scheduler 136 for implementing the Trigger function described above.
  • Figure 9 is a block schematic diagram of a wireless device 200 comprising a transmitter 210 and a receiver 220 coupled to an antenna for the transmission and reception of wireless signals. Coupled to the transmitter 210 and receiver 220 is a processing system 100 as described above.
  • the invention also extends to computer program code adapted to carry out the invention when processed by a processor.
  • the computer program code can be carried by a computer readable medium.
  • the medium may be a physical storage medium such as a Read Only Memory (ROM) chip. Alternatively, it may be a disk such as a Digital Versatile Disk (DVD-ROM) or Compact Disk (CD-ROM). It could also be a signal such as an electronic signal over wires, an optical signal or a radio signal such as to a satellite or the like.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne un procédé permettant de faire fonctionner un système de traitement comportant un processeur pour exécuter alternativement un système d'exploitation en temps réel et un système d'exploitation non en temps réel. Des interruptions générées par le système d'exploitation non en temps réel pour lancer l'exécution d'une tâche par le système d'exploitation en temps réel sont classées par catégories comme un type retardé ou un type immédiat. Les tâches correspondant au type retardé d'interruptions ne sont pas exécutées immédiatement par le système d'exploitation en temps réel RTOS, mais ces interruptions sont au contraire mémorisées, et l'exécution de leurs tâches est reportée jusqu'à ce qu'un type immédiat d'interruption soit généré, moment auquel les tâches correspondant à toutes les interruptions en suspens sont exécutées. Par la suite, l'exécution du système d'exploitation non en temps réel est reprise.
PCT/IB2009/050196 2008-01-28 2009-01-20 Systèmes d'exploitation doubles fonctionnant sur un unique processeur WO2009095812A1 (fr)

Applications Claiming Priority (2)

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EP08290072.1 2008-01-28
EP08290072 2008-01-28

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2280344A1 (fr) * 2009-07-23 2011-02-02 Biosense Webster, Inc. Prévention d'événements informatiques perturbateurs pendant les procédures médicales
WO2014001370A3 (fr) * 2012-06-26 2014-02-27 Inter Control Hermann Köhler Elektrik GmbH & Co. KG Dispositif et procédé pour une utilisation critique pour la sécurité
CN109522099A (zh) * 2017-09-20 2019-03-26 厦门雅迅网络股份有限公司 提高非实时性操作系统实时性的方法及其系统
CN111745651A (zh) * 2020-06-15 2020-10-09 哈工大机器人（合肥）国际创新研究院 一种智能机器人操作系统结构及其运作方法
WO2020217345A1 (fr) * 2019-04-24 2020-10-29 三菱電機株式会社 Dispositif, procédé et programme de traitement de données
CN115958600A (zh) * 2022-12-28 2023-04-14 上海新时达机器人有限公司 一种机器人控制系统

Citations (2)

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WO2004090719A2 (fr) * 2003-04-09 2004-10-21 Jaluna Sa Systemes d'exploitation
EP1538497A2 (fr) * 2003-12-05 2005-06-08 Rockwell Automation Technologies, Inc. Système d'exploitation de temps réel distribué

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
WO2004090719A2 (fr) * 2003-04-09 2004-10-21 Jaluna Sa Systemes d'exploitation
EP1538497A2 (fr) * 2003-12-05 2005-06-08 Rockwell Automation Technologies, Inc. Système d'exploitation de temps réel distribué

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011028751A (ja) * 2009-07-23 2011-02-10 Biosense Webster Inc 医療処置中のコンピューターの妨害イベントの防止
US8606377B2 (en) 2009-07-23 2013-12-10 Biosense Webster, Inc. Preventing disruptive computer events during medical procedures
EP2280344A1 (fr) * 2009-07-23 2011-02-02 Biosense Webster, Inc. Prévention d'événements informatiques perturbateurs pendant les procédures médicales
US10394212B2 (en) 2012-06-26 2019-08-27 Inter Control Hermann Kohler Elektrik Gmbh & Co. Kg Apparatus and method for a security-critical application
WO2014001370A3 (fr) * 2012-06-26 2014-02-27 Inter Control Hermann Köhler Elektrik GmbH & Co. KG Dispositif et procédé pour une utilisation critique pour la sécurité
CN104508578A (zh) * 2012-06-26 2015-04-08 盈德克勒电控有限公司 用于安全关键的应用的设备和方法
CN104508578B (zh) * 2012-06-26 2018-05-22 盈德克勒电控有限公司 用于安全关键的应用的设备和方法
CN109522099A (zh) * 2017-09-20 2019-03-26 厦门雅迅网络股份有限公司 提高非实时性操作系统实时性的方法及其系统
CN109522099B (zh) * 2017-09-20 2023-03-31 厦门雅迅网络股份有限公司 提高非实时性操作系统实时性的方法及其系统
WO2020217345A1 (fr) * 2019-04-24 2020-10-29 三菱電機株式会社 Dispositif, procédé et programme de traitement de données
CN113711187A (zh) * 2019-04-24 2021-11-26 三菱电机株式会社 数据处理装置、数据处理方法及程序
CN113711187B (zh) * 2019-04-24 2022-07-01 三菱电机株式会社 数据处理装置、数据处理方法及储存有程序的记录介质
CN111745651A (zh) * 2020-06-15 2020-10-09 哈工大机器人（合肥）国际创新研究院 一种智能机器人操作系统结构及其运作方法
CN111745651B (zh) * 2020-06-15 2022-04-05 哈工大机器人（合肥）国际创新研究院 一种智能机器人操作系统结构及其运作方法
CN115958600A (zh) * 2022-12-28 2023-04-14 上海新时达机器人有限公司 一种机器人控制系统

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