WO2009087491A1

WO2009087491A1 - Dynamic element matching processor for use in a data converter and a method of operation

Info

Publication number: WO2009087491A1
Application number: PCT/IB2008/051268
Authority: WO
Inventors: Hassan Ihs; Franck Da Costa; Frederic Schrive
Original assignee: Freescale Semiconductor, Inc.
Priority date: 2008-01-09
Filing date: 2008-01-09
Publication date: 2009-07-16

Abstract

A dynamic element matching (DEM) processor (200) for use in processing a multi-bit output signal produced by a sigma delta modulator (101, 111 ), the processor including a plurality of successive dividing stages (D1, D2, D3) in each of which at least one input signal having a number n, of digits is divided by a divider to produce a plural number n0 of output signals each having a number of digits equal to the number n, divided by the number n0, wherein each stage includes a number of dividers which is equal to the number of input signals applied in the stage; wherein a later dividing stage (D3) which follows at least one earlier dividing stage (D1, D2) includes a plurality of dividers which comprise Maximum-to-Minimum sorting processors (207, 209, 21 1, 213). Also described is a method of operation of the processor (200).

Description

TITLE: DYNAMIC ELEMENT MATCHING PROCESSOR FOR USE IN A DATA CONVERTER AND A METHOD OF OPERATION

FIELD OF THE INVENTION The present invention relates to a dynamic element matching (DEM) processor for use in a data converter and a method of operation of the processor. In particular, the invention relates to a DEM processor for use in processing of an output signal produced by a multi-bit sigma delta modulator. The modulator may be part of an analog to digital converter (ADC) or of a digital to analog converter (DAC), which are collectively referred to herein as 'data converters'.

BACKGROUND OF THE INVENTION

Sigma delta (also known as delta sigma) modulation is a technique widely used in data converters. The technique allows an electronic signal to be converted with a good Signal to Noise Ratio (SNR) and is used in a variety of products such as cellular telephones, landline telecommunications, consumer electronics and automotive control systems.

Typically, in a one-bit first order data converter providing an overall analog to digital conversion, the sigma delta modulator comprises an integrator followed by a one-bit quantiser with a feedback loop including a one-bit DAC unit connected from the output of the quantiser to the input of the integrator. In the case of a one-bit first order data converter providing an overall digital to analog conversion, a one- bit DAC unit is positioned at the output of the sigma delta modulator but not in a feedback loop.

For higher order data converters providing an overall analog to digital conversion, the sigma delta modulator comprises a plurality of integrators in series and a plurality of feedback loops, each including a DAC unit, connected from the output of the quantiser to the respective inputs of the integrators. In the case of a higher order data converter providing an overall digital to analog conversion, a DAC unit is positioned at the output of the sigma delta modulator but not in a feedback loop.

In order to achieve higher SNRs, multi-bit sigma delta modulation is gaining a wide acceptance in the design of Integrated Circuits (ICs). In a multi-bit sigma delta modulator, a multi-bit quantiser is employed in place of a single-bit quantiser. The associated DAC unit employed (in the feedback loop of the modulator or following the modulator) is a multi-bit processor The amount of noise introduced by the quantiser (known as 'quantisation noise') in a multi-bit sigma delta modulator is thereby reduced. However, multi-bit sigma delta modulation suffers from the problem of non-linearities in the DAC unit included in the data converter. The non-linearities stem from random mismatches inherent to analog components. In order to reduce the effect of these non-linearities, a DEM processor is employed. The DEM processor is included in the data converter between the sigma delta modulator output and the associated DAC unit, i.e. the DAC unit employed in the feedback loop of the modulator (for analog to digital data converters) or the DAC unit positioned after the modulator but not in a loop (for digital to analog data converters). The purpose of the DEM processor is to randomise the error introduced by DAC unit non-linearities and to stretch the power spectrum of the error over the sampling frequency band. Most of the power spectrum can then be filtered out by a downstream low-pass filter. In order to achieve particularly good suppression of non-linearity errors, noise-shaping techniques are used. Several first and second order noise shaping DEM processors have been reported in the published literature. In some applications employing switched capacitor circuits in which component mismatches are less than 1 %, first order noise shaping DEM processors are generally sufficient to achieve reasonable SNRs with moderate to high Over-Sampling Ratios (OSRs). The OSR is well known as the ratio between the sampling rate of the sigma delta modulator and twice the maximum signal frequency. However, it is desirable to achieve a low power consumption and a high signal bandwidth together with a suitably low OSR in sigma delta modulators, and this objective requires the use of second and higher order noise-shaping DEM processors. In addition, some sigma delta modulators, such as current mode and continuous time modulators, use current sources as components in DAC units. These modulators can experience mismatches in excess of 10% requiring the use of higher order noise-shaping DEM processors to provide satisfactory performance.

Whilst a limited number of second and higher order noise shaping DEM processors are known, none of these known processors is ideal. For example, for some DEM processors, e.g. the known 'Maximum-to-Minimum Sorting DEM' described later, the amount of hardware required to provide a satisfactory implementation of the processor, and hence the cost of the processor, is unduly large. In other DEM processors, e.g. the Galton DEM described later, although the amount of hardware required is not excessive, the noise suppression performance is less than desirable.

Thus, there exists a need for an improved DEM processor, and a method of use of the processor, for use in processing of an output signal produced by a multi-bit sigma delta modulator, which addresses at least some of the shortcomings of known DEM processors.

SUMMARY OF THE INVENTION

According to the present invention there is provided a DEM processor and a method of operation as described in the accompanying claims.

Specific embodiments of the invention are set forth in the dependent claims. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings

FIG. 1a shows a block schematic diagram of a generalised line-up of functional components in an analog to digital data converter. FIG. 1 b shows a block schematic diagram of a generalised line-up of functional components in a digital to analog data converter.

FIG. 2 shows a block schematic diagram of a DEM processor embodying the present invention which is useful in the line-up of FIG. 1a or FIG. 1 b.

FIG. 3 shows a block schematic diagram showing more detail of an illustrative Galton cell useful in the DEM processor of FIG. 2.

FIG. 4 shows a block schematic diagram showing more detail of an illustrative Maximum-to- Minimum sorting cell useful in the DEM processor of FIG. 2.

FIG. 5 shows a block schematic diagram showing more detail of an illustrative accumulator for use in the Maximum-to-Minimum sorting cell of FIG. 4. FIG. 6 shows a graph of Signal to Noise Ratio (SNR) versus input amplitude for different DEM processors, illustrating comparative performance of a DEM processor embodying the invention. FIG. 7 shows a graph of Signal to Noise Ratio (SNR) versus run number plotted for various simulated runs of different DEM processors, further illustrating comparative performance of a DEM processor embodying the invention.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION

FIG. 1a is a block schematic diagram of a generalised line-up 100 of functional components in an analog to digital data converter. A multi-bit sigma delta (ΣΔ) modulator 101 receives an analog input signal S_a and produces in a known way an output signal which comprises a bitstream which is a multi- bit serial signal whose average level represents an average level of the analog input signal S_a. The number of bits per word, n, of the output bitstream is indicated in FIG. 1a by the symbol 'n' accompanied by a diagonal stroke. The number of bits per word of other bitstreams is indicated in a similar manner in the drawings. The output signal is delivered to a feedback control loop 103 comprising a DEM processor ('DEM') 105 and a DAC (digital to analog converter) unit 107. The DEM processor 105 operates in a manner described later. The DAC 107 provides a reconversion of the multi-bit digital bitstream applied to it back into an analog error control signal in a known way. The error control signal is combined with the input signal S₃ by the modulator 101.

The output bitstream signal from the modulator 101 is also applied to a low pass filter 109, e.g. a decimation filter, which filters noise produced in the modulator 101 and in the DAC 107 to provide an output signal O₃ which is a digital representation of the input signal S₃. FIG. 1 b is a block schematic diagram of a generalised line-up 110 of functional components in a digital to analog data converter. A multi-bit sigma delta modulator 111 receives a digital input signal S_b and produces in a known way an output signal which comprises a bitstream which is a multi-bit serial signal whose average level represents an average level of the digital input signal S_b. The output signal produced by the modulator 111 is delivered in turn to a DEM processor 113, a DAC (digital to analog converter) unit 115 and a low pass filter 117. The DEM processor 113 operates in a manner described later. The DAC 1 15 provides a re-conversion of the multi-bit digital bitstream applied to it into an analog signal in a known way. The output signal from the DAC unit 115 is applied to a low pass filter 107, e.g. a smoothing filter, which filters noise produced in the modulator 101 and in the DAC 105 to provide an output signal O_b which is an analog representation of the input signal S_b.

As noted earlier, DEM processing is a technique which may be used to improve the linearity of DAC units. Thus, each of the DEM processor 103 in the line-up 100 and the DEM processor 1 13 in the line-up 110 is provided to improve the linearity of the associated DAC unit which follows it, namely the DAC unit 105 and the DAC unit 115 respectively. The non-linearity in the DAC unit in each case is caused by mismatches between internal processing elements in the DAC unit, and can be significantly reduced by the DEM processing. The DEM processing as operated by each of the DEM processors 103 and 113 includes selecting elements in the associated DAC unit in such a way that mismatch noise is randomised and pushed away from the signal frequency where it can be easily removed by filtering by the filter 107 or the filter 1 17 as appropriate. So the technique provides shaping of the mismatch noise by operating in the DEM processors 103 and 113 an element selection algorithm. This selection algorithm can be designed to achieve a first order noise shaping (such as the known data weighted averaging algorithm) or a second or higher order noise shaping. Second or higher order noise shaping allows mismatch noise to be more severely attenuated.

FIG. 2 is a block schematic diagram of a DEM processor 200 embodying the present invention. The DEM processor 200 is a second order DEM processor which is useful as the DEM processor 103 in the line-up 100 of FIG. 1a and also as the DEM processor 113 in the line-up 110 of FIG. 1 b. An input multi-bit signal S2 (obtained from the sigma delta modulator 101 shown in FIG. 1a or from the sigma delta modulator 11 1 shown in FIG. 1 b) is applied to the DEM processor 200. The input signal S2 is a bitstream representing a number which defines an amplitude level of the input signal S_a (FIG. 1a) or S_b (FIG. 1 b). For illustration purposes, the input signal S2 may be considered as being a sixteen-bit stream. In other words, the number N of bits per word in the input signal S_a is sixteen. A data stream having sixteen bits per word is typical of the streams currently produced as the outputs of sigma delta modulators. However, the number of bits per word in the multi-bit stream of the input signal S2 may be another number, especially another number greater than four that is an integral power of two. The DEM processor 200 includes successive dividing stages D1 , D2 and D3 mutually arranged in a treelike configuration branching from the first dividing stage D1. In each of the dividing stages there is at least one divider which divides an input signal applied to the stage having a number n, of bits to produce a plural number of output signals each having a number n_oof bits. The number n₀ of bits in each output signal is equal to the number n, of bits in the input signal of the stage divided by the number of output signals. Each dividing stage thus includes a number of dividers which is equal to the total number of the output signals produced in the stage divided by the number of input signals applied in the stage.

The 16-bit input signal S2 is applied in the first dividing stage D1 of the DEM processor 200 to a single divider provided by a Galton cell (processor) 201 described in more detail later with reference to FIG. 3. The Galton cell 201 produces in parallel two output 8-bit signals by division of the input signal S2. The two 8-bit signals are applied in parallel as input signals in the second dividing stage D2 respectively to a Galton cell 203 and a Galton cell 205. Each of the Galton cell 203 and the Galton cell 205 produces in parallel two output 4-bit signals by division of the 8-bit signal applied to it. Thus four A- bit signals are produced in parallel by the second dividing stage D2. The four 4-bit signals are applied as input signals in the third dividing stage D3. The third dividing stage D3 is illustratively a final dividing stage in the DEM processor 200. However, in principle, further dividing stages could follow the third dividing stage D3. The 4-bit signals applied in the third dividing stage D3 are applied in parallel respectively to a 4-bit Max-to-Min (Maximum-to-Minimum) sorting cell (processor) 207, a 4-bit Max-to- Min sorting cell 209, a 4-bit Max-to-Min sorting cell 211 and a 4-bit Max-to-Min sorting cell 213. The cell 207 produces in parallel four output 1-bit signals 01 , 02, 03 and 04 by division of the 4-bit signal applied to it. The cell 209 produces in parallel four output 1-bit signals 05, 06, 07 and 08 by division of the 4-bit signal applied to it. The cell 211 produces in parallel four output 1-bit signals 09, O10, 011 and 012 by division of the 4-bit signal applied to it. The cell 213 produces in parallel four output 1-bit signals 013, 014, 015 and 016 by division of the 4-bit signal applied to it. Thus sixteen 1-bit signals are produced in parallel by the third dividing stage D3. The output signals 01 to 016 may be applied to a DAC unit following the DEM 200, e.g. to the DAC 105 (FIG. 1a) or to the DAC 115 (FIG. 1 b) as appropriate, in a known manner. The application may be made in the form of a serial bitstream or as a parallel set of outputs, which may be in the form of single or multiple bits, depending on the configuration of the following DAC unit.

In addition to dividing the input signal applied to it, each of the dividers in each of the dividing stages D1 , D2 and D3 re-arranges the bits of the input signal applied to it so that the bits of the output signals it produces are ordered pseudo - randomly for the purpose of randomising selection of the elements of the following DAC that the bits of the output signals 01 to 016 are to be applied.

FIG. 3 is a block schematic diagram of an illustrative Galton cell 300 useful as each of the Galton cell 201 , the Galton cell 203 and the Galton cell 205 in the DEM processor 200 of FIG. 2. The Galton cell 300 has a form which is known per se from US-A-5,684,482 issued to Ian A. Galton. The Galton cell 300 operates to divide an input digital signal S3 having n (= n, ) bits, where n is a number which is an integral power of two, into two output signals each having n₀ bits, where n₀ is equal to n divided by two. The input signal S3 is applied in parallel to an adder 301 and a subtractor 303 as well as to a parity checker 309. An output of the adder 301 is applied as an input signal to a divider 305 which divides the input signal by two. An output of the subtractor 303 is applied as an input signal to a divider 307 which divides the input signal by two.

An output of the parity checker 309 is applied as a first input signal to a multiplier 311 which also receives as a second input signal an input from a control loop 313. The control loop 313, which includes the multiplier 311 , extends from an output of the multiplier 311 and includes a cascade of two integrators, namely an integrator 315 and an integrator 317. An output signal from the integrator 317 is applied as an input signal to an adder 321 which adds the input signal to another input signal from an amplifier 319, e.g. having a gain factor of ten, in a feed forward loop extending between an input of the integrator 317 and the adder 321. The amplifier 319 is present to improve signal to noise ratio in a known manner. An output signal from the adder 321 is delivered to the multiplier 311 via a one-bit quantiser 323, which in a simple form may be a comparator.

The Galton cell 300 operates in the following way. The input signal S3 is formed into three equal parts each having the same value as the signal S3 by application respectively to the parity checker 309, the adder 301 and the subtractor 303. The parity checker 309 checks whether the input signal S3 is even or odd by checking in a known way whether the number represented by the n bits of the input signal S3 is even or odd. The parity checker 309 produces an output signal having a value of zero when the input signal S3 is even and a value of one when the input signal is odd.

When the input signal S3 is detected by the parity checker 309 to be even, no change is made to the two parts of the signal S3 at the adder 301 and at the subtractor 303. Both of those parts are divided by two respectively by the divider 305 and the divider 307. Signals produced by the divider 305 and the divider 307 are output signals each coded with n_o = n/2 bits. The total value of the output signals is equal to the value of S3.

When the input signal S3 is detected by the parity checker 309 to be odd, one part of it is respectively incremented by one, or decremented by one, in the adder 301 and the other part is respectively decremented by one, or incremented by one, in the subtractor 303. An output signal from the adder 301 is again divided by two by the divider 305, and an output signal from the subtractor 303 is again divided by two by the divider 307. Signals produced by the divider 305 and the divider 307 are again output signals each coded with n_o = n/2 bits. However, the coding of the output bits is different in the cases when the input signals are respectively even and odd. The total value of the output signals is the same in the two cases. A signal required to be applied to the adder 301 and to the subtractor 303 when the signal S3 is odd in order to increment or decrement the parts of the input signal S3 by one is generated by the loop 313. As noted earlier, the parity checker 309 produces an output signal having a value of one when the input signal S3 is odd. This output signal is applied to the multiplier 311 , which produces an output signal causing the loop 313 to come into operation. An output signal from the quantiser 323 is received via the multiplier 311 by the loop 313. The loop 313, including the cascade of the integrators 315 and 317, behaves like a sigma delta modulator and can be considered as introducing a second order element mismatch shaping. The quantiser 323 produces an output signal having a value of plus or minus one (as appropriate) which is delivered via the multiplier 311 to the adder 301 and the subtractor 303.

In some of the systems according to the prior art, it is necessary to add some dithering in a known way at an input of a quantiser equivalent to the quantiser 323 to break down any cyclical patterns that may take place in the loop 313 in order to reduce well known idle tones. Beneficially, since the Galton cell 300 is used in the first dividing stage D1 and the second dividing stage D2 in the DEM processor 200 embodying the invention, no such dithering is needed because of the presence of the Max-to-Min sorting cells in the third dividing stage D3 of the DEM processor 200.

The architecture of the Galton cell 300 described with reference to FIG. 3 is very hardware efficient, and the Galton cells in the DEM processor 200 can be implemented using the architecture with an acceptable amount of hardware present, especially when in the form of a semiconductor integrated circuit incorporating hardware elements fabricated in a known manner.

FIG. 4 is a block schematic diagram of an illustrative generalised Max-to-Min sorting cell 400 useful as each of the Max-to-Min sorting cells 207, 209, 21 1 and 213 in the processor 200 shown in FIG. 2. The cell 400 is a processor which includes a Max-to-Min sorter 409 which receives in parallel n input n-digit numbers {Ai} produced respectively by n accumulators 401 , 403, 405 ... 407 (four are shown and used but more could be used). The sorter 409 sorts values of the n input numbers Ai from largest to smallest. The sorter 409 produces in parallel n 1-bit output signals 01 , 02, O3....On, which may be generally denoted as output signals Oi. The output signals Oi correspond respectively to the inputs from the n accumulators 401 , 403, 405 ... 407. The accumulators 401 , 403, 405 407 are controlled by (i) an n-digit input signal S4 provided to the processor 400 which is delivered to each of the accumulators 401 , 403, 405 and 407; and (ii) the output signals Oi, corresponding to each of the accumulators 401 , 403, 405 and 407, produced by the sorter 409.

If the input signal S4 represents a number having a value equal to S, the S largest of the Ai numbers are selected by the sorter 409 and their corresponding output signals Oi are assigned a value equal to one by the sorter 409. The remaining output signals Oi are assigned a value equal to zero by the sorter 409. For instance, consider a situation in which n = 4, the input signal has a value S = 3, and the accumulators 401 , 403, 405 and 407 have generated numbers whose sizes are in the following order: A1 > A2 > A3 > A4. Since the three (S = 3) largest numbers Ai are A1 , A2 and A3, then the corresponding output signals 01 , 02 and 03 will be assigned the value of one by the sorter 409. The remaining output signal 04 will be assigned the value of zero.

FIG. 5 is a block schematic diagram of an illustrative accumulator 500 suitable for use as each of the accumulators 401 , 405, 407 and 409 in the Max-to-Min sorting cell 400. The input signal S4 and the output signal Oi corresponding to the accumulator 500, e.g. where produced by the sorter 409 (FIG. 4), are applied as input signals to the accumulator 500. The input signal Oi is amplified by an amplifier 503 having a gain factor of n. The input signal S4 and an output signal produced by the amplifier 503 are both applied as input signals to a subtractor 501. The subtractor 501 produces an output signal equal to S4 minus (Oi multiplied by n). The output signal produced by the subtractor 501 is applied in turn to a first integrator 505 and, via an adder 507, to a second integrator 51 1. The output signal produced by the subtractor 501 is also applied via an amplifier 509, e.g. having a gain factor of ten, to the adder 507.

Since the accumulator 500 includes a second order cascade of the integrators 505 and 511 it sets the second order noise shaping of element mismatches. The first integrator 505 integrates an error signal equal to the output signal produced by the subtractor 501.

The second integrator 511 integrates an error signal equal to an amplified version of the output signal produced by the subtractor 501 plus an output signal produced by the first integrator 505.

When the output signal Oi of the sorter 409 which is applied to the subtractor 501 has a value equal to one, the accumulator 500 operates to decrement the value of the output number Ai that it produces so that a value of zero is assigned to the corresponding output signal Oi. Similarly, when the output signal Oi which is applied to the subtractor 503 has a value equal to zero, the accumulator 500 operates to increment the value of the number Ai that it produces so that a value of one is assigned to the corresponding output signal Oi. By each of the accumulators 401 , 405, 407 and 409 operating in the manner which has been described for the accumulator 500, values of the numbers Ai are produced by the accumulators 401 , 405, 407 and 409 giving zeros and ones as the output signals Oi from the Max-to-Min sorter 409 in a pseudo-random and noise-shaped way.

The Max-to-Min sorter 409 of the processor 400 requires n! logical operations to execute its sorting procedure, where n is the number of bits of the input signal S4. Thus, if n = 4, only 24 logical operations are required. This number of operations is easily achievable with an acceptable amount of implementation hardware. However, when the number of bits n of the input signal S4 is greater than 4, and the number of bits n is normally an integral power of two, the unduly large amount of hardware required becomes impractical to implement. For instance, when n = 8, 40320 logical operations are required in the sorter 409. In consequence, Max-to-Min sorting processors are only suitable for practical use in DEM processors when the number n of bits in the input signal is limited to 4. However, such limitation is acceptable for the Max-to-Min sorting cells 207, 209, 21 1 and 213 in the DEM processor 200 embodying the invention, since the input signals that those processors receive have already been limited to four bits by the operation of the Galton cells 201 , 203 and 205 in the earlier dividing stages. Although the Galton cell 300 and the Max-to-Min sorting cell 400 are known per se, the arrangement of Galton cells and Max-to-Min sorting cells in the form illustrated in the DEM processor 200 is novel and inventive. The arrangement provides a beneficial combination of the advantages of each of the Galton cell and the Max-to-Min sorting cell, whilst keeping the disadvantages of each, particularly the disadvantages of the Max-to-Min sorting cell, within acceptable limits. Thus, although (as noted earlier) implementation of each Max-to-Min sorting cell requires, especially in the sorter of the cell, many hardware components, the input signal to each such cell may be limited to n = M bits, where M is a number which requires an acceptable number of hardware components. For example, a practical limit to the number n = M is four. Using a plurality of such M-bit cells in a later dividing stage of the DEM processor, which may be the final dividing stage, e.g. the stage D3 of the processor 200, following earlier dividing stages in which the dividers are other than Max-to-Min sorting cells, e.g. the Galton cells in the dividing stages D1 and D2 of the processor 200, allows an input signal to the DEM processor 200 having N bits, where N is a number greater than M, to be suitably divided in the earlier dividing stages, before application to the stage having the M-bit Max-to-Min sorting cells. Implementation of such a processor may be achieved without requiring an unduly large number of hardware components in the earlier dividing stages.

The number of M-bit Max-to-Min sorting cells that may be used in the later dividing stage is not necessarily limited to four. The number of such cells used in that stage and the number of other cells used in other dividing stages of the DEM processor is limited only by what is considered to be an upper practical limit to the total number of cells, and the number of processing elements in the cells, of the DEM processor. However, the DEM processor 200 illustrates use of a practical number of the individual cells in the overall processor. The input signal to the DEM processor 200 has illustratively sixteen bits and is divided successively in stages D1 and D2 to give four parallel four-bit signals as inputs to the four Max-to-Min sorting cells of the third dividing stage D3 giving sixteen one-bit output signals from the stage D3. The resulting effect of providing the arrangement illustrated by the DEM processor 200 is to provide, for a given number n of bits in the input signal S2, an overall DEM processor that shows a better performance than if implemented by only Galton cells in all dividing stages. The resulting overall DEM processor can thereby be implemented using a number of hardware components which is kept within an acceptable upper limit, unlike an overall DEM processor implemented by only a Max-to-Min sorting cell operating on an n-bit input signal when n is greater than four. In order to demonstrate the benefits obtainable by use of (i) the DEM processor 200 compared with (ii) a sixteen bit DEM processor comprising only Galton cells; and (iii) a sixteen bit DEM processor comprising only Max-to-Min sorting cells; a comparative simulation analysis has been carried out. In the analysis, the three DEM processors (i), (ii) and (iii) were included in a current mode stereo DAC using a third order 17-levels sigma delta modulator having an OSR of 128. The behaviour of the three processors was simulated by considering Signal to Noise Ratio (SNR) obtained as a function of input signal amplitude with a 10% random mismatch applied in the DAC. The results obtained are shown in FIG. 6. A curve 601 represents the results obtained for the DEM processor (ii) formed only of Galton cells. The best SNR obtainable (at the upper right hand end of curve 601 ) is about 112 dB. A curve 605 represents the results obtained for the DEM processor (iii) formed only of a Max-to-Min sorting cell. The best SNR obtainable is about 120 dB. A curve 603 represents the results obtained for the DEM processor (i) which comprises the DEM processor 200 embodying the invention. The curve 603 lies between the curves 601 and 605. The best SNR obtainable is about 117 dB which is close to the best SNR for the curve 605. The curve 603 is about 1OdB higher than the curve 601 for most of its range. A curve 607 represents the theoretical performance of an ideal DEM processor, which is one simulated to show no mismatch error.

The comparative results for the DEM processors (i), (ii) and (iii) simulated with and without the presence of 10% random element mismatches applied using a fixed input signal amplitude of -2OdB were also obtained. Since the simulated mismatches applied were random, a large number, i.e. fifty, runs were carried out to obtain suitable mean values for the results. The Signal to Noise Ratio (SNR) versus random run numbers for component mismatches of the three DEM processors (i), (ii) and (iii) referred to above, as well as the result for an ideal processor having zero mismatch error, were plotted and the resulting plots are shown in FIG. 7. A curve 701 represents the plot obtained for the DEM processor (ii) formed only of Galton cells. A curve 705 represents the plot obtained for the DEM processor (iii) formed only of a Max-to-Min sorting cell. A curve 703 represents the plot obtained for the DEM processor (i) comprising the DEM processor 200 embodying the invention. A line 707 represents the plot obtained for the ideal DEM processor. FIG. 7 shows that the curve 703 is between the curves 701 and 705, but is closer to the curve 705 which shows a better average SNR than the curve 701.

The results plotted in FIGS. 6 and 7 demonstrate that the DEM processor 200 embodying the invention gives a noise shaping performance which is improved compared with the DEM processor (ii) formed only of Galton cells. The performance is not as good as that theoretically obtainable with the DEM processor (iii) using only a Max-to-Min sorting cell. However, the DEM processor (iii) is not achievable in a practical form when the input signal has more than four bits because the number of hardware components needed to implement it is unduly large. So the DEM processor (i) comprising the DEM processor 200 embodying the invention beneficially has a performance which approaches the theoretical performance of the DEM processor (iii) but has a form which can be produced in a practical implementation for an input signal having more than four bits, e.g. sixteen bits.

The DEM processor 200 embodying the invention may suitably be fabricated using known technology in the form of an integrated circuit, e.g. formed on a semiconductor chip. The chip may include other functional units, for example other components of a data converter such as a DAC or an ADC.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, the connections may be an type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise the connections may for example be direct connections or indirect connections.

For example, the invention is not limited to physical devices or units implemented in non- programmable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code. Furthermore, the devices may be physically distributed over a number of apparatuses, while functionally operating as a single device. Also, devices functionally forming separate devices may be integrated in a single physical device. However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the words 'a' and 'an' shall not be construed as limited to 'only one', but instead are used to mean 'at least one', and do not exclude a plurality. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A dynamic element matching (DEM) processor (200) for use in processing a multi-bit output signal (S2) produced by a sigma delta modulator (101 , 111 ), the processor including a plurality of successive dividing stages (D1 , D2, D3) in each of which at least one input signal having a number n, of digits is divided by a divider to produce a plural number n₀ of output signals each having a number of digits equal to the number n, divided by the number n₀, wherein each stage includes a number of dividers which is equal to the number of input signals applied in the stage; and wherein a later dividing stage (D3) which follows at least one earlier dividing stage (D1 , D2) includes a plurality of dividers which comprise Maximum-to-Minimum sorting processors (207, 209, 21 1 , 213).

2. A dynamic element matching processor according to claim 1 wherein each of the Maximum-to- Minimum sorting processors (400) is operable to receive a four-bit input signal (S4) and to produce four one-bit output signals (01 , 02, 03, 04).

3. A dynamic element matching processor according to claim 1 or claim 2 wherein the Maximum- to-Minimum sorting processor (400) includes a sorter (409) and a plurality of accumulators (401 , 403,

405, 407) providing input signals (A1 , A2, A3, A4) to the sorter, wherein the sorter is operable to sort values of the input signals from the accumulators in an order and to provide output signals each corresponding to one of the input signals, each output signal having a first value when its corresponding input signal is in a first set of largest values in the sorted order and having a second value when its corresponding input signal is in a second set of smallest values in the sorted order, the first and second sets having sizes depending on a value of an input signal from an earlier dividing stage.

4. A dynamic element matching processor according to claim 3 wherein the accumulator (500) of the Maximum-to-Minimum sorting processor (400) is operable to receive an input signal (S4) from an earlier dividing stage and an input signal (Oi) which is the corresponding output signal produced by the sorter and to produce an output signal which changes the value of its corresponding output signal (Oi) produced by the sorter.

5. A dynamic element matching processor according to any one of the preceding claims wherein each dividing stage (D1 , D2) of the at least one earlier dividing stage prior to said later dividing stage (D3) includes at least one divider (201 , 203, 205) which is operable to divide an input signal (S2) having a number n, of digits into two output signals each having a number of digits equal to the number n, divided two.

6. A dynamic element matching processor according to any one of the preceding claims which includes at least three dividing stages wherein the first stage (D1 ) includes a single divider (201 ) operable to divide an input signal having n bits into two output signals each having a number of bits equal to n divided by two, the second stage (D2) includes two dividers (203, 205) each receiving one of the output signals from the divider of the first stage and each operable to divide its input signal having n divided by two bits into two output signals each having a number of bits equal to n divided by four.

7. A dynamic element matching processor according to claim 5 or claim 6 wherein each divider in the at least one earlier dividing stage (D1 , D2) prior to said later dividing stage (D3) comprises a Galton processor (201 , 203, 205).

8. A dynamic element matching processor according to claim 7 wherein the Galton processor comprises a parity checker (309), an adder (301 ) and a subtractor (303) each operable to receive an input signal (S3) to the Galton processor, a first divider (305) operable to divide an output signal produced by the adder by two, a second divider (307) operable to divide an output signal produced by the subtractor by two, and a modulator (313, 315, 317, 321 , 323) operable when the input signal is detected by the parity checker to have an odd value, to apply to the subtractor and the adder an input signal which changes the value of the input signal.

9. A dynamic element matching (DEM) processor according to any one of the preceding claims wherein the DEM processor (200) is in the form of a semiconductor integrated circuit chip optionally including one or more other devices or systems.

10. A method of operation in a dynamic element matching (DEM) processor according to any one of the preceding claims including delivering to the DEM processor a multi-bit output signal (S2) produced by a sigma delta modulator (101 , 111 ) , applying the delivered signal successively to a plurality of dividing stages (D1 , D2, D3) in each of which at least one input signal to the stage having a number n, of digits is divided by a divider to produce a plural number n₀ of output signals each having a number of digits equal to the number n, divided by the number n₀, wherein each dividing stage includes a number of dividers which is equal to the number of input signals applied in the stage; the method further including, in a later dividing stage (D3) following at least one earlier dividing stage (D1 , D2), applying each of a plurality of input signals to the stage to each of a plurality of dividers which comprise Maximum-to-Minimum sorting processors (207, 209, 211 , 213).

11. A data converter including a dynamic element matching processor according to any one of claims 1-9.