WO2009087090A1 - Dispositif et procédé de commutation sélective de deux maîtres pour des esclaves attribués dans un circuit en boucle logique - Google Patents

Dispositif et procédé de commutation sélective de deux maîtres pour des esclaves attribués dans un circuit en boucle logique Download PDF

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Publication number
WO2009087090A1
WO2009087090A1 PCT/EP2009/000039 EP2009000039W WO2009087090A1 WO 2009087090 A1 WO2009087090 A1 WO 2009087090A1 EP 2009000039 W EP2009000039 W EP 2009000039W WO 2009087090 A1 WO2009087090 A1 WO 2009087090A1
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WIPO (PCT)
Prior art keywords
master
signal
switch
transmitter
receiver
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PCT/EP2009/000039
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German (de)
English (en)
Inventor
Emanuel Seidinger
Wolfgang Schittenhelm
Georg Lechner
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Fachhochschule Rosenheim
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Publication of WO2009087090A1 publication Critical patent/WO2009087090A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40169—Flexible bus arrangements
    • H04L12/40176—Flexible bus arrangements involving redundancy
    • H04L12/40202—Flexible bus arrangements involving redundancy by using a plurality of master stations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/423—Loop networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/43—Loop networks with decentralised control with synchronous transmission, e.g. time division multiplex [TDM], slotted rings
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/4026—Bus for use in automation systems

Definitions

  • the invention relates to a device for the selective switching of at least two masters for at least one associated slave.
  • the invention relates to a device for selectively switching over at least two masters for at least one associated slave, one of the at least two masters and the slaves being connected by at least one logical ring circuit via a bus system, wherein a changeover switch is provided which optionally provides the each active in the ring circuit master exchanges against another of at least two master in0 the ring circuit.
  • the invention also relates to a method for selectively switching at least two masters for at least one associated slave. More particularly, the invention relates to a method for selectively switching at least two masters for at least one associated slave, wherein each one of the at least two master and5 the slaves are connected by at least one logical ring circuit via a bus system, wherein a switch is provided which optionally the respective active in the ring circuit master exchanges against another of at least two master in the ring circuit.
  • the SERCOS (Real Real Time Communication System) interface is a worldwide standardized IEC 61491 and EN 61491 standard digital interface for communication between controllers, drives and other distributed peripherals. With this, numerically controlled high-performance drive applications in mechanical engineering can be realized.
  • the SERCOS switch is a network component for the SERCOS interface.
  • the SERCOS interface is a ring-shaped fieldbus for electric drives.
  • a master control also called a master for short, and several slaves communicate via a line, for example via an optical line (SERCOS I 1 II) or a copper line (SERCOS III).
  • the slaves provide the bus connection for the drives
  • the master and each slave have at least one transmitter and one receiver.
  • the SERCOS interface specifies a strictly hierarchical communication with the data in the form of data blocks, the so-called telegrams, which are exchanged in time-constant cycles (cycle phase, cycle phase, CP) between the master and the several slaves.
  • T c time-constant cycles
  • the cycle time T c is selected during the initialization of the master and usually remains as long as this master is active in the ring circuit.
  • the master either transmits subscripts or feeds fill characters into the ring with an independent send step.
  • the slaves either pass on their input signals to the next participants in the ring circuit or they send their own telegram.
  • the master does not pass on its input signal.
  • Each telegram starts and ends with a telegram limit.
  • the communication cycle of the SERCOS interface is divided into five phases: CPO, CP1, CP2, CP3 and CP4. Each cycle is started by a master synchronization telegram (MST), which is used to specify the communication phase 'and the time reference. Due to the ring structure of the system, all connected nodes receive this telegram one after the other. Thus, SERCOS achieves synchrony, but no simultaneity, since there is a time offset between the participants of the ring circuit.
  • the drive telegrams which are sent by the individual slaves are connected to the master synchronization telegram. After all drive telegrams have been sent to the master, this sends a master data telegram to all slaves.
  • the master starts the next cycle with the master synchronization telegram.
  • the SERCOS interface knows the following types of synchronization: bit synchronization, synchronization of the communication and the synchronization of the data processing in the slaves.
  • German Patent Application DE 198 15 097 A1 discloses a bus master switching unit for a fundamentally non-redundant bus system, to each of which a bus master is operated from a group of redundant bus masters.
  • the switching unit is operated even on the bus to be switched, so that consequently no special signals for switching the bus master are required.
  • the respective active master and the drives are not operated in a ring circuit but via a line bus of the Profibus (bus system).
  • a switch adapted to the SERCOS interface including plug, protocol, etc., is not available on the market.
  • the available devices of the prior art do not support the SERCOS protocol with regard to the interfaces.
  • the opto-mechanical solution SERCOS II
  • data losses and errors in the switchover during operation are unavoidable.
  • SERCOS III is the third generation of the SERCOS Interface series and combines the advantages of SERCOS I and II, high-precision synchronization of digital drives in real time mainly within local networks, with the advantages of Ethernet physics and the Ethernet protocol, fast data exchange also far Distances and more flexibility.
  • the invention is therefore based on the object to provide a device which allows switching within at least one logical ring circuit between at least two masters and is suitable for all generations of SERCOS. This object is achieved by a device comprising the features of claim 1. Further advantages emerge from the associated subclaims and the description.
  • a further object of the present invention is to provide a method which switches without errors during operation within at least one logical ring circuit between at least two masters and can be used for all generations of SERCOS.
  • a master is connected to at least one associated slave by at least one logical ring circuit via a bus system.
  • a physical and at the same time logical ring circuit is established via optical lines (eg optical waveguides).
  • SERCOS IM both a physical line topology or a ring topology can be given over the Ethernet, for example via copper lines.
  • This physical line or ring topology in a SERCOS III application can be used as simple or double logical ring circuit in terms of the SERCOS technology due to the duplexing properties of the Ethernet, so the bidirectional signal forwarding, as in the following description for Figures 14 to 20 is explained in detail.
  • a switch which optionally exchanges the respective active in the ring circuit master against another master in the ring circuit.
  • the switch is realized as a digital circuit.
  • the signal forwarding is thus constructed such that alternating operation of the slaves with two masters is possible.
  • the switch of the device according to the invention comprises various receivers and transmitters of the prior art, as described in detail in the description of Figures 1, 4 and 5, so that the switch with each master and each slave is connected in a ring circuit.
  • a digital circuit with a multiplexer M4_1 and a demultiplexer D1_4 used in the prior art connected to a functional block which communicates with the multiplexer and the demultiplexer via the ring circuit on the bus system (see Figures 10 and 13).
  • the multiplexer, the demultiplexer and the functional block are integrated in the switch of the device according to the invention and connected to the respective active master and the slaves in the ring circuit.
  • an additional function "flying master” is implemented, by which the switch takes over the time slot of the synchronization telegram of the last active master during the change between the two masters and blocks the data of the last active master during the change and blocks its own synchronization telegram to the After transfer, the data of the now active master is forwarded.
  • the switch By the synchronization telegram of the switch so the change in the communication phase CPO and thus the shutdown of the slaves is triggered. For this, the time interval between the master synchronization telegrams of the last active master must first be determined, which corresponds to the states Detect_MST_x, "x" identifies the respective master, "1" stands for the first master, "2" stands for For example, the switch is in the Detect_MST_1 state if the last active master is the first master In this state, the signals of the last active master are forwarded to the slaves without any errors active Masters determined, ie the state Detect_MST_x terminated, the Flying Master of the switch starts to send the "wrong" master synchronization telegram, which corresponds to the states Send_MST_x, with "x” as described above.For the above example is the System then in the state Send_MST_1, where the signal of the last active Ma Sters blocked and forwarded the signal of the flying master of the switch.
  • the time slot of the MST of the Flying Master corresponds to that of the last active Master. After a few communication cycles, the Flying Master stops generating the master synchronization telegram and the signals of the new master are forwarded, which corresponds to the states Route_Master_x. With regard to the above example, the system is then in the state LC_ ⁇ v ⁇ ⁇ o ⁇ £. ivi ⁇ oici ucu ci oi ⁇ i ⁇ ivi ⁇ oi ⁇ i ⁇
  • the invention also discloses a method for selectively switching over at least two masters for at least one associated slave, wherein in each case one of the at least two masters and the slaves are connected by at least one logical ring circuit via a bus system.
  • a changeover switch is provided, which optionally exchanges the respectively actively located in the ring circuit master against another master in the ring circuit, preferably with a functional block as mentioned above.
  • the switch is realized as a digital circuit.
  • the signal forwarding is bidirectional instead of monodirectional. Accordingly, the transmitter or receiver are designed as duplex connections, so that the transmitter or receiver are at the same time also receivers or transmitters.
  • Figure 1 a schematic representation of the structure of the optical field bus in a ring circuit according to the prior art
  • FIG. 2 is a schematic representation of the communication cycle of the SERCOS interface with its five phases according to the prior art
  • FIG. 3 shows a diagram of the timing of a SERCOS communication cycle according to the prior art with any communication phase, viewed at the transmitter of the last slave;
  • Fig. 4 is a schematic representation of a prior art Riny & uhciituny with two masters;
  • Figure 5 is a schematic representation of an embodiment of the device according to the invention for a ring circuit with two masters and a switch;
  • FIG. 6 is a schematic representation of an opto-mechanical switching according to the prior art in one setting
  • Figure 7 is a schematic representation of an opto-mechanical switching according to the prior art in a different setting than Figure 6;
  • FIG. 8 shows a diagram of the time sequence of a SERCOS communication cycle with any communication phase CPx in the communication cycle n and the communication phase CPO from the communication cycle n + 1, viewed at the transmitter of the last slave for the changeover switch of the device according to the invention;
  • FIG. 9 shows a state diagram with states and signals for a simple switchover
  • Figure 10 is a digital block diagram of an embodiment of the switch of the device according to the invention with a multiplexer and a demultiplexer for easy switching; ⁇
  • Figure 11 is a state diagram for the sequence of switching between two masters with the switch of the device according to the invention for a safe switching;
  • Figure 12 is a diagram showing the timing of a switching operation with any communication phase CPx in the communication cycle n and the communication phase CPO from the communication cycle n + 3, considered at the transmitter of the last slave for the switch of the inventive device for a secure switching;
  • FIG. 13 is a digital block diagram for a preferred embodiment of the switch of the device according to the invention with a multiplexer, a demultiplexer and a functional block for secure switching;
  • FIG. 14 a schematic view of a simple SERCOS II! and Etherrset- suitable embodiment of the device according to the invention, wherein the switch each having a duplex connection to a master and a respective duplex connection to the first slave;
  • Figure 15 is a schematic transmission channel view of the circuit of Figure 14 with the first master active
  • Figure 16 is a schematic transmission channel view of the circuit of Figure 14 with the second master active
  • FIG. 17 shows a schematic connection view of a preferred SERCOS IM and Ethernet-suitable embodiment of the device according to the invention, wherein the
  • Changeover switch has two duplex connections each with one master and two duplex connections to the slaves each;
  • Figure 18 is a schematic transmission channel view of the circuit of Figure 17 with the first master active
  • Figure 19 is a schematic transmission channel view of the circuit of Figure 17 with the second master active.
  • FIG. 20 shows a state diagram for the sequence of switching between two masters with the converter of the simple or preferred SERCOS III and Ethernet-suitable embodiment of the device according to the invention for a secure switchover.
  • Figure 1 shows a schematic representation of the structure of the bus system 5 in a ring circuit 1 according to the prior art.
  • the master 2 includes an optical transmitter 22 and an optical receiver 21.
  • Each slave 3 j, j 1, ..., n, has an optical transmitter and an optical receiver 32 j 31 j.
  • the transmitter 22 of the master 2 sends signals to the receiver 3I 1 of the first slave 3i.
  • the transmitter 32i of the first slave 3 ⁇ sends signals to the receiver 31 2 of the second slave 3 2
  • the transmitter 32 2 of the second slave 3 2 sends signals to the receiver 31 3 of the third slave 3 3
  • Sender 32 n- i of the penultimate slave 3 n- i sends signals to the receiver 31 n of the last slave 3 ".
  • the Ringing circuit 1 is closed in that the transmitter 32 n of the last slave 3 n sends signals to the receiver 21 of the master 2.
  • first slave and “last slave” is meant that the first slave follows as the first slave to the master and the master follows the last slave in the ring circuit 1.
  • the communication phases CPO to CP3 the communication is initialized.
  • CP4 cyclic communication then takes place.
  • CPx can only switch to the next higher communication phase CPx + 1, with x between 0 and 3, represented by the initialization communication paths 60.
  • CPO represents an exception because the phase CPO can be used by every other communication phase CP1, CP2, CP3 or CP4, represented by the failsafe communication paths 62.
  • CPO can therefore be regarded as a failsafe state in which the slaves 3 j are shut down. If the slaves are 3, in the CPO state, they do not expect any telegrams and the communication can be reinitialized at any time.
  • FIG. 3 shows a diagram of the time sequence t of a SERCOS II communication cycle according to the prior art with any communication phase CPx, x between 0 and 4, viewed at the transmitter of the transmitter 32 "of the last slave 3 n .
  • a respective communication cycle with the duration T c is, as described above, sequentially via the first slave S 1 to the last slave 3 "sent.
  • slave data telegrams also called drive telegrams (AT)
  • MDT master data telegrams
  • CPx the communication phase CPx of the nth communication cycle according to FIG. 3, after the master synchronization telegram (MST-CPx), for example, AT and MDT telegrams continue one after the other. Subsequently, at time (n + 1) * Tc, the next communication cycle starts with a communication phase CPx with the message MST_CPx.
  • the only telegram sent in each communication phase CPx is the master synchronization telegram (MST_CPx).
  • the master synchronization message MST is sent via the bus system 5.
  • the telegrams AT and MDT are not sent during the communication phase CPO.
  • the MST in the communication phase CPO serves the currently active master 2, to check the ring circuit 1 for closure.
  • the slaves 3, send their telegrams AT, not yet or not more.
  • the slaves 3, (drives) are shut down. In this phase the slaves expect 3, no telegrams, neither the MST. It can therefore be an arbitrarily long communication break.
  • FIG. 4 shows a further schematic illustration of a ring circuit 1.
  • two masters 2 1 and 2 2 according to the prior art are provided here.
  • no changeover switch 4 is shown yet.
  • the transmitter 22, the master sends signals to the receiver 3I 1 of the first slave 3i.
  • the transmitter 32i of the first slave S 1 sends signals to the receiver 31 2 of the second slave 3 2
  • the transmitter 32 2 of the second slave 3 2 sends signals to the receiver 31 3 of the third slave 3 3 , etc., ...
  • the transmitter 32 n- i of the penultimate slave 3 n- i sends signals to the receiver 31 "of the last slave 3 n .
  • the ring circuit 1 is closed by the transmitter 32 "of the last slave 3" sends signals to the receiver 21, the active master 2.
  • the master 2 ⁇ is actively connected in the ring circuit 1 to the slaves 3, represented by the solid lines.
  • the master 2 2 is not connected to the ring circuit 1.
  • the master 2 1 is to be exchanged for the master 2 2 in the ring circuit 1, represented by the dashed lines.
  • Figure 5 shows a schematic representation of an embodiment of the device according to the invention for a ring circuit 1 with two masters 2i and 2 2 and a switch 4.
  • the underlying topology is shown with the switch 4 of the device according to the invention.
  • the changeover switch 4 is arranged between the masters 2 ⁇ and 2 2 on the one hand and the slaves 3, on the other hand, so that an alternating operation of the slaves 3, with the two masters 2, is possible.
  • the switch 4 of the device according to the invention with each master 2, and with each slave 3 j in ring circuit 1 is switchable, as described below.
  • each master 2 each a receiver 41, arranged, wherein the switch 4 is so connected to the respective master 2, that the respective transmitter 22, the respective master 2, signals to the respective receiver 41, the switch 4 can send.
  • the changeover switch 4 comprises for each master 2, in each case one transmitter 42 ", wherein the changeover switch 4 is connected to the respective master 2, such that the respective transmitter 42, the changeover switch 4, sends signals to the respective receiver 21, of the respective one Masters 2, can send.
  • the switch 4 also comprises a transmitter 43, wherein the switch 4 is connected to the first slave S 1 such that the transmitter 43 of the switch 4 can send signals to the receiver 3I 1 of the first slave 3i.
  • the umscnaiter 4 also includes a receiver 44, wherein the switch 4 is connected to the last slave 31 "so that the receiver 44 of the switch 4 can receive signals from the transmitter 32 n of the last slave 3".
  • FIG. 6 shows a schematic representation of the principle of an opto-mechanical switching circuit 40 according to the prior art in one setting.
  • Such an opto-mechanical switching 40 can be used in a ring circuit 1 according to FIG.
  • the first master 2 1 is active in the ring circuit 1 with the slaves 3 j , in that the receiver 2I 1 of the first master 2 ⁇ is connected to the transmitter 32 n of the last slave 3 n , in that the receiver 44 of the switch 4 is connected to the transmitter ⁇ 2 ⁇ of the switch 4, and in that the transmitter 22 1 of the first master 2 ⁇ is connected to the receiver 3I 1 of the first slave S 1 , characterized in that the receiver 4I 1 of the switch 4 with the Transmitter 43 of the switch 4 is connected.
  • An opto-mechanical coupling 20 is set accordingly, that the first master 2 1 via the bus system 5 is active in the ring circuit 1 with the slaves 3 j .
  • FIG. 7 shows a schematic representation of an opto-mechanical switching 40 according to the prior art in a different setting than FIG. 6.
  • the second or further master 2 2 is active in the ring circuit 1 with the slaves 3 in that the receiver 21 2 of the second or further master 2 2 is connected to the transmitter 32 n of the last slave 3 n , in that the receiver 44 of the changeover switch 4 is connected to the transmitter 42 2 of the changeover switch 4, and by the transmitter 22 2 of the second or further master 2 2 is connected to the receiver 3I 1 of the first slave S 1 , characterized in that the receiver 41 2 of the switch 4 is connected to the transmitter 43 of the switch 4.
  • the opto-mechanical coupling 20 according to FIG. 6 is now different and adjusted such that the second or further master 2 2 is active in the ring circuit 1 with the slaves 3, via the bus system 5.
  • Figure 8 shows a diagram of the timing of a SERCOS communication cycle with any communication phase CPx in the communication cycle n and the communication phase CPO from the communication cycle n + 1, viewed at the transmitter 32 n of the last slave 3 n .
  • the change-over switch 4 detects the time slot of the MST, which is transmitted by the currently active master 2.
  • the change-over switch 4 ends the signal forwarding for the active master 2, and sends its own MST in the time slot of the last active Masters 2 "he soft in the Medünikationsphase CPO % , v ⁇ ch ⁇ e! t and the slaves 3 j prepared for a re-initialization by the newly activated, other Master 2.
  • FIG. 9 shows a state diagram with states 200, represented as ellipses, and signals, shown as arrows, for a simple switchover.
  • states 200 represented as ellipses, and signals, shown as arrows, for a simple switchover.
  • states 200 For simple switching only two states 200 "Route_Master_1” and “Route_Master_2” are necessary. In addition, four further states 200 are necessary for reliable switching, as will be described later for FIG. 11.
  • the signals 122 i are forwarded by the first master 2, to the first slave 3 i or the signals 132 of the last slave 3 n to the first master 1 ⁇ by means of a switching signal 10
  • Switch signal is changed directly to state 200 "Route_Master_2" or “Route_Master_1".
  • the signals 122 2 are forwarded from the second master 2 2 to the first slave S 1 or the signals 132 of the last slave 3 n to the second master 2 2 .
  • FIG. 10 shows a digital circuit diagram for an embodiment of the change-over switch 4 of the device according to the invention with a simple changeover.
  • a digital circuit with a multiplexer 6 is used in one embodiment as an M4_1 multiplexer and with a demultiplexer 7 in an embodiment as a D1_4 demultiplexer from the prior art.
  • the inputs 61 3 and 61 4 of the multiplexer 6 and the two outputs 72 3 and 72 4 of the demultiplexer 7 are not required for the embodiment of Figure 10, since they are irrelevant to the function of the switch 4.
  • the multiplexer 6 is responsible for the signal forwarding from the respective active master 2, to the first slave S 1 and the demultiplexer 7 for the signal forwarding from the last slave 3 n to the respective active master 2.
  • a functional block 11 of the switch 4 is connected between the multiplexer 6 and the demultiplexer 7.
  • the functional block 11 registers at an input 13 a switching signal 10 and then sends at its output 15 a control signal 100 (routing control signal Sig_Route m t), which consists of two bits.
  • the functional block 11 toggles via its output 15 and on via a data node o / the low-order bit of the control signal 100 and sends the control signal 100 to the input 63 of the multiplexer 6 and to the input 73 of the demultiplexer 7.
  • the value of the high-order bit of the control signal 100 is for the embodiment of the device with the simple Changeover according to FIG. 10 irrelevant. However, the high order bit of the control signal 100 is relevant to the secure switching embodiment (see FIG. 13). In each case one of the two possible values for the value of the low-order bit of the control signal 100 stands for the simple switching from the first master 2 ⁇ to the second master 2 2 , in the embodiment according to Figure 10 this is the value "0" of the two values of the low-order bit of the control signal 100 for the simple switching from the second master 2 2 to the first master 2 U in the embodiment according to FIG. 10, this is the value "1".
  • That master is designated 2i or 2 2 , for which the signal forwarding takes place.
  • the signal forwarding is determined by the switching signal 10 and takes place as shown in the truth tables 1 and 2.
  • the transmitter 43 of the changeover switch 4 is responsible for forwarding the signal 131 from the changeover switch 4 to the first slave 3i, and the inputs 41, are responsible for receiving the signals 122, the changeover switch 4 from the respective master 2.
  • the transmitter 43 is in particular the output of the multiplexer 6 of the changeover switch 4, and the inputs 41 are two out of four inputs of the multiplexer 6 of the changeover switch 4.
  • the receiver 44 of the changeover switch 4 is responsible for receiving the signal 132 of the changeover switch 4 from the last slave 3 ", and the transmitters 42, the changeover switch 4 are responsible for forwarding the respective signals 121 to the respective master 2.
  • the receiver 44 is in particular the input of the demultiplexer 7 of the switch 4 and the transmitters 42 are two out of four outputs of the demultiplexer 7 of the switch 4.
  • the following truth table 2 applies:
  • FIG. 9 a simple switching from master 2 ⁇ to master 2 2 by means of the switch 4 of the simple embodiment of the device according to the invention is shown in FIG.
  • the initial state 200 is "Route_Master_1" according to FIG. 9.
  • the control signal 100 at the input 63 of the multiplexer 6 has the value "00".
  • the multiplexer 6 is configured to receive the signals 122 ⁇ from the first master 2i as signal 131 to the first one Slave 3i, on the condition that the control signal 100 has the value "00", according to Zeii Ie Z1 the truth table 1.
  • the demultiplexer 7 is configured so that it receives the signals 132 from the last slave 3 n as a signal 12I 1 to the first Master 2 ⁇ also under the condition that the control signal 100 has the value "00", according to row Z1 of the truth table 2 forwards.
  • a switching signal 10 (switch signal) at the switch input 13 of the functional block 11 is represented by the upper arrow 10 in the state diagram of FIG. 9 and triggers a state transition to the state 200 "Route_Master_2" according to FIG.
  • the final state 200 is "Route_Master_2.”
  • the control signal 100 at the input 63 of the multiplexer 6 has the value "01".
  • the multiplexer 6 is configured to pass the signals 122 2 from the second master 2 2 as the signal 131 to the first slave 3i under the condition that the control signal 100 is "01" according to the row Z2 of the truth table 1.
  • the demultiplexer 7 is configured to forward the signals 132 from the last slave 3 n as signal 121 2 to the second master 2 2, also under the condition that the control signal 100 has the value "01", according to row Z 2 of the truth table 2.
  • the switch 4 of the device according to the invention for a safe switching.
  • six states 200 are necessary.
  • the master 2 X is the currently active master and master 2 y the master to be activated.
  • the changeover switch 4 (not shown in FIG. 11) is initially in the state 200 "Route_Master_x" for the signal forwarding of the respectively active master 2 X to the first slave 3i or from the last slave 3 n to the master 2 X , analogously as already detailed in FIG 9 described.
  • a switchover signal 10 is triggered to the functional block 11 of the changeover switch 4 (see FIG. 13).
  • the changeover signal 10 triggers a transition of the state 200 from "Route_Master_x” to "Detect_MST_x”.
  • the state 200 "Detect_MST_x” is both for the signal forwarding of the master 2 X to the first slave 3i or from the last slave 3 n to the master 2 X and for the search for the time slot of the master synchronization telegram (MST) of the master 2 X and Detecting the cycle time T c of the master 2 X.
  • the ring circuit 1 remains in state 200 "Detect_MST_x” until a master detected signal 190 (Sig_MST_detected ⁇ n t) (see FIG.
  • the master detected signal 190 indicates that the time slot of the master synchronization telegram MST of the still active master 2 X has been found and triggers a transition of the state 200 from "Detect_MST_x" to "Send_MST_CP0_x".
  • the state 200 "Send_MST_CP0_x" is responsible for generating a flying master signal 140 (Sig_FM 0U t) from the functional block 11 to the multiplexer 6 with the phase CPO (see Figure 13) .
  • the flying master signal 140 is one hundred Master synchronization telegrams MST of the still active master 2 X with the phase CPO in the time slot of the last active master 2 X.
  • the MST sent signal 191 also triggers a transition of state 200 from "Send_MST_CP0_x" to "Route_Master_y".
  • the Master 2 y is now fully activated and the Master 2 X completely disabled. It is obvious for any person skilled in the art that more or less than one hundred master synchronization telegrams MST of the still active master 2 X can be sent with the phase CPO, depending on the respective requirement for the time buffer described above, without thereby abandoning the scope of protection of the invention leave.
  • control signal 100 in the respective state 200 are also mentioned in FIG.
  • signals 10, 100, 140, 190 and 191 in the safe switching see the description of FIG. 13.
  • FIG. 12 shows a diagram of the timing of a switching process with any communication phase CPx in the communication cycle n and the communication phase CPO from the communication cycle n + 3, viewed at the transmitter 32 n of the last slave 3 n for the switch 4 of the device 1 according to the invention safe switching.
  • the communication via the bus system 5 takes place as described below.
  • the master 2 X is to be activated and the master 2 y to be activated in the course of the switching process.
  • the state 200 of the ring circuit 1 is "Route_Master_x.”
  • a switching signal 10 is now triggered (switch event) for switching from the master 2 X to the master 2 y by actuation of the changeover switch 4.
  • switching state 10 changes state 200 "Route_Master_x" to "Detect_MST_x” at time T 10 .
  • the switch 4 has detected in the example shown here the time slot of the master synchronization telegram MST from the master 2 X and the cycle time T c of the master 2 X detected.
  • the signal forwarding to the last active master 2 X is now interrupted and the master 2 X is now deactivated.
  • FIG. 13 shows a digital block diagram for a preferred embodiment of the change-over switch 4 of the device according to the invention with a multiplexer 6 and a demultiplexer 7 for the forwarding of the electrical SERCOS signals and with a functional block 11 for the safe switching.
  • the functional block 11 of the change-over switch 4 is used for signal evaluation and generation, also referred to as "signal evaluation.”
  • the functional block 11 controls the multiplexer 6 and the demultiplexer 7 via the control signal 100, as already described in FIG.
  • the functional block 11 essentially corresponds to the evaluation unit 92 of the preferred embodiment according to FIG. 13.
  • the output 14 of the MST transmitter 91 is connected to the two remaining inputs 61 3 and 61 4 of the multiplexer 6 to signal controlled by the control signal 100 signal forwarding of a Flying Master signal 140 (Sig_FM 0U t) of the MST transmitter 91 to ensure the first slave S 1 .
  • a switching signal 10 switch signal
  • the detection of the master synchronization telegram MST in the MST detector 90 is started.
  • the control signal 100 remains unchanged with the value "00" or "01” according to FIG. 11.
  • the MST detector 90 sends a master detected öignai i9ö (Sig_MST_deieuied) to the Auswertu ⁇ gsei ⁇ heit 92 (Routing Controller or Route Ctrl) and to the MST transmitter 91st
  • the higher-order bit of the control signal 100 is set to the value "1" by the evaluation unit 92 and the lower-order bit remains unchanged by the master-detected signal 190.
  • the control signal 100 takes the values "10" and "11” according to FIG. on, and the flying master signal 140 is forwarded via the output 14 to the inputs 61 3 and 61 4 and then on to the first slave S 1 according to lines Z3 and Z4 of Table 3.
  • the MST transmitter 91 active , 2 2 no signal is forwarded to the master 2, and 2 according to the lines Z3 and Z4 of the following table 4.
  • the drives 31, the slaves 3, can now be shut down.
  • the MST transmitter 91 sends an MST sent signal 191 to the evaluation unit 92 (routing controller), which then resets the high-order bit of the control signal 100 to the value "0" and the low-order bit is inverted, whereby the signals 122 y of the respective other master 2 y , to the first slave 3 i, and the signals 132 of the last slave 3 n , respectively, are forwarded to the respective other master 2 y Value "00" or "01" and switching from the Master 2 X to the other Master 2 y is completed.
  • the evaluation unit 92 routing controller
  • the multiplexer 6 for the preferred embodiment of the secure switching device according to the invention has the following truth table 3:
  • the demultiplexer 7 for the preferred embodiment of the device according to the invention with the safe switching has the following truth table 4:
  • the demultiplexer 7 has four outputs ⁇ 2 ⁇ , Al 2 , 72 3 and 72 4 in the embodiment shown here. However, only the two outputs 42 X are each connected to the input 21 X of the master 2 X , since in the embodiment of the preferred device 1 according to FIG. 13 only two masters 2 X are used. The remaining outputs 72 3 and 72 4 are therefore not connected, that is irrelevant to the function of the switch 4 for this embodiment. However, it will be understood by those skilled in the art that the outputs 72 3 and 72 4 may be connected in an analogous manner to other masters 2 X when more than two masters 2 X are to be incorporated into the ring circuit 1, without departing from the scope of the following claims to leave.
  • corresponding multiplexers 6 and demultiplexers 7 having more inputs 41, or more outputs 42 are to be used, and the functional block 11 of the switch 4 is to be set up with a control signal 100 of more than two bits to be able to map the number of switching options.
  • the output 42i DiiMüiu ⁇ lcXcr 7 is connected to the first master 2i, where the demultiplexer 7 via its output 42 i a signal 121 1 (Sig_M1 0ut ) to the receiver 21 1 of the first master 2, can send.
  • the demultiplexer 7 Via the output 42 2 , the demultiplexer 7 is connected to the second or further master 2 2 , the demultiplexer 7 sending via its output 42 2 a signal 121 2 (Sig_M 2 0U t) to the receiver 21 2 of the second or further master 2 2 can.
  • the initial state 200 is "Route_Master_1" according to Figure 11.
  • the control signal 100 has the value "00".
  • the multiplexer 6 is configured to forward the signals 122i from the first master 2 ⁇ as signals 131 (Sig_S1 out ) to the first slave 3 ⁇ according to row Z1 of the truth table 3.
  • the demultiplexer 7 is configured so that it signals 132 (Sig_Sn in) from the last slave 3 n as signals 121 1 (Sig_M1 O ut) for the first Master 2 ⁇ forwards according to line Z1 of truth Table 4 below.
  • a switching signal 10 arriving at the input 13 of the functional block 11 triggers, according to FIG. 11, a transition of the state 200 from "Route_Master_1" to "Detect_MST_1". As described for FIG. 12, the switching event triggering the switching signal 10 can take place at any time during the communication cycle.
  • the MST detector 90 is active and detected, triggered via a signal 194 (Sig_Ctrl_CM in ) from the output 43 of the multiplexer 6 to the input 12 of the functional block 11, the time slot of the active master 2 X and the length T 0 of a communication cycle.
  • the state 200 "Detect_MST_1” is ended according to FIG. 11 by a master detected signal 190 triggered by an MST detected event, after which a state change into the state 200 "Send_MST_CP0_1" takes place.
  • the drives of the slaves 3 are shut down, for which purpose a flying master signal 140 is generated by the MST transmitter 91.
  • the multiplexer 6 is set such that the generated flying master signal 140 is connected to the first Slave S 1 is forwarded according to line Z3 of Table 3.
  • the demultiplexer 7 is set so that no signal forwarding to the two master 2, according to line Z3 of Table 4.
  • the state 200 "Send_MST_CP0_1” is terminated by an MST sent event. This results in a transition to state 200 "Route_Master_2" according to FIG. 11.
  • the MST sent event triggers an MST sent signal 191, which is sent from the MST transmitter 91 to the evaluation unit 92.
  • the control signal 100 has the value "01".
  • the multiplexer 6 according to line Z2 of Table 3 is configured to forward the signals 122 2 from the second master 2 2 as signals 131 to the first slave 3i.
  • the demultiplexer 7 is configured to forward the signals 132 from the last slave 3 "as signals 121 2 to the second master 2 2 according to row Z2 of Table 4. '
  • the device according to the invention it is possible to switch the SERCOS field bus between two master controllers without a protocol error occurring. For example, tests to redevelop a master controller can be easily performed by switching between the new controller and a reference system using the switcher of the inventive apparatus. Similarly, debugging the commissioning of equipment can be simplified by switching between an already running and the controller to be tested. This can help diagnose and troubleshoot, saving time and money. Hguren i to 13, the state of the art and Austexsforrnen the srfin- dungsdorfen device was shown, which are suitable for the SERCOS I or SERCOS II technology.
  • the newer SERCOS III technology combines the previous advantages of SERCOS with those of the Ethernet, for which a suitable changeover switch 4 must also be specified.
  • the following description of the figures therefore represent embodiments of the device according to the invention which are suitable for the SERCOS III technology and thus also for the known Ethernet technology.
  • FIG. 14 shows a schematic connection view of a simple SERCOS III and Ethernet-suitable embodiment of the device according to the invention.
  • the physical bidirectional circuit 8 has a line topology, viewed from the respective active master 2 ⁇ or 2 2 via the changeover switch 4 according to the invention and further via the slaves 3i, 3 2 , ..., 3 n .
  • the lines of the bidirectional bus system 5 are, for example, copper lines, which forward (biretechnischal) signals in both directions, indicated in Figure 14 by the arrows in both directions per line.
  • the receivers 2I 1 , 21 2 , 3I 1 , 31 2 ,..., 31 n , 4I 1 , 41 2 already described in the preceding figures are configured as duplex ports in the embodiment according to FIG As is known, bidirectional signal forwarding is possible. Thus, these receivers can also be used simultaneously as a transmitter. Correspondingly, conversely, conversely, the transmitters 22 ⁇ 22 2 , 32 !, 32 2 32 n , 43 are also designed as duplex ports and thus also simultaneously usable as a receiver. Due to the bidirectional property of duplex connections, a simple logical ring circuit 1 can be constructed with the respectively active master 2 ⁇ or 2 2 , as shown in FIGS. 15, 16.
  • the changeover switch 4 has one duplex connection 41 j to the respective active master 2, and one duplex connection 43 to the first slave S 1 .
  • FIG. 15 shows a schematic transmission channel view of the bidirectional circuit 8 according to FIG. 14, the principle of the changeover switch 4 being shown as a mechanical switch and the first master 2 1 being active.
  • the bidirectional bus system 5 comprises a logical downlink 81 for one of the two directions of signal forwarding and a logical reverse channel 82 for the reverse direction of the signal forwarding.
  • a logical downlink 81 for one of the two directions of signal forwarding and a logical reverse channel 82 for the reverse direction of the signal forwarding.
  • a logical reverse channel 82 for the reverse direction of the signal forwarding.
  • the signal 132 for the logical return channel 82 is only forwarded by the slaves 3 ", 3 n-1 ,..., 3i. There is no data processing.
  • the channels 81, 82 form a logical ring circuit 1 with the first master 2i.
  • FIG. 16 shows a schematic transmission channel view of the circuit 8 according to FIG. 14, wherein, in contrast to FIG. 15, the second master 2 2 is now active, since the signal forwarding of the logical output channel 81 and of the logical return channel 82 takes place for the second master 2 2 .
  • the channels 81, 82 now form a logical ring circuit 1 with the second master 2 2 .
  • FIG. 17 shows a schematic connection view of a preferred and Ethernet-suitable embodiment of the device according to the invention, wherein the physical bidirectional circuit 8, unlike the embodiment according to FIGS. 14 to 16, has no linear but annular topology and can therefore be used as a double-ring logic circuit 1 , as shown in Figures 18, 19.
  • the switch 4 requires two (instead of one) duplex connectors 41 "42, each master 2, and two (rather than one) duplex connectors 43, 44 for the slaves 3i, 3 2, ... 3 n.
  • FIG. 18 shows a schematic transmission channel view of the circuit according to FIG. 17, the principle of the changeover switch 4 being shown as a mechanical switch and the first master 2i being active.
  • the signal is carried out - forwarding the Hinkanals 81 and the return channel 82 for the first master 2i for the ⁇ first logical ring 1 (primary channel) and the second logical ring 1 (the secondary channel).
  • the signal 132 for the return channel 82 of the respective active ring 1 is forwarded by the slaves 3 1 f 3 2 ,... 3 n . There is no data processing. This results in the logical double ring structure.
  • FIG. 19 shows a schematic transmission channel view of the circuit according to FIG. 17, wherein the second master 2 2 is active.
  • the signal forwarding of the forward channel 81 and the return channel 82 for the second master 2 2 takes place for the first logical ring 1 (primary channel) and the second logical ring 1 (secondary channel).
  • FIG. 20 shows a state diagram with the SERCOS III communication phases for the switchover between two masters 2 1 2 2 with the changeover switch 4 of the simple che or 3ERCO3! L! And Ethernet-suitable embodiment of the device according to the invention for a safe switchover (according to FIGS. 14 to 19).
  • the subscribers change over the error communication paths 64 to the "Com Error" state, from which the subscribers can change to the state CPO via the CPO-Com error communication path 66 State CPO, the communication can be reinitialized (principle of "safe switching"). Therefore, the changeover switch 4 based on the SERCOS III technology must take no further measures for safe switching.
  • Switching is not opto-mechanical in Figure 20 due to the Ethernet-based SERCOS IiI technology.
  • MSTJDPx Master synchronization telegram with arbitrary communication phase CPx
  • MST_M1_CPx Master synchronization telegram of the first master 2 ⁇ with any communication phase CPx
  • MST_M2_CPx Master synchronization telegram of the second or further master 2 2 with any communication phase CPx
  • MST_FM_CPO Master synchronization telegram of the flying master of the changeover switch
  • MST_M2_CP0 Master synchronization telegram of the second or further master 2 2 with communication phase
  • SwJvH 1n optical or electrical signal input 4I 1 of the SERCOS switch 4 for the output signal of the first SERCOS master 2 ⁇
  • Sw_M2, n optical or electrical signal input 41 2 of the SERCOS switch 4 for the output signal of the second or further SERCOS master 2 2 Sw_Sn._; optical or electrical signal input 44 of the SERCOS changeover switch 4 for the output signal of the nth or last SERCOS slave 3 n signal outputs:
  • MI 0Ut optical or electrical signal output 22i of the first SERCOS master 2 ⁇ M2 0Ut : optical or electrical signal output 22 2 of the second or further SERCOS master 2 2
  • Sw_M2 0Ut optical or electrical signal output 42 2 of the SERCOS changeover switch 4 for the input signal of the second or further SERCOS master 2 2 Sw_S1 0Ut : optical or electrical signal output 43 of the SERCOS changeover switch 4 for the input signal of the first SERCOS slave 3i input signals:
  • Sig_M1, n optical or electrical input signal of the SERCOS switch 4, which corresponds to the output signal 122i of the first SERCOS master 2 ⁇ Sig_M2 ⁇ n : optical or electrical input signal of the SERCOS switch 4, which the output signal 122 2 of the second or further SERCOS Masters 2 2 corresponds
  • Sig_Sn ⁇ n optical or electrical input signal of the SERCOS switch 4, which corresponds to the output signal 132 of the nth or last SERCOS slave 3 n output signals: Sig_M1 0Ut : optical or electrical output signal of the SERCOS switch 4, which the input signal 121 1 of first SERCOS masters 2 ⁇ corresponds to Sig_M2 0Ut : optical or electrical output signal of the SERCOS switch 4, which corresponds to the input signal 121 2 of the second SERCOS master 2 2 Sig_S1 0Ut : optical or electrical output signal of the SERCOS switch 4, which is the input signal 131 of the first SERCOS slave 3 ⁇ corresponds to internal modules of the SERCOS switch 4: Mux: Multiplexer 6 (4 inputs to 1 output) Demux: Demultiplexer 7 (1 input to 4 outputs) Ctrl: functional block 11 for controlling the simple or safe switching MST Detector: unit 90 of the functional block 11 for evaluating the signal of active Masters 2,
  • MST transmitter unit 91 of the functional block 11 for generating a SERCOS master signal
  • Route Ctrl unit 92 of the functional block 11 for evaluating the module-internal signals and for controlling the signal forwarding
  • Demux_Route ⁇ n input 73 of the demultiplexer 7 for the control signal of the functional block 11th
  • Ctrl_FM 0U t Output 14 of the functional block 11 for the SERCOS master signal generated by the functional block 11 Internal signals of the SERCOS switch 4:
  • Sig_Route int internal control signal 100 generated by the output 15 (Ctrl_Route ou t), which represents the state of the signal forwarding
  • Sig_FM 0Ut internal electrical flying-master signal 140
  • nt internal master detected signal 190 from the MST detector 90 to the evaluation unit 92 of the functional block 11, the signal representing the MST_detected event during the switching to the output Ctrl_FM ou t 14 of the functional block 11 generated electrical SERCOS master signal
  • Sig_Switch ⁇ n represents Sig_MST_sent int : internal signal 191 from the MST transmitter 91 to the evaluation unit 92 of the functional block 11, which represents the MST_sent event during the switching

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Abstract

La présente invention concerne un dispositif et un procédé pour la commutation au choix d'au moins deux maîtres (21, 22) pour au moins un esclave attribué (31, 32,...,3n), respectivement un des deux maîtres ou plus (21, 22) et les esclaves (31, 32,...,3n) étant reliés par au moins un circuit en boucle logique (1) par l'intermédiaire d'un système de bus (5), un commutateur (4) échangeant au choix le maître actif respectif dans le circuit en boucle (1) contre un autre des deux maîtres ou plus (21, 22) dans le circuit en boucle. Ainsi, le commutateur (4) est réalisé comme un circuit numérique.
PCT/EP2009/000039 2008-01-07 2009-01-07 Dispositif et procédé de commutation sélective de deux maîtres pour des esclaves attribués dans un circuit en boucle logique WO2009087090A1 (fr)

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DE102008003317 2008-01-07
DE102008037610A DE102008037610A1 (de) 2008-01-07 2008-11-28 Vorrichtung und Verfahren zur wahlweisen Umschaltung zweier Master für zugeordnete Slaves
DE102008037610.8 2008-11-28

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US9196153B2 (en) * 2013-05-10 2015-11-24 The Boeing Company Remote wireless motor control law processing system
US9806658B2 (en) 2014-03-06 2017-10-31 The Boeing Company Wirelessly powered electric motor
CN111182659B (zh) * 2019-12-16 2023-04-07 深圳市共进电子股份有限公司 一种Mesh设备的模式切换方法、模式切换装置及Mesh设备
DE102020127804B4 (de) 2020-10-22 2022-05-05 Beckhoff Automation Gmbh Automatisierungssystem mit einer Master-Slave-Struktur und Verfahren zur Telegrammübertragung

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US20040008720A1 (en) * 2002-07-10 2004-01-15 I/O Controls Corporation Redundant multi-fiber optical ring network
US20050232145A1 (en) * 2004-04-15 2005-10-20 Cooper Cameron Corporation Systems and methods of providing redundant communication to an electronic device
DE102004055330A1 (de) * 2004-11-16 2006-05-24 Bosch Rexroth Aktiengesellschaft Verfahren und Vorrichtung zum Betreiben eines Netzwerkes
DE102006018884A1 (de) * 2006-04-24 2007-10-25 Beckhoff Automation Gmbh Schnittstelleneinheit und Kommunikationssystem mit einer Master-Slave-Struktur

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US20040008720A1 (en) * 2002-07-10 2004-01-15 I/O Controls Corporation Redundant multi-fiber optical ring network
US20050232145A1 (en) * 2004-04-15 2005-10-20 Cooper Cameron Corporation Systems and methods of providing redundant communication to an electronic device
DE102004055330A1 (de) * 2004-11-16 2006-05-24 Bosch Rexroth Aktiengesellschaft Verfahren und Vorrichtung zum Betreiben eines Netzwerkes
DE102006018884A1 (de) * 2006-04-24 2007-10-25 Beckhoff Automation Gmbh Schnittstelleneinheit und Kommunikationssystem mit einer Master-Slave-Struktur

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