WO2009081289A1 - Semiconductor storage device, operating and manufacturing thereof - Google Patents

Semiconductor storage device, operating and manufacturing thereof Download PDF

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Publication number
WO2009081289A1
WO2009081289A1 PCT/IB2008/053442 IB2008053442W WO2009081289A1 WO 2009081289 A1 WO2009081289 A1 WO 2009081289A1 IB 2008053442 W IB2008053442 W IB 2008053442W WO 2009081289 A1 WO2009081289 A1 WO 2009081289A1
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Prior art keywords
storage device
semiconductor
field effect
effect transistor
semiconductor storage
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PCT/IB2008/053442
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French (fr)
Inventor
Nader Akil
Michiel Van Duuren
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Nxp B.V.
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Publication of WO2009081289A1 publication Critical patent/WO2009081289A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell

Definitions

  • the invention relates to a semiconductor storage device with a semiconductor body comprising a semiconductor region of a first conductivity type and first and second semiconductor surface zones of a second opposite conductivity type forming a channel region and source and drain regions of a field effect transistor, an electrically insulating layer through which charge carrier can tunnel being present on a surface of said semiconductor region, a first conducting layer being present on the insulating layer which is totally surrounded by electrically insulating material for storing charge of which at least a part forms a floating gate of the field effect transistor and a second conducting layer being present of which at least a part forms a control gate of the field effect transistor which control gate is capacitively coupled to the floating gate,
  • the invention also relates to a method of operating such a storage device and to a method of manufacturing such a storage device.
  • a device as mentioned in the opening paragraph is known from the United States Patent that has been published under number US 4,019,197 that has been published on April 19, 1977. In this document it is stated that rather high voltages were required for recording and erasing information in prior art storage devices.
  • the control gate was formed as a semiconductor region sunken in the semiconductor body. In this way the area of said control gate could be increased compared to prior art devices in which the control gate is on top of the floating gate and viewed in projection coincides with the latter. This allows for a large coupling between the two relevant capacitors formed between semiconductor body, floating gate and control gate and in this way reading, programming and erasing the storage device requires moderate voltages.
  • a disadvantage of the known device is that its area is relatively large.
  • CMOS Complimentary Metal Oxide Semiconductor
  • a semiconductor storage device of the type described in the opening paragraph is characterized in that the first and second conductive layers are coplanar and are sufficiently close to each to obtain a capacitively coupling between the floating gate and the control gate.
  • the cell size of such a storage device would be relatively large since well-to-well distance is relatively large and thus dominates the total memory cell area which cannot be scaled well below 20-25 square micron.
  • the invention is based on the recognition that forming floating gate and control gate coplanar on the one hand allows for a sufficiently large coupling between the relevant capacities to allow for very low operating voltages of the storage device while on the other hand two MOS transistors, i.e. a storage transistor and a selection transistor can be manufactured within one single well thus allowing for a moderate surface area of a memory cell.
  • the first conducting layer is strip shaped and the second conducting layer borders the first conducting layer along the largest part of its length direction.
  • the second conducting layer borders the first conducting layer on opposite sites along its length direction.
  • Maximum coupling is possible if the control gates also borders the floating gate along its two opposite smaller side faces. In this way one could say that the control gate practically surrounds the floating gate.
  • the cell size can be in the order of 1,5 square micron.
  • a semiconductor storage device preferably comprises a further field effect transistor with an access gate formed in a further conducting layer and functioning to select the field effect transistor for programming and erasing.
  • the field effect transistor and the further field effect transistor are formed within a single well of a CMOS process. It is to be noted that a further field effect transistor can be present for each field effect transistor. However it is also possible that only one selection further field effect transistor is present in a bit line. The selection transistor may also be used for reading the storage device.
  • first, second and further conducting layers are formed within a single layer comprising polycrystalline silicon.
  • CHE and PAHH being the preferred methods for respectively erasing and programming a semiconductor storage device according to the present invention.
  • the semiconductor storage device further comprises a voltage source used for reading, programming and erasing the storage device, characterized in that the voltage source provides an electric potential having an absolute value in a range between 2V and 8V and in particular a value of less than or equal to about 6,5 V.
  • the voltage on the floating gate is about 3V.
  • a 90 nm device technology with an oxide thickness of about 6.5 nm implies a suitable operating voltage on the floating gate of about half this value, i.e. 3.25 Volt.
  • About three volt on the floating gate is sufficient for a practical programming window when CHE and PAHH are used.
  • the present invention realizes that in order to allow usage of a storage device according to the invention at the above mentioned moderate voltage conditions, a design of a coplanar floating and control gate is possible having a coupling coefficient that is suitable to obtain these results.
  • a method of manufacturing a semiconductor storage device wherein within a semiconductor body a semiconductor region of a first conductivity type and first and second semiconductor surface zones of a second opposite conductivity type are formed which form a channel region and source and drain regions of a field effect transistor, an electrically insulating layer through which charge carrier can tunnel being formed on a surface of said semiconductor region, a first conducting layer being formed on the insulating layer which is totally surrounded by electrically insulating material for storing charge of which at least a part forms a floating gate of the field effect transistor and a second conducting layer being formed of which at least a part forms a control gate of the field effect transistor which control gate is capacitively coupled to the floating gate, is according to the present invention, characterized in that the first and second conductive layers are formed coplanar and are sufficiently close to each to obtain a capacitively coupling between the floating gate and the control gate. In this way a semiconductor storage device according to the invention is obtained.
  • the method is very suitable for integration into a common low voltage CMOS technology.
  • Figure 1 shows in projection an embodiment of a semiconductor storage device according to the invention
  • Figure 2 shows a part of a memory array of memory cells comprising the semiconductor storage device of figure 1
  • Figure 3 shows a cross-section perpendicular to the thickness direction of the semiconductor storage device of figure 1 and along the line III-III
  • Figure 4 shows a cross-section perpendicular to the thickness direction the semiconductor storage device of figure 1 and along the line IV-IV.
  • Figure 5 to 13 show a cross-section perpendicular to the thickness direction the semiconductor storage device of figure 1 in subsequent stages of its manufacturing using a method of manufacturing according to the invention, the cross-section of figures 3, 5, 6, 8, 10 and 12 begin along the line III-III in figure 1 and the cross-section of figures 4, 7, 9, 11 and 13 being along the line IV-IV in figure 1,
  • Figure 14 shows in projection a further embodiment of a semiconductor storage device according to the invention
  • Figure 15 shows endurance characteristics that are possible when using CHE and PAHH for operating a semiconductor storage device according to the invention
  • Figure 16 shows the control gate coupling coefficient and the cell size for a semiconductor storage device according to the invention in function of the length of the floating gate.
  • Figure 1 shows a cross-section perpendicular to the thickness direction of a first embodiment of a semiconductor sensor device 10 according to the invention.
  • the active region 15 has a first connection regions 16 and a second connection region 17 of respectively source and drain regions.
  • the first FET comprises an access gate 9 and the second FET comprises a floating gate 6.
  • the floating gate 6 is substantially surrounded by a control gate 8.
  • Both gates, floating gate 6 and control gate 8 are formed within a single polycrystalline silicon layer on top of an insulating layer and the control gate 8 is connected to a metal layer 81 through a further insulating layer.
  • both gates, floating gate 6 and control gate 8 are formed coplanar and are capacitively well coupled thanks to a small distance A of 140 nm in the present case and thanks to the fact that the control gate 8 virtually surrounds the complete floating gate 6.
  • the storage device 10 according to the invention may be operated at low voltages of about 3 V. Erasing is done by the PAHH method and programming is done using CHE, which is explained in more detail below.
  • Figure 2 shows a part of a memory array of memory cells comprising the semiconductor storage device 10 of the above embodiment.
  • Part 22 of the memory matrix corresponds substantially with what has been shown in figure 1.
  • Floating gate 6 and access gate 9 are strip-shaped as in figure 1.
  • the two parts of the control gate 8 that surround a floating gate 6 are H-shaped. In this way the control gate parts can be shared by memory cells both below and above the memory cell 22.
  • Memory cells below and above in this context means adjacent or adjoining cells arranged in substantially the same plane or level of the matrix.
  • Figure 3 shows a cross-section perpendicular to the thickness direction of the semiconductor storage device of figure 1 and along the line HI-III.
  • Figure 4 shows a cross-section perpendicular to the thickness direction the semiconductor storage device of figure 1 and along the line IV-IV. These figures show a semiconductor region 1 that forms the channel regions 4 of both FETs.
  • STI Shallow Trench Isolation
  • regions 50 comprising silicon dioxide.
  • Above the channel region 4 a tunnel oxide or a gate oxide region 5 is present.
  • both FETs may have a different thickness for the gate oxide 5 in this example this is not the case.
  • Both floating gate 6 and control gate 8 are laterally bordered by spacers 7 of an insulating material such as silicon dioxide or silicon nitride.
  • Source/drain regions 21, 2, 3 comprise in this example shallow and lightly doped extensions that border the channel region.
  • the device 10 of this example may be manufactured as follows with a method according to the present invention.
  • the semiconductor region 1 is a p-type well in an n-type silicon substrate, the latter not being shown in the drawing. Accordingly, source and drain regions 21, 2, 3 are of the N+ conductivity type and both FETs are NMOSFETs.
  • Figure 5 to 13 show a cross-section perpendicular to the thickness direction the semiconductor storage device of figure 1 in subsequent stages of its manufacturing using a method of manufacturing according to the invention.
  • the cross-section of figures 5, 6, 8, 10 and 12 are taken along the line HI-III in figure 1.
  • the cross-section of figures 1, 9, 11 and 13 are taken along the line IV-IV in figure 1.
  • n+ type silicon substrate (not shown in the drawing) in which - among others - a p-type well 1 is formed.
  • STI regions 50 are formed and filled with silicon dioxide.
  • the surface of the silicon region 1 is oxidized using a thermal oxidation by which an insulating layer comprising silicon dioxide is formed on top of the silicon region 1.
  • CVD Chemical Vapor Deposition
  • the polycrystalline layer 6 is patterned and etched into floating gate 6, control gate 8 and access gate 9. Photolithography and etching are used in this phase. Etching is done using Plasma etching.
  • spacers 7 are formed that laterally border the gates 6, 8, 9 and n+ type ion implantations are done to form source/drain regions 21, 2, 3.
  • the shallow part of these regions is formed before the formation of the spacers 7, the deeper parts after formation of the spacers 7, the latter thus forming part of an implantation mask that is formed by the gate regions 6,9.
  • a further insulating layer e.g. of silicon dioxide is deposited over the resulting structure, e.g. by CVD.
  • contact windows formed in the latter metal plugs can be present that contact source/drain regions or a gate region to a metal layer or metal pattern on top of the latter further insulating layer.
  • components may be formed in the semiconductor body 11 in the same Io w- voltage CMOS process used to form the memory. Such components can be active or passive, and may form other circuitry such as logic or such as used to form a voltage source for operating the storage device 10.
  • Figure 14 shows in projection a further embodiment of a semiconductor storage device according to the invention.
  • the figure shows the essential elements of the first example such as floating gate 6, control gate 8 and access gate 9 and active region 15 with source/drain connections 16, 17.
  • the main difference with the first embodiment is that both floating gate 6 and control gate 8 show a meandering structure in which fingers of the floating gate 6 are interdigited with fingers of the control gate 8.
  • the control gate 8 practically surrounds the floating gate 6. Since for the same surface area, floating gate 6 and control gate 8 border each other along a much greater length than in the first example a relatively high CG coupling coefficient is obtainable in this example.
  • a defined first logical state may be assumed by the memory cell, so that after the programming procedure the programmed memory cell enduringly or permanently remains in this first logical state.
  • a current value between the source/drain terminals is indicative of the first logical state which may be identified as a value "1".
  • a control unit For programming the memory cell to assume the first logical state, a control unit is adapted for applying a first electric potential to the drain terminal to accelerate electrons in a channel region to thereby generate negatively charged accelerated electrons in the substrate.
  • the control unit is further adapted for simultaneously applying a second electric potential to the gate terminal to attract the accelerated electrons towards the gate terminal to thereby inject the electrons in the charge trapping structure after transmission through a gate insulating layer.
  • the gate and drain are not applied simultaneously but with a certain shift in the pulse duration, like first generate the inversion region (electrons in the channel) by rising the gate voltage, and then start to accelerate the electrons by rising the drain voltage.
  • the first electric potential may be +5V.
  • the second electric potential may be +5V as well.
  • the accelerated electrons may be injected in the charge trapping structure after tunnelling through the gate oxide layer made of silicon oxide material.
  • the thickness "d" of the gate oxide layer may be more than 3 nm, for instance may be 5 nm.
  • a third electric potential may be applied to the source terminal of the memory cell to accelerate the electrons between the source/drain terminals.
  • the control unit is adapted for applying a forth electric potential to the drain terminal to accelerate electrons in the channel region to thereby generate positively charged holes by impact ionisation of the accelerated electrons in the substrate.
  • the control unit is further adapted for (simultaneously or subsequently) applying a fifth electric potential to the gate terminal to accelerate the generated holes to thereby inject the positively charged holes in the charge trapping structure after transmission through the gate insulating layer.
  • the forth electric potential may be +5V.
  • the fifth electric potential may be -5V.
  • the generated hot holes may be injected in the charge trapping structure after tunnelling through the gate oxide layer.
  • a sixth electric potential may be applied to a source terminal to accelerate the electrons between the source and drain terminals.
  • a defined second logical state may be assumed by the memory cell (i.e. the cell may be brought to the second logical state), so that after the programming procedure the programmed memory cell enduringly or permanently remains in this second logical state.
  • a current value between the source/drain terminals is indicative of the second logical state, which in this example may be identified as a value "0".
  • channel hot electrons injection may be combined with punch-through assisted hot holes (PAHH) injection.
  • PAHH punch-through assisted hot holes
  • Such an architecture may allow to obtain a programming scheme for thick bottom oxide SONOS, wherein the programming may be done with hot holes generated with low voltages ( ⁇ 5V), while erasing does not require conventional high voltage Fowler Nordheim injection (-+12V).
  • both program and erase mechanisms may be done with low voltages ( ⁇ 5V) to avoid high voltage processing to save masks and enable ultra- low cost embedded non- volatile memory in advanced CMOS generations .
  • the memory transistor for instance a SONOS transistor
  • the memory transistor may be a punching transistor, that is to say a transistor with electrons flowing from source to drain even when the transistor is off, or even when a negative voltage is applied to the gate.
  • Hot holes may be generated in such a punching channel by impact ionisation events of electrons flowing from source to drain deep below the interface. Some or all of the generated hot holes may be accelerated by the gate field to be injected in the charge trapping layer to have a symmetrically programmed charge trapping layer such as a silicon nitride layer. Compared to localized injection procedures, the punch-through assisted hot holes may improve the endurance. Particularly, a voltage difference between source and drain may be adjusted appropriately to accelerate electrons from the source to the drain, or vice versa, producing the impact ionisation.
  • the invention is in particular based on the recognition to provide a poly non- volatile memory device where the Vt of the memory device is increased by using CHE injection mechanism and decreased by using PAHH mechanism.
  • Figure 15 shows endurance characteristics that are possible when using CHE and PAHH for operating a semiconductor storage device according to the invention.
  • the endurance characteristics are of a FG miniarray (128 cells) using CHE and PAHH but of device in which floating gate and control gate are stacked and have the same area.
  • the coupling between control gate 8 and floating gate 6 is about 0,65.
  • +/- 3 V on the floating gate is sufficient to have a good programming window when CHE and PAHH are used in a device according to the invention.
  • the punch-through assisted hot holes (PAHH) injection mechanism to be used to erase the memory cell of the present invention may make use of a 3rd poly gate (AG) in the cell.
  • the AG transistor is in series with the memory transistor and it should be slightly open during PAHH erase.
  • the AG should be used to limit the bitline current during erase, which is advantageous for the reliability of the cell.
  • Figure 16 shows the control gate coefficient and the cell size for a semiconductor storage device according to the invention in function of the length of the floating gate.
  • Curve 160 represent the cell- size *0.1 square micron and curve 162 gives the control gate coupling coefficient.
  • Relevant parameters are as indicated in figure 1 and in a layout as shown in figure 2:
  • A the distance between poly FG and poly CG
  • B the distance between poly CG and active
  • C the distance between poly CG and Poly access gate (AG)
  • D the extension of poly FG on STI (one side)
  • E the active width
  • An embodiment of the invention may be based on the recognition that the PAHH mechanism preferably requires a low voltage on the FG to decrease the Vt of the memory cell, a structure which has a relatively bad coupling, like a poly-poly capacitor, but easy the process to couple few volts ( ⁇ 3V) to the FG.
  • the coupling coefficient between CG and FG of the cell of figures 1 and 2 and the cell area 22 (figure 2) has been calculated using cmos65 design rules and the results are depicted in figure 16. For a 60nm FG length, the CG coupling coefficient would be 0.46 and the cell size ⁇ 1.5 ⁇ m 2 .

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Abstract

The invention relates to a semiconductor storage device (10) with a semiconductor body (11) comprising a semiconductor region (1) of a first conductivity type and first and second semiconductor surface zones (2,3) of a second opposite conductivity type forming a channel region (4) and source and drain regions (2,3) of a field effect transistor, an electrically insulating layer (5) through which charge carrier can tunnel being present on a surface of said semiconductor region (1), a first conducting layer (6) being present on the insulating layer (5) which is totally surrounded by electrically insulating material (7) for storing charge of which at least a part forms a floating gate (6) of the field effect transistor and a second conducting layer (8) being present of which at least a part forms a control gate (8) of the field effect transistor which control gate (8) is capacitively coupled to the floating gate (6). According to the invention the first and second conductive layers (6,8) are coplanar and are sufficiently close to each to obtain a capacitively coupling between the floating gate (6) and the control gate (8). The invention furthers comprises a method of operating and a method of manufacturing such a storage device.

Description

SEMICONDUCTOR STORAGE DEVICE , OPERATING AND MANUFACTURING THEREOF
FIELD OF THE INVENTION
The invention relates to a semiconductor storage device with a semiconductor body comprising a semiconductor region of a first conductivity type and first and second semiconductor surface zones of a second opposite conductivity type forming a channel region and source and drain regions of a field effect transistor, an electrically insulating layer through which charge carrier can tunnel being present on a surface of said semiconductor region, a first conducting layer being present on the insulating layer which is totally surrounded by electrically insulating material for storing charge of which at least a part forms a floating gate of the field effect transistor and a second conducting layer being present of which at least a part forms a control gate of the field effect transistor which control gate is capacitively coupled to the floating gate, The invention also relates to a method of operating such a storage device and to a method of manufacturing such a storage device.
BACKGROUND OF THE INVENTION
Such a storage device is very suitable for many applications and as such will be present arranged in rows and columns in devices requiring non- volatile memory. They are e.g. known as E(E)PROM = Electrically (Erasable and) Programmable Read Only Memory. Storage of charge on the floating gate allows the threshold voltage (VT) to be electrically altered between a low and a high value to represent logic 0 and 1 , respectively.
A device as mentioned in the opening paragraph is known from the United States Patent that has been published under number US 4,019,197 that has been published on April 19, 1977. In this document it is stated that rather high voltages were required for recording and erasing information in prior art storage devices. In the device of the before mentioned patent the control gate was formed as a semiconductor region sunken in the semiconductor body. In this way the area of said control gate could be increased compared to prior art devices in which the control gate is on top of the floating gate and viewed in projection coincides with the latter. This allows for a large coupling between the two relevant capacitors formed between semiconductor body, floating gate and control gate and in this way reading, programming and erasing the storage device requires moderate voltages. A disadvantage of the known device is that its area is relatively large. Using intermediate values for the coupling between the control gate and the floating gate allows for a reduction but such a memory cell remains relatively large. Moreover, in order to be manufacturable in a low voltage CMOS (= Complimentary Metal Oxide Semiconductor) technology, still lower erasing and/or programming voltages, e.g. of around 3V (on the floating gate), are required.
OBJECT AND SUMMARY OF THE INVENTION
It is therefore an object of the present invention to avoid the above drawbacks and to provide a semiconductor storage device, which occupies a small surface area and can be operated at very moderate voltages and is manufacturable in low voltage CMOS technology.
To achieve this, a semiconductor storage device of the type described in the opening paragraph is characterized in that the first and second conductive layers are coplanar and are sufficiently close to each to obtain a capacitively coupling between the floating gate and the control gate. The present invention is based on the following surprising recognitions. Firstly that suitable very low voltage programming and erasing methods are CHE (= Channel Hot Electrons)-injections (also abreviated as CHEI) and PAHH (= Punch-through Assisted Hot Holes) requiring the use of an additional MOS transistor for selecting the storage transistor that is e.g. to be programmed or erased. In a device following the teaching of the prior art, which device comprises two well regions, such an additional transistor could be positioned in one of the two wells. However, the cell size of such a storage device would be relatively large since well-to-well distance is relatively large and thus dominates the total memory cell area which cannot be scaled well below 20-25 square micron. Finally, the invention is based on the recognition that forming floating gate and control gate coplanar on the one hand allows for a sufficiently large coupling between the relevant capacities to allow for very low operating voltages of the storage device while on the other hand two MOS transistors, i.e. a storage transistor and a selection transistor can be manufactured within one single well thus allowing for a moderate surface area of a memory cell.
In a preferred embodiment the first conducting layer is strip shaped and the second conducting layer borders the first conducting layer along the largest part of its length direction. In this way a relatively large coupling can be obtained for the smallest distance between both gates that is possible in a state of the art CMOS process. Preferably, the second conducting layer borders the first conducting layer on opposite sites along its length direction. Maximum coupling is possible if the control gates also borders the floating gate along its two opposite smaller side faces. In this way one could say that the control gate practically surrounds the floating gate. A CG (= Control Gate) coupling coefficient between 0.3 and 0.5 is possible for a lateral distance between control gate and floating gate of about 140 nm. This allows for operating voltages on the floating gate of the storage device that are about 3 Volt, e.g. between 2.5 and 3.5 Volt. The cell size can be in the order of 1,5 square micron.
In accordance with the above a semiconductor storage device according to the invention preferably comprises a further field effect transistor with an access gate formed in a further conducting layer and functioning to select the field effect transistor for programming and erasing. Preferably the field effect transistor and the further field effect transistor are formed within a single well of a CMOS process. It is to be noted that a further field effect transistor can be present for each field effect transistor. However it is also possible that only one selection further field effect transistor is present in a bit line. The selection transistor may also be used for reading the storage device.
In a further preferred embodiment the first, second and further conducting layers are formed within a single layer comprising polycrystalline silicon. In this way a single poly floating gate non- volatile memory is obtained that is programmable and erasable by CHE and PAHH. The latter being the preferred methods for respectively erasing and programming a semiconductor storage device according to the present invention.
Preferably the semiconductor storage device further comprises a voltage source used for reading, programming and erasing the storage device, characterized in that the voltage source provides an electric potential having an absolute value in a range between 2V and 8V and in particular a value of less than or equal to about 6,5 V. The latter implies that the voltage on the floating gate is about 3V. This holds for a 90 nm device technology with an oxide thickness of about 6.5 nm which implies a suitable operating voltage on the floating gate of about half this value, i.e. 3.25 Volt. About three volt on the floating gate is sufficient for a practical programming window when CHE and PAHH are used. For a 45 nm device technology, the oxide thickness may be as low as 5 nm which implies that the voltage on the floating gate is about (5/2=) 2.5 Volt. The present invention realizes that in order to allow usage of a storage device according to the invention at the above mentioned moderate voltage conditions, a design of a coplanar floating and control gate is possible having a coupling coefficient that is suitable to obtain these results. The coupling coefficient, also referred to as CG (= Control Gate) coupling coefficient, being the ratio of the CG to FG (= Floating Gate) capacity and the FG to semiconductor region capacity. A method of manufacturing a semiconductor storage device wherein within a semiconductor body a semiconductor region of a first conductivity type and first and second semiconductor surface zones of a second opposite conductivity type are formed which form a channel region and source and drain regions of a field effect transistor, an electrically insulating layer through which charge carrier can tunnel being formed on a surface of said semiconductor region, a first conducting layer being formed on the insulating layer which is totally surrounded by electrically insulating material for storing charge of which at least a part forms a floating gate of the field effect transistor and a second conducting layer being formed of which at least a part forms a control gate of the field effect transistor which control gate is capacitively coupled to the floating gate, is according to the present invention, characterized in that the first and second conductive layers are formed coplanar and are sufficiently close to each to obtain a capacitively coupling between the floating gate and the control gate. In this way a semiconductor storage device according to the invention is obtained. The method is very suitable for integration into a common low voltage CMOS technology.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter, to be read in conjunction with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows in projection an embodiment of a semiconductor storage device according to the invention,
Figure 2 shows a part of a memory array of memory cells comprising the semiconductor storage device of figure 1 , Figure 3 shows a cross-section perpendicular to the thickness direction of the semiconductor storage device of figure 1 and along the line III-III,
Figure 4 shows a cross-section perpendicular to the thickness direction the semiconductor storage device of figure 1 and along the line IV-IV.
Figure 5 to 13 show a cross-section perpendicular to the thickness direction the semiconductor storage device of figure 1 in subsequent stages of its manufacturing using a method of manufacturing according to the invention, the cross-section of figures 3, 5, 6, 8, 10 and 12 begin along the line III-III in figure 1 and the cross-section of figures 4, 7, 9, 11 and 13 being along the line IV-IV in figure 1, Figure 14 shows in projection a further embodiment of a semiconductor storage device according to the invention,
Figure 15 shows endurance characteristics that are possible when using CHE and PAHH for operating a semiconductor storage device according to the invention, and Figure 16 shows the control gate coupling coefficient and the cell size for a semiconductor storage device according to the invention in function of the length of the floating gate.
The figures are diagrammatic and not drawn to scale, the dimensions in the thickness direction being particularly exaggerated for greater clarity. Corresponding parts are generally given the same reference numerals and the same hatching in the various figures.
DESCRIPTION OF EMBODIMENTS
Figure 1 shows a cross-section perpendicular to the thickness direction of a first embodiment of a semiconductor sensor device 10 according to the invention. The device 10 comprises in this example a silicon substrate forming a semiconductor body 11, which contains an active region 15 comprising from left to right: a source region, a channel region, a common source drain region, another channel region and a drain region of two FETs (= Field Effect Transistors), i.e. a first FET and a second FET, in series. The active region 15 has a first connection regions 16 and a second connection region 17 of respectively source and drain regions. The first FET comprises an access gate 9 and the second FET comprises a floating gate 6. The floating gate 6 is substantially surrounded by a control gate 8. Both gates, floating gate 6 and control gate 8 are formed within a single polycrystalline silicon layer on top of an insulating layer and the control gate 8 is connected to a metal layer 81 through a further insulating layer. Thus both gates, floating gate 6 and control gate 8 are formed coplanar and are capacitively well coupled thanks to a small distance A of 140 nm in the present case and thanks to the fact that the control gate 8 virtually surrounds the complete floating gate 6. Thus, the storage device 10 according to the invention may be operated at low voltages of about 3 V. Erasing is done by the PAHH method and programming is done using CHE, which is explained in more detail below. Figure 2 shows a part of a memory array of memory cells comprising the semiconductor storage device 10 of the above embodiment. Part 22 of the memory matrix corresponds substantially with what has been shown in figure 1. Floating gate 6 and access gate 9 are strip-shaped as in figure 1. The two parts of the control gate 8 that surround a floating gate 6 are H-shaped. In this way the control gate parts can be shared by memory cells both below and above the memory cell 22. Memory cells below and above in this context means adjacent or adjoining cells arranged in substantially the same plane or level of the matrix.
Figure 3 shows a cross-section perpendicular to the thickness direction of the semiconductor storage device of figure 1 and along the line HI-III.
Figure 4 shows a cross-section perpendicular to the thickness direction the semiconductor storage device of figure 1 and along the line IV-IV. These figures show a semiconductor region 1 that forms the channel regions 4 of both FETs. In the storage FET (storage FET never mentioned/defined before ???) the channel region 4 is bordered by isolation regions, here in the form of STI (= Shallow Trench Isolation) regions 50 comprising silicon dioxide. Above the channel region 4 a tunnel oxide or a gate oxide region 5 is present. Although both FETs may have a different thickness for the gate oxide 5 in this example this is not the case. Both floating gate 6 and control gate 8 are laterally bordered by spacers 7 of an insulating material such as silicon dioxide or silicon nitride. On top of both gates 6, 8 is a further insulating layer, not shown in the drawing, through which contact regions 25 are arranged to contact the control gate 8 and the first contact region 16 and the second contact region 17 contact the source and drain regions 21 (2) and 3 of the access and storage FETs. Source/drain regions 21, 2, 3 comprise in this example shallow and lightly doped extensions that border the channel region. The device 10 of this example may be manufactured as follows with a method according to the present invention. In this example the semiconductor region 1 is a p-type well in an n-type silicon substrate, the latter not being shown in the drawing. Accordingly, source and drain regions 21, 2, 3 are of the N+ conductivity type and both FETs are NMOSFETs.
Figure 5 to 13 show a cross-section perpendicular to the thickness direction the semiconductor storage device of figure 1 in subsequent stages of its manufacturing using a method of manufacturing according to the invention. The cross-section of figures 5, 6, 8, 10 and 12 are taken along the line HI-III in figure 1. The cross-section of figures 1, 9, 11 and 13 are taken along the line IV-IV in figure 1.
Starting point is (see figures 5, 6 and 7) an n+ type silicon substrate (not shown in the drawing) in which - among others - a p-type well 1 is formed. In the latter STI regions 50 are formed and filled with silicon dioxide. Subsequently the surface of the silicon region 1 is oxidized using a thermal oxidation by which an insulating layer comprising silicon dioxide is formed on top of the silicon region 1. Subsequently (see figures 8 and 9) a polycrystalline silicon layer 6 is deposited on the surface of the semiconductor body by means of CVD (= Chemical Vapor Deposition). Next (see figures 10 and 11) the polycrystalline layer 6 is patterned and etched into floating gate 6, control gate 8 and access gate 9. Photolithography and etching are used in this phase. Etching is done using Plasma etching.
Finally (see figures 12 and 13) spacers 7 are formed that laterally border the gates 6, 8, 9 and n+ type ion implantations are done to form source/drain regions 21, 2, 3. The shallow part of these regions is formed before the formation of the spacers 7, the deeper parts after formation of the spacers 7, the latter thus forming part of an implantation mask that is formed by the gate regions 6,9. After this a further insulating layer, e.g. of silicon dioxide is deposited over the resulting structure, e.g. by CVD. In contact windows formed in the latter metal plugs can be present that contact source/drain regions or a gate region to a metal layer or metal pattern on top of the latter further insulating layer.
Other components may be formed in the semiconductor body 11 in the same Io w- voltage CMOS process used to form the memory. Such components can be active or passive, and may form other circuitry such as logic or such as used to form a voltage source for operating the storage device 10.
Figure 14 shows in projection a further embodiment of a semiconductor storage device according to the invention. The figure shows the essential elements of the first example such as floating gate 6, control gate 8 and access gate 9 and active region 15 with source/drain connections 16, 17. The main difference with the first embodiment is that both floating gate 6 and control gate 8 show a meandering structure in which fingers of the floating gate 6 are interdigited with fingers of the control gate 8. In this way, again the control gate 8 practically surrounds the floating gate 6. Since for the same surface area, floating gate 6 and control gate 8 border each other along a much greater length than in the first example a relatively high CG coupling coefficient is obtainable in this example.
Next, it will be explained how programming may be done in the memory cell by performing a defined channel hot electron injection procedure. With such a procedure (which may also be applied simultaneously to some or all memory cells of a memory array), a defined first logical state may be assumed by the memory cell, so that after the programming procedure the programmed memory cell enduringly or permanently remains in this first logical state. Thus, when sampling the memory content by applying a read voltage to the gate terminal and a test voltage between the source/drain terminals, a current value between the source/drain terminals is indicative of the first logical state which may be identified as a value "1".
For programming the memory cell to assume the first logical state, a control unit is adapted for applying a first electric potential to the drain terminal to accelerate electrons in a channel region to thereby generate negatively charged accelerated electrons in the substrate. The control unit is further adapted for simultaneously applying a second electric potential to the gate terminal to attract the accelerated electrons towards the gate terminal to thereby inject the electrons in the charge trapping structure after transmission through a gate insulating layer. Instead of simultaneously applying the above potentials, it is possible that the gate and drain are not applied simultaneously but with a certain shift in the pulse duration, like first generate the inversion region (electrons in the channel) by rising the gate voltage, and then start to accelerate the electrons by rising the drain voltage.
For instance, the first electric potential may be +5V. The second electric potential may be +5V as well. By applying these voltages, the accelerated electrons may be injected in the charge trapping structure after tunnelling through the gate oxide layer made of silicon oxide material. The thickness "d" of the gate oxide layer may be more than 3 nm, for instance may be 5 nm.
During this programming procedure, a third electric potential may be applied to the source terminal of the memory cell to accelerate the electrons between the source/drain terminals. For programming the memory cell to bring it into a second logical state (which is complementary or inverse to the first logical state value), the control unit is adapted for applying a forth electric potential to the drain terminal to accelerate electrons in the channel region to thereby generate positively charged holes by impact ionisation of the accelerated electrons in the substrate. The control unit is further adapted for (simultaneously or subsequently) applying a fifth electric potential to the gate terminal to accelerate the generated holes to thereby inject the positively charged holes in the charge trapping structure after transmission through the gate insulating layer.
For instance, the forth electric potential may be +5V. The fifth electric potential may be -5V. By applying these voltages, the generated hot holes may be injected in the charge trapping structure after tunnelling through the gate oxide layer. For programming, a sixth electric potential may be applied to a source terminal to accelerate the electrons between the source and drain terminals.
As a consequence of the described impact ionisation procedure for inserting holes in the charge trapping structure, a defined second logical state may be assumed by the memory cell (i.e. the cell may be brought to the second logical state), so that after the programming procedure the programmed memory cell enduringly or permanently remains in this second logical state. Thus, when sampling the memory content by applying a read voltage to the gate terminal and a test voltage between the source/drain terminals, a current value between the source/drain terminals is indicative of the second logical state, which in this example may be identified as a value "0".
According to an exemplary embodiment of the invention, channel hot electrons injection (CHEI) may be combined with punch-through assisted hot holes (PAHH) injection. Such an architecture may allow to obtain a programming scheme for thick bottom oxide SONOS, wherein the programming may be done with hot holes generated with low voltages (~5V), while erasing does not require conventional high voltage Fowler Nordheim injection (-+12V). According to an exemplary embodiment of the invention, both program and erase mechanisms may be done with low voltages (~5V) to avoid high voltage processing to save masks and enable ultra- low cost embedded non- volatile memory in advanced CMOS generations .According to an exemplary embodiment of the invention, the memory transistor (for instance a SONOS transistor) may be a punching transistor, that is to say a transistor with electrons flowing from source to drain even when the transistor is off, or even when a negative voltage is applied to the gate.
Hot holes may be generated in such a punching channel by impact ionisation events of electrons flowing from source to drain deep below the interface. Some or all of the generated hot holes may be accelerated by the gate field to be injected in the charge trapping layer to have a symmetrically programmed charge trapping layer such as a silicon nitride layer. Compared to localized injection procedures, the punch-through assisted hot holes may improve the endurance. Particularly, a voltage difference between source and drain may be adjusted appropriately to accelerate electrons from the source to the drain, or vice versa, producing the impact ionisation.
The invention is in particular based on the recognition to provide a poly non- volatile memory device where the Vt of the memory device is increased by using CHE injection mechanism and decreased by using PAHH mechanism.
Figure 15 shows endurance characteristics that are possible when using CHE and PAHH for operating a semiconductor storage device according to the invention. The endurance characteristics are of a FG miniarray (128 cells) using CHE and PAHH but of device in which floating gate and control gate are stacked and have the same area. The coupling between control gate 8 and floating gate 6 is about 0,65. The FG voltages used in figure 15 during CHE is Vcg*0.65 = 4*0.65 = + 2.6 V, and during PAHH is Vcg*0.65 = - 5*0.65 = - 3.25 V. Thus, it can be assumed that +/- 3 V on the floating gate is sufficient to have a good programming window when CHE and PAHH are used in a device according to the invention.
In an embodiment, the punch-through assisted hot holes (PAHH) injection mechanism to be used to erase the memory cell of the present invention may make use of a 3rd poly gate (AG) in the cell. The AG transistor is in series with the memory transistor and it should be slightly open during PAHH erase. The AG should be used to limit the bitline current during erase, which is advantageous for the reliability of the cell.
Figure 16 shows the control gate coefficient and the cell size for a semiconductor storage device according to the invention in function of the length of the floating gate. Curve 160 represent the cell- size *0.1 square micron and curve 162 gives the control gate coupling coefficient. Relevant parameters are as indicated in figure 1 and in a layout as shown in figure 2:
A: the distance between poly FG and poly CG B: the distance between poly CG and active C: the distance between poly CG and Poly access gate (AG) D: the extension of poly FG on STI (one side) E: the active width
F: the CG poly length G: the FG poly length
The results of figure 16 have been obtained using the following data for a device according to the present invention. The FG extension over active D = 140nm, Wactive E = 80nm, the CG length is F = 140nm as well as the CG-FG distance A. Remaining cell parameters are taken as follow: B = 50nm, C = 250nm, AG length = 280nm, AG-common source distance = 140nm, AG-CG distance = 250nm, common source width = 400nm, horizontal distance between CG and BL contact = 125nm, distance between two neighboring CG = 250nm, oxide thickness 5.5nm.
An embodiment of the invention may be based on the recognition that the PAHH mechanism preferably requires a low voltage on the FG to decrease the Vt of the memory cell, a structure which has a relatively bad coupling, like a poly-poly capacitor, but easy the process to couple few volts (~3V) to the FG. The coupling coefficient between CG and FG of the cell of figures 1 and 2 and the cell area 22 (figure 2) has been calculated using cmos65 design rules and the results are depicted in figure 16. For a 60nm FG length, the CG coupling coefficient would be 0.46 and the cell size ~1.5μm2. Assuming reasonably that the maximum voltage that we can handle in cmos65 (with cascoding I/O transistors) is -6.5V, would mean 6.5*0.46=3 V. This means that when the design of figures 1 and 2 is used, we will be able to couple ± 3 V to the FG and if we use CHE and PAHH as program and erase mechanisms we would be able to have a large programming window (see fig.15) with a cell size of ~1.5μm2.
It will be obvious that the invention is not limited to the examples described herein, and that within the scope of the invention many variations and modifications are possible to those skilled in the art.
Furthermore it is noted that various modifications are possible with respect to individual manufacturing steps. For example other deposition techniques can be selected instead of those used in the example

Claims

CLAIMS:
1. Semiconductor storage device (10) with a semiconductor body (11) comprising a semiconductor region (1) of a first conductivity type and first and second semiconductor surface zones (2, 3) of a second, opposite conductivity type forming a channel region (4) and source and drain regions (2, 3) of a field effect transistor, an electrically insulating layer (5) through which charge carrier can tunnel being present on a surface of said semiconductor region (1), a first conducting layer (6) being present on the insulating layer (5) which is totally surrounded by electrically insulating material (7) for storing charge of which at least a part forms a floating gate (6) of the field effect transistor and a second conducting layer (8) being present of which at least a part forms a control gate (8) of the field effect transistor, which control gate (8) is capacitively coupled to the floating gate (6), characterized in that the first and second conductive layers (6, 8) are coplanar and are sufficiently close to each to obtain a capacitively coupling between the floating gate (6) and the control gate (8).
2. Semiconductor storage device (10) according to claim 1, wherein the first conducting layer (6) is strip shaped, characterized in that the second conducting layer (8) borders the first conducting layer (6) along the largest part of its length.
3. Semiconductor storage device (10) according to claim 2, characterized in that the second conducting layer (8) borders the first conducting layer (6) on opposite sites along the largest part of its length and preferably substantially surrounds the first conducting layer (6).
4. Semiconductor storage device (10) according to any of the claims 1, 2 or 3, characterized in that the semiconductor storage device comprises a further field effect transistor with an access gate (9) comprising a further conducting layer (9) functioning to select the field effect transistor for programming and erasing.
5. Semiconductor storage device (10) according to claim 4, characterized in that the field effect transistor and the further field effect transistor are formed within a single well (l) ofa CMOS process.
6. Semiconductor storage device according to claim 4 or 5, characterized in that the first, second and further conducting layers (6,8,9) are formed within a single layer (6) comprising polycrystalline silicon.
7. Semiconductor storage device (10) according to any one of the preceding claims, further comprising a voltage source used for reading, programming and erasing the storage device, characterized in that the voltage source provides an electric potential having an absolute value in a range between 2 V and 8 V and in particular a value of less than or equal to about 6.5 V.
8. Semiconductor storage device (10) according to claim 7, characterized in that the erasing is done by punch-through assisted hot holes injection and the programming is done by hot electrons injection.
9. Semiconductor storage device (10) according to anyone of the preceding claims, characterized in that the semiconductor body of the device also comprises electronic circuitry and that the memory of the storage device thus forms an embedded memory.
10. Method of operating a semiconductor storage device (10) according to any one of the preceding claims, wherein the operating comprises the steps of programming and erasing, characterized in that the erasing is done by punch-through assisted hot holes injection and the programming is done by hot electrons injection.
11. Method of manufacturing a semiconductor storage device (10) wherein within a semiconductor body (11) a semiconductor region (1) of a first conductivity type and first and second semiconductor surface zones (2,3) of a second opposite conductivity type are formed which form a channel region (4) and source and drain regions (2,3) of a field effect transistor, an electrically insulating layer (5) through which charge carrier can tunnel being formed on a surface of said semiconductor region (1), a first conducting layer (6) being formed on the insulating layer (5) which is totally surrounded by electrically insulating material (7) for storing charge of which at least a part forms a floating gate (6) of the field effect transistor and a second conducting layer (8) being formed of which at least a part forms a control gate (8) of the field effect transistor which control gate (8) is capacitively coupled to the floating gate (6), characterized in that the first and second conductive layers (6,8) are formed coplanar and are sufficiently close to each to obtain a capacitively coupling between the floating gate (6) and the control gate (8).
PCT/IB2008/053442 2007-12-20 2008-08-27 Semiconductor storage device, operating and manufacturing thereof WO2009081289A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137724A (en) * 1998-04-01 2000-10-24 National Semiconductor Corporation Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages
US20030203575A1 (en) * 2002-04-29 2003-10-30 Powerchip Semiconductor Corp. Single-poly eprom and method for forming the same
US20060079054A1 (en) * 2004-10-08 2006-04-13 Samsung Electronics Co., Ltd. Non-volatile memory device and methods of forming the same
US20070166912A1 (en) * 2006-01-04 2007-07-19 Tower Semiconductor Ltd. Three-dimensional control-gate architecture for single poly EPROM memory devices fabricated in planar CMOS technology
US7276759B1 (en) * 2004-03-11 2007-10-02 Nanostar Corporation Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6137724A (en) * 1998-04-01 2000-10-24 National Semiconductor Corporation Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages
US20030203575A1 (en) * 2002-04-29 2003-10-30 Powerchip Semiconductor Corp. Single-poly eprom and method for forming the same
US7276759B1 (en) * 2004-03-11 2007-10-02 Nanostar Corporation Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling
US20060079054A1 (en) * 2004-10-08 2006-04-13 Samsung Electronics Co., Ltd. Non-volatile memory device and methods of forming the same
US20070166912A1 (en) * 2006-01-04 2007-07-19 Tower Semiconductor Ltd. Three-dimensional control-gate architecture for single poly EPROM memory devices fabricated in planar CMOS technology

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