WO2009067950A1

WO2009067950A1 - Management method and device of shared memory in multi-core system

Info

Publication number: WO2009067950A1
Application number: PCT/CN2008/073148
Authority: WO
Inventors: Dingchun Chen
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2007-11-29
Filing date: 2008-11-21
Publication date: 2009-06-04
Also published as: CN101246466B; CN101246466A

Abstract

A management method and device of shared memory in a multi-core system are provided. The method concretely includes the following steps: a globally shared memory and a locally shared memory are allocated in the multi-core system; all the CPUs in the multi-core system can access the globally shared memory, and a part of the CPUs in the multi-core system can access the locally shared memory.

Description

Description Method and device for managing shared memory in multi-core system

[I] This application claims the priority of the Chinese Patent Application entitled "Management Method and Device for Shared Memory in Multi-core System" submitted by the Chinese Patent Office on November 29, 2007, with the application number of 200710178405.4, the entire contents of which are The bow I is used in conjunction with this application.

[2] Technical field

[3] The present invention relates to the field of computer applications, and in particular, to a method and apparatus for managing shared memory in a multi-core system.

[4] Background of the invention

[5] At present, in today's electronics, communications and IT industries, whether it is an embedded system or a general-purpose computer system, the limitations of single-core processors are becoming more and more obvious, and users are increasingly unable to meet high-performance, high-capacity Claim. So multi-core, ie multi-CPU (Central Processing

The technology of Unit, Central Processing Unit has emerged as the times require, and it has been continuously developed and matured. The scope of application in the market is rapidly expanding. Multi-core technology has become an inevitable trend in the elimination of traditional single-core technology.

[6] Multi-core memory management technology is a key technology in multi-core technology. The whole system architecture depends on it. Its performance directly affects the performance and competitiveness of multi-core processors. One of the prior technologies The memory management method is as follows: Memory is not supported between multiple cores. When communicating between multiple cores, it is necessary to copy the memory contents multiple times.

[7] Figure 1 shows the schematic diagram of the communication between two CPUs in the solution. The specific processing flow includes the following steps:

[8] Step 1. CPU1 applies for a memory block from its own memory space;

[9] Step 2. CPU1 constructs a data packet, which contains the communication contents of CPU1 and CPU2;

[10] Step 3. The CPU 1 carries the above data packet in the requested memory block, and sends the data packet to the communication line between the CPU 1 and the CPU 2;

[I I] Step 4. CPU1 releases the memory block of the above application, so that the memory block is reused;

[12] Step 5. The above data packet is transmitted to the CPU 2 through the communication line;

[13] Step 6. CPU2 applies for a memory block from its own memory space; [14] Step 7. The CPU 2 reads the above data packet from the communication line, and the data packet is stored in the memory block applied by itself;

[15] Step 8. CPU2 processes the above data packet;

[16] Step 9. After processing the above data packet, CPU2 releases the requested memory block and the communication ends.

[17] Summary of the invention

[18] The embodiment of the invention provides a method and a device for managing shared memory in a multi-core system, which can support shared memory to be freely transferred between CPUs, greatly reducing the probability of shared memory access conflicts, and effectively improving the multi-core system. performance.

[19] The embodiment of the present invention provides a method for managing shared memory in a multi-core system, including:

[20] Configuring global shared memory and locally shared memory in a multi-core system; wherein all central processing CPUs in the multi-core system are capable of accessing the global shared memory, part of the multi-core system

The CPU is capable of accessing the locally shared memory;

[21] The CPU in the multi-core system carries information through the global shared memory and locally shared memory

[22] The embodiment of the present invention further provides a management device for sharing memory in a multi-core system, including:

[23] a global shared memory configuration module, configured to configure global shared memory in a multi-core system, wherein all CPUs in the multi-core system can access the global shared memory;

[24] A local shared memory configuration module, configured to configure locally shared memory in a multi-core system, wherein a portion of the CPUs in the multi-core system can access the locally shared memory.

[25] It can be seen from the technical solutions provided by the above embodiments that the global shared memory and the locally shared memory are configured in a multi-core system. It can support shared memory freely transfer between CPUs, which greatly reduces the probability of shared memory access conflicts and effectively improves the performance of multi-core systems.

[26] BRIEF DESCRIPTION OF THE DRAWINGS

[27] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings to be used in the embodiments will be briefly described below. Obviously, the drawings in the following description are only the present drawings. Some embodiments of the invention may be obtained by those of ordinary skill in the art from the drawings without departing from the scope of the invention.

[28] FIG. 1 is a schematic diagram of a principle of communication between two CPUs in the prior art; 2 is a schematic diagram of memory sharing in which multiple sharing modes coexist according to Embodiment 1 of the present invention; FIG. ₃ is a schematic diagram of a principle of dividing a global shared area and a local shared area implemented by memory mapping according to Embodiment 1 of the present invention;

₄ is a schematic diagram of transferring a memory block between multiple cores according to Embodiment 1 of the present invention;

FIG ₅ a schematic view of the utilization of a variety of types of shared memory according to a second embodiment of the invention; FIG. ₆ one kind of memory according to a second embodiment of the matching processing based on the flowchart of the present invention, the minimum matching principle; Figure _{7 is} FIG. ₈ is a schematic structural diagram of a multi-core memory sharing processing apparatus according to Embodiment 4 of the present invention.

Mode for carrying out the invention

In the process of implementing the present invention, the inventors have found that at least the following problems exist in the prior art: Since memory cannot be transferred between multiple cores, the communication process is quite complicated, and the memory application and release overhead are also large; and the more complicated the communication process is, The greater the overhead, the lower the system performance, and the new requirements of cutting-edge technologies such as multi-core chips and multi-core operating systems.

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Embodiments of the present invention propose global sharing (Global Shared) and local sharing (Local)

Shared) A memory sharing technique that coexists with multiple sharing methods. The following various sharing methods are introduced separately.

Global sharing: Global shared memory is accessible from the perspective of access rights. Local sharing: Local shared memory From the perspective of access rights, only some CPUs can access, other CPUs cannot access;

Full sharing: Fully shared memory from the perspective of operational rights, the access to the CPU can be fully controlled; semi-shared: semi-shared memory from the perspective of operational permissions, the access to the CPU only partial permissions, such as readable but not writeable, Use memory but cannot apply for memory, etc.

According to the foregoing various sharing manners, the embodiment of the present invention configures the above-mentioned global shared memory in a multi-core system. And locally shared memory.

[45] Moreover, global fully shared and global semi-shared memory is configured in the global shared memory, and all CPUs in the multi-core system can completely control the global fully shared memory, and part of the CPU in the multi-core system The global semi-shared memory can be fully controlled, while other CPUs can only partially control the global semi-shared memory.

[46] Also, local fully shared and locally semi-shared memory is configured in the locally shared memory, and a part of CPUs in the multi-core system capable of accessing the locally shared memory can completely complete the locally fully shared memory. Controlling, a particular CPU of a portion of the CPU capable of accessing the locally shared memory, is capable of full control of the locally semi-shared memory.

[47] Embodiments of the present invention configure the global shared memory and the locally shared memory of various length types according to the lengths of various service data packets in the multi-core system. When there are multiple types of global shared memory and/or locally shared memory in a multi-core system that can be used to carry the same type of service data packet, select the smallest shared type of global shared memory and/or the free memory in the locally shared memory. A memory block to carry the service data packet.

[48] In the embodiment of the present invention, the global shared memory carrying the service data packet is transferred between the CPUs, and the global shared memory is released by the CPU that last uses the global shared memory. Simultaneously, the multicast data packet is carried in the global shared memory, the address information of the multicast data packet is copied into multiple copies, and the multiple address information is separately sent to each destination CPU; Address information

And obtaining the service data packet from the global shared memory.

[00] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[50] Embodiment 1 is shown in FIG. 2, which is a schematic diagram of memory sharing in which multiple sharing modes are provided in the first embodiment.

The principle of coexistence of the multiple sharing modes is to divide the memory sharing area into several sub-areas, and flexibly set the access rights and read-write rights of each sub-area to achieve the purpose of coexistence of multiple sharing modes.

[51] As shown in FIG. 2, according to the CPU application model, the shared memory is divided into a plurality of global shared areas and local shared areas, and the division of the global shared area and the local shared area is related to the service distribution on each CPU. The global shared area allows all CPU access, and the local shared area allows partial (one or several) CPU access, and each local shared area cannot access each other. [52] As shown in Figure 2, local shared area 1 only allows CPU1 and CPU2 access, local shared area m only allows CPUn access, and global shared area allows all CPUs (CPU 1 - CPUn) to access. Therefore, by dividing the shared memory area into a global shared area and a local shared area, the possibility of multi-CPU competition can be reduced, and all the original CPU competitions become partial CPU competition or no competition at all (one CPU exclusive local shared area).

[53] According to the operation authority of each CPU that can access the memory area, a certain local shared area or a global shared area can be further subdivided into a full shared area and a semi-shared area. As shown in Figure 2, the shared area of the local shared area 1, C PU1 and CPU2 can be fully controlled, and the semi-shared area of the local shared area 1, CPU1 has only partial operational rights, CPU2 can be fully controlled; local shared area m Full shared area, CPUn can be fully controlled, and the shared area m is a semi-shared area. CPUn has only partial operation rights; the shared area of the global shared area, all CP Us can be completely controlled, and the semi-shared area of the global shared area, CPU1~CPUn-l only have partial operation rights, and CPUn can be fully controlled.

[54] Therefore, by dividing the global shared area or the local shared area accessible by multiple CPUs into a full shared area and a semi-shared area, and clarifying the operation authority of each CPU, the multi-CPU competition can be further reduced, in the semi-shared area, The CPU operates according to its own permissions, allowing only one CPU to have full control.

[55] The foregoing methods for coexisting multiple sharing modes can be applied to multiple application scenarios in a multi-core system. For example, application scenario 1 allocates separate code segments and data segments for each CPU, and each CPU does not mutually exclusive access to its own. Data segment; Application scenario 2, only one CPU is allowed to modify the heartbeat count value, and other CPUs only read the heartbeat count value.

[56] The schematic diagram of the division principle of the global shared area and the local shared area implemented by the memory mapping provided in the first embodiment is shown in FIG. 3.

[57] Assume a generic MIPS (Microprocessor without Interlocked Pipeline)

Stages, microprocessor without internal interlocking flow level) There are 32 CPUs in a multi-core system of the architecture. CPU 0 is responsible for controlling maintenance services. CPU1 and CPU2 are responsible for multicast processing and MAC layer messaging. CPU3-CPU31 can be independent. Handle voice and data services. Since each CPU works independently, it is necessary to divide ₃₂ independent code segments and data segments (local shared areas) in the shared memory for each CPU to process the service; in addition, communication between the CPUs is required, and the memory needs to be in the CPU. Inter-pass, therefore, also need to divide a multi-core communication segment (global shared area) in the shared memory. [58] In the first embodiment, the division of the global shared area and the local shared area may be implemented by a memory mapping, where the memory mapping refers to a conversion relationship between a virtual address and a physical address. In the multi-core processor of the MIPS architecture, the CPU accesses the memory by using a virtual address. As shown in FIG. 3, on the CPU, the same virtual address space is mapped to different physical memory, and a local shared area can be realized. On CPU0, the accessed data segment is the portion indicated by the solid arrow; on the CPU 31, the accessed data segment is the portion indicated by the dashed arrow. Similarly, on each CPU, mapping the same virtual address space to the same physical memory can implement a global shared area, such as the multi-core communication segment in FIG.

[59] Each CPU accesses its own code segment and data segment, and does not need to be mutually exclusive. This achieves the goal of reducing memory access conflicts as much as possible, thereby improving the performance of multi-core systems. Multi-core processors can provide relevant hardware implementation memory mapping, and memory mapping can also be implemented by software.

[60] In a multi-core system, since multiple cores need to communicate with each other and also support memory transfer between multiple cores, the dynamic memory pool must be deployed in the global shared area, so that all CPUs can apply in the dynamic memory pool. The memory is released, and the requested memory is also visible to other CPUs and can be used to transfer between CPUs.

[61] A schematic diagram of a memory block transferred between multiple cores according to Embodiment 1 is shown in FIG.

[62] As shown in FIG. 4, in the global shared area, a private memory pool is established for each CPU in a software manner, where the private is relative, not other CPUs cannot access, but refers to the private memory. The owner of the pool can apply for and release memory, while other CPUs can only use and release, but do not apply for permission. Therefore, the private memory pool is a semi-shared memory area. Peer, considering that if you need to create a private memory pool for each CPU, you need more memory, and in the case of sudden traffic, there is a risk of insufficient resources. Therefore, in the global shared area, a common memory pool is created, which is a full shared area.

[63] How much private memory pool and common memory pool are set to achieve a balance between resources and efficiency. In practice, an approximation principle can be used: Set up about 80% of memory under normal business conditions. The operation takes place in a private memory pool. The specific configuration can be adjusted according to the actual business model.

[64] In the above-mentioned memory sharing mode of full sharing and semi-sharing, in most cases, the CPU can apply for memory in its own private memory pool, and only in a few cases, will it apply for memory in the public memory pool. Therefore, the conflict of multiple CPU peers applying for memory will become very small, and the invention reduces the shared memory. The purpose of the access conflict.

[65] Since the multi-core communication segment is located in the global shared area, all CPUs can access the area, and the memory blocks in the private memory pool of each CPU can be arbitrarily transferred between the multi-cores, and the end-release principle is adopted, and the last used memory block is used. The CPU releases the memory block back to the CPU that first applied for the memory block. As shown in Figure 4, the memory block requested by CPU0 can be transferred between other CPUs, and the CPU (CPU1) that last used the memory block releases the memory block back to CPU0's private memory pool. The above method of transferring memory blocks between multiple cores can realize 0 copies of communication between multiple cores, thereby avoiding multiple copies of communication contents.

[Embodiment 2] This embodiment provides a diversified design of a shared memory type in a multi-core system, and can configure a corresponding memory type and a number of memory blocks according to specific service requirements, and automatically select an appropriate memory to carry and transmit service data. , improve memory utilization.

[67] Assuming that there are multiple service types in a multi-core system, each service has a different packet length, and the largest packet length is 1024 bytes. Then the shared memory can be configured to be 32 bytes, 64 bytes, 128. Bytes, 256 bytes, 512 bytes, 1024 bytes, etc., and according to the actual business model, allocate a certain number of memory blocks for various types of memory to form a memory pool. For example, if the number of packets of 128 bytes to 512 bytes accounts for more than 50% of the total traffic, then allocate more memory space for 128 bytes, 256 bytes, and 512 bytes of memory, which is less for other types of memory. Allocate some memory space.

[68] A schematic diagram of utilization of multiple types of shared memory provided in the second embodiment is shown in FIG. 5. As shown in FIG. 5, a 30-byte packet accounts for 20%, and a 500-byte packet accounts for 70%, 1024 bytes of data packets accounted for 10%, the corresponding memory utilization rate was 93.75%, 97.66%, 93.75%, and the weighted memory utilization rate was (20%*9 3.75% + 70 *97.66 + 10%* 100 %) =

97.112%, it can be seen that memory utilization is greatly improved compared to a single memory type.

[69] A flow matching processing flowchart based on the minimum matching principle provided in the second embodiment is shown in FIG. 6. For different service types, quickly select the appropriate memory type through the "Minimum Matching Principle". The specific processing is as follows:

[70] After selecting memory, first determine whether there is memory matching the service data packet in the system. When it is judged that there are multiple types of memory in the system that match the service data packet, select the first memory type with the smallest length. The service data packet is carried. Then, it is further determined whether there is a free memory block in the first memory type, and if yes, selecting a memory block in which the memory block is idle, the memory matching processing flow ends; otherwise, The second memory type of the second smallest length matching the service data packet is continuously selected, and it is continuously determined whether there is a free memory block in the second memory type. The above process is repeated until the free memory block is selected to carry the service data packet.

[71] For example, the service data packet length is 500 bytes. There are two types of memory in the system: 512 bytes and 1024 bytes, which can be used to carry the service data packet. According to the "minimum matching principle", first select 512 words. Section memory, if the 512-byte memory does not have a corresponding free memory block, further select 1024 bytes of memory.

[72] Embodiment 3 is a schematic diagram of a memory level multicast technology provided in this embodiment.

This embodiment is based on memory sharing between multiple cores, and proposes a multicast technology at the memory level. The specific processing process is as follows: After sharing the shared memory area, one or more dedicated multicast pools are opened for the CPU supporting the multicast function, and multicasting is performed. A certain number of multicast message blocks are stored in the pool, such as 4096. The specific quantity depends on the number of multicast services. Each multicast message block includes a multicast packet address, a size domain, and a multicast control domain (such as multicast).

[73] After multicasting between multiple cores, the multicast packets are not copied, but the information of the multicast packets (including the address and its size) is transmitted to the destination through the message channel, and the destination CPU is based on the multicast data. The packet information is obtained and processed.

[74] As shown in Figure 7, CPU1 receives a multicast packet and stores the multicast packet in the memory of the global shared area. Then, the CPU 1 accesses the dedicated multicast pool, requests and constructs a multicast message packet (the multicast message block contains information such as the storage address and size of the multicast data packet), and transmits the constructed multicast message packet to the CPU for each purpose. Then, each destination CPU parses the storage address and the size of the multicast data packet according to the information in the multicast message packet, acquires the multicast data packet according to the storage address, and performs corresponding processing on the multicast packet. In the above process, there is always only one multicast packet, which avoids the process of copying the multicast packet during the multicast process, and improves the multicast processing efficiency.

[75] Embodiment 4 is a schematic structural diagram of a processing device for implementing multi-core memory sharing proposed in this embodiment, as shown in FIG. 8, and includes the following modules:

[76] The global shared memory configuration module is configured to configure global shared memory in a multi-core system, and all CPUs in the multi-core system can access the global shared memory; including: a global fully shared memory configuration module, global semi-shared memory Configure the module. [77] A local shared memory configuration module, configured to configure locally shared memory in a multi-core system, and a portion of CPUs in the multi-core system can access the locally shared memory. Including: local full shared memory configuration module, local semi-shared memory configuration module.

[78] a memory mapping module, configured to map virtual address spaces of respective CPUs to the same physical address space, configure the global shared memory for each CPU; map virtual address spaces of the respective CPUs to different physical address spaces, The locally shared memory is configured for each CPU.

[79] The memory type configuration module is configured to configure, according to the length of the various service data packets, the global shared memory of the respective length types and/or the locally shared memory.

[80] a memory matching processing module, configured to: when there are multiple types of the global shared memory in the multi-core system, and/or the locally shared memory can carry the same type of service data packet, and select the type of the smallest length The global shared memory or the free memory block in the locally shared memory to carry the service data packet.

[81] a memory delivery module, configured to transfer the global shared memory carrying the service data packet between the CPUs, and release the global shared memory by a CPU that last uses the global shared memory

[82] a multicast packet processing module, configured to carry the multicast data packet in a global shared memory, copy the address information of the multicast data packet into multiple copies, and send multiple copies to the plurality of destination CPUs. Address information of the multicast data packet, the plurality of destination CPUs acquiring the multicast data packet from the global shared memory according to the address information.

[83] The global shared memory configuration module in the global shared memory configuration module is configured to configure global fully shared memory in the global shared memory, and all CPUs in the multi-core system can be fully shared by the global Full control of the memory;

[84] The global semi-shared memory configuration module in the global shared memory configuration module is configured to configure global semi-shared memory in the global shared memory, and part of the CPU in the multi-core system can access the global semi-shared memory. Full control is performed, while other CPUs are only able to partially control the global semi-shared memory.

[85] The local shared memory configuration module in the local shared memory configuration module is configured to configure locally fully shared memory in the locally shared memory, and the multi-core system can access the local shared The stored part of the CPU is capable of completely controlling the locally fully shared memory;

[86] The local semi-shared memory configuration module in the local shared memory configuration module is configured to configure local semi-shared memory in the locally shared memory, and a part of the CPU in the multi-core system capable of accessing the locally shared memory The specific CPU in the middle can fully control the local semi-shared memory.

[87] It should be noted that, in the above device embodiment, each unit included is only divided according to functional logic, but is not limited to the above division, as long as the corresponding function can be implemented; The specific names are also for convenience of distinguishing from each other and are not intended to limit the scope of the present invention.

In addition, those skilled in the art can understand that all or part of the steps of the method provided by the embodiments of the present invention can be completed by using hardware related to program instructions. For example, it can be done by computer running. The program can be stored on a readable storage medium such as a random access memory, a magnetic disk, an optical disk, or the like.

[89] In summary, the embodiment of the present invention supports shared memory freely transferred between CPUs, and supports flexible allocation of memory sharing modes on each CPU, thereby realizing multiple memory sharing modes. Therefore, the process of communication between the multi-cores can be simplified, the probability of the shared memory access conflict is greatly reduced, the performance of the multi-core system is improved, and the multi-core communication 拷贝 0 copy can be realized. In the embodiment of the present invention, the memory type is diversified and can be improved. Memory utilization reduces development costs and implements multi-core memory-level multicast technology, which improves multicast processing efficiency and helps improve multi-core system performance.

The above description is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of within the technical scope disclosed by the present invention. Changes or substitutions are intended to be included within the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

Claim

[1] A method for managing shared memory in a multi-core system, comprising:

Configuring global shared memory and locally shared memory in a multi-core system; wherein all central processing units in the multi-core system are capable of accessing the global shared memory, and some CPUs in the multi-core system are capable of accessing the Locally shared memory;

The CPU in the multi-core system is carried by the global shared memory and the locally shared memory

Ι π Λ∑! ,.

[2] The method according to claim 1, wherein the configuring the global shared memory and the locally shared memory in the multi-core system comprises:

Mapping the virtual address space of each CPU in the multi-core system to the same physical address space, and configuring the global shared memory for each CPU;

The virtual address space of each CPU in the multi-core system is mapped to a different physical address space, and the locally shared memory is configured for each CPU.

[3] The method according to claim 1, wherein the configuring the global shared memory and the locally shared memory in the multi-core system comprises:

According to the length of various service data packets in a multi-core system, global shared memory and locally shared memory of various length types are configured.

[4] The method of claim 1 wherein:

The global shared memory includes: globally shared memory and global semi-shared memory; wherein, all CPUs in the multi-core system are capable of completely controlling the globally-shared memory; in the multi-core system Part of the CPU can fully control the global semi-shared memory, while other CPUs can only partially control the global semi-shared memory.

[5] The method according to claim 1, wherein:

The partially shared memory includes: a locally fully shared memory and a locally semi-shared memory; wherein, a part of the CPU in the multi-core system capable of accessing the locally shared memory is capable of performing the locally fully shared memory Full control; a specific CPU in a portion of the _CPUs of the multi-core system capable of accessing the locally shared memory is capable of full control of the locally semi-shared memory.

[6] The method according to any one of claims 1 to 5, wherein the method further comprises: when there are multiple types of global shared memory and/or locally shared memory in the multi-core system The same type of service data packet is used to carry the global shared memory of the smallest type and/or the free memory block in the locally shared memory to carry the service data packet.

[7] The method according to claim 6, wherein the method further comprises:

The global shared memory carrying the service data packet is transferred between the CPUs, and the global shared memory is released by the CPU that last uses the global shared memory.

[8] The method according to claim 6, wherein the method further comprises:

The multicast data packet is carried in the global shared memory, and the address information of the multicast data packet is copied into multiple copies, and the address information is separately sent to each destination CPU;

And each of the destination CPUs obtains the multicast data packet from the global shared memory according to the received address information.

[9] A management device for shared memory in a multi-core system, comprising:

a global shared memory configuration module, configured to configure global shared memory in a multi-core system, wherein all CPUs in the multi-core system can access the global shared memory;

A local shared memory configuration module is configured to configure locally shared memory in a multi-core system, and a portion of the CPUs in the multi-core system can access the locally shared memory.

[10] The device according to claim 9, further comprising:

a memory mapping module, configured to map virtual address spaces of the CPUs to the same physical address space, configure the global shared memory for each CPU, and map virtual address spaces of the CPUs to different physical address spaces, The CPU configures the locally shared memory.

[11] The device according to claim 9, further comprising:

The memory type configuration module is configured to configure global shared memory and/or locally shared memory of various length types according to lengths of various service data packets.

[12] The device according to claim 9, wherein the global shared memory configuration module specifically includes:

a global fully shared memory configuration module, configured to configure global fully shared memory in the global shared memory, where all CPUs in the multi-core system can perform the global fully shared memory fully control;

a global semi-shared memory configuration module, configured to configure global semi-shared memory in the global shared memory, wherein a part of the CPUs in the multi-core system can completely control the global semi-shared memory, and other CPUs can only Partial control of the global semi-shared memory.

[13] The apparatus according to claim 9, wherein the local shared memory configuration module specifically includes:

a local full shared memory configuration module, configured to configure locally fully shared memory in the locally shared memory, where a part of the CPU capable of accessing the locally shared memory in the multi-core system is capable of accessing the locally shared memory Full control;

a local semi-shared memory configuration module, configured to configure local semi-shared memory in the locally shared memory, wherein a specific CPU of the partial CPU capable of accessing the locally shared memory in the multi-core system can Semi-shared memory for full control.

[14] The device according to any one of claims 9 to 13, further comprising:

a memory matching processing module, configured to: when there are multiple types of global shared memory and/or locally shared memory in the multi-core system, can be used to carry the same type of service data packet, select a minimum-type type of global shared memory or A free memory block in the locally shared memory to carry the service data packet.

[15] The device according to claim 14, further comprising:

The memory delivery module is configured to transfer the global shared memory carrying the service data packet between the CPUs, and release the global shared memory by the CPU that last uses the global shared memory.

[16] The device according to claim 14, further comprising:

a multicast packet processing module, configured to carry the multicast data packet in the global shared memory, and copy the address information of the multicast data packet into multiple copies, and separately send the address information to multiple destination CPUs; The plurality of destination CPUs acquire the multicast data packet from the global shared memory according to the received address information.