WO2009058125A3 - Method and apparatus for testing a memory device - Google Patents

Method and apparatus for testing a memory device Download PDF

Info

Publication number
WO2009058125A3
WO2009058125A3 PCT/US2007/082854 US2007082854W WO2009058125A3 WO 2009058125 A3 WO2009058125 A3 WO 2009058125A3 US 2007082854 W US2007082854 W US 2007082854W WO 2009058125 A3 WO2009058125 A3 WO 2009058125A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory device
memory cells
voltage
testing
given
Prior art date
Application number
PCT/US2007/082854
Other languages
French (fr)
Other versions
WO2009058125A2 (en
Inventor
Ross A Kohler
Richard J Mcpartland
Wayne E Werner
Original Assignee
Agere Systems Inc
Ross A Kohler
Richard J Mcpartland
Wayne E Werner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Inc, Ross A Kohler, Richard J Mcpartland, Wayne E Werner filed Critical Agere Systems Inc
Priority to EP07844691A priority Critical patent/EP2208203A2/en
Priority to US12/443,776 priority patent/US8023348B2/en
Priority to KR1020107009401A priority patent/KR101492667B1/en
Priority to JP2010531999A priority patent/JP2011502326A/en
Priority to PCT/US2007/082854 priority patent/WO2009058125A2/en
Publication of WO2009058125A2 publication Critical patent/WO2009058125A2/en
Publication of WO2009058125A3 publication Critical patent/WO2009058125A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.
PCT/US2007/082854 2007-10-29 2007-10-29 Method and apparatus for testing a memory device WO2009058125A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP07844691A EP2208203A2 (en) 2007-10-29 2007-10-29 Method and apparatus for testing a memory device
US12/443,776 US8023348B2 (en) 2007-10-29 2007-10-29 Method and apparatus for testing a memory device
KR1020107009401A KR101492667B1 (en) 2007-10-29 2007-10-29 Method and apparatus for testing a memory device
JP2010531999A JP2011502326A (en) 2007-10-29 2007-10-29 Method and apparatus for testing memory devices
PCT/US2007/082854 WO2009058125A2 (en) 2007-10-29 2007-10-29 Method and apparatus for testing a memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2007/082854 WO2009058125A2 (en) 2007-10-29 2007-10-29 Method and apparatus for testing a memory device

Publications (2)

Publication Number Publication Date
WO2009058125A2 WO2009058125A2 (en) 2009-05-07
WO2009058125A3 true WO2009058125A3 (en) 2009-07-09

Family

ID=40003084

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/082854 WO2009058125A2 (en) 2007-10-29 2007-10-29 Method and apparatus for testing a memory device

Country Status (5)

Country Link
US (1) US8023348B2 (en)
EP (1) EP2208203A2 (en)
JP (1) JP2011502326A (en)
KR (1) KR101492667B1 (en)
WO (1) WO2009058125A2 (en)

Families Citing this family (25)

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Publication number Priority date Publication date Assignee Title
EP2208203A2 (en) 2007-10-29 2010-07-21 Agere Systems, Inc. Method and apparatus for testing a memory device
US8381019B2 (en) 2010-06-24 2013-02-19 International Business Machines Corporation EDRAM macro disablement in cache memory
US8922236B2 (en) * 2010-09-10 2014-12-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and method for inspecting the same
US8804407B1 (en) 2011-07-12 2014-08-12 Altera Corporation PMOS pass gate
JP2013114728A (en) * 2011-11-30 2013-06-10 Toshiba Corp Semiconductor memory device
JP5112566B1 (en) * 2011-12-16 2013-01-09 株式会社東芝 Semiconductor memory device, nonvolatile semiconductor memory inspection method, and program
US8995175B1 (en) 2012-01-13 2015-03-31 Altera Corporation Memory circuit with PMOS access transistors
US9076558B2 (en) * 2012-11-01 2015-07-07 Nanya Technology Corporation Memory test system and memory test method
CN103761174A (en) * 2014-01-21 2014-04-30 浪潮电子信息产业股份有限公司 Design method of marginal test for memory signals in start-up process
KR102389820B1 (en) 2015-09-22 2022-04-22 삼성전자주식회사 Memory controller and memory system controlling training operation and operating method thereof
US10304522B2 (en) * 2017-01-31 2019-05-28 International Business Machines Corporation Method for low power operation and test using DRAM device
US9916890B1 (en) 2017-02-21 2018-03-13 International Business Machines Corporation Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells
US11526768B2 (en) 2017-06-02 2022-12-13 International Business Machines Corporation Real time cognitive reasoning using a circuit with varying confidence level alerts
US10663502B2 (en) 2017-06-02 2020-05-26 International Business Machines Corporation Real time cognitive monitoring of correlations between variables
US10598710B2 (en) 2017-06-02 2020-03-24 International Business Machines Corporation Cognitive analysis using applied analog circuits
US10607715B2 (en) 2017-06-13 2020-03-31 International Business Machines Corporation Self-evaluating array of memory
JP6543324B2 (en) * 2017-12-15 2019-07-10 株式会社メガチップス Information processing system, program, and method for determining authenticity of attached device
US11448692B2 (en) * 2018-08-16 2022-09-20 Taiwann Semiconductor Manufacturing Company Ltd. Method and device for wafer-level testing
US11073551B2 (en) * 2018-08-16 2021-07-27 Taiwan Semiconductor Manufacturing Company Ltd. Method and system for wafer-level testing
US11568951B2 (en) * 2019-03-13 2023-01-31 Texas Instruments Incorporated Screening of memory circuits
CN112309490A (en) * 2019-07-26 2021-02-02 第一检测有限公司 Memory test method
DE102021106795A1 (en) * 2020-10-16 2022-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. METHOD AND APPARATUS FOR WAFER LEVEL TESTING
US20220310620A1 (en) * 2021-03-29 2022-09-29 Micron Technology, Inc. Memory device including calibration operation and transistor having adjustable threshold voltage
EP4258266A4 (en) * 2022-02-18 2024-04-17 Changxin Memory Tech Inc Test method for memory chip and device therefor
TWI834265B (en) * 2022-08-29 2024-03-01 大陸商集創北方（珠海）科技有限公司 Self-testable column driver circuits, display devices and information processing devices

Citations (4)

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US5297087A (en) * 1993-04-29 1994-03-22 Micron Semiconductor, Inc. Methods and devices for accelerating failure of marginally defective dielectric layers
EP0987717A1 (en) * 1998-08-19 2000-03-22 STMicroelectronics, Inc. Method and apparatus for testing dynamic random access memory
US6324108B1 (en) * 2000-02-29 2001-11-27 Advanced Micro Devices, Inc. Application of external voltage during array VT testing
US20040130957A1 (en) * 2003-01-08 2004-07-08 International Business Machines Corp; Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to dram mosfet array transistor

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US4800332A (en) * 1985-03-07 1989-01-24 Texas Instruments Incorporated Reconfigurable integrated circuit with enhanced testability of memory cell leakage
US4816757A (en) 1985-03-07 1989-03-28 Texas Instruments Incorporated Reconfigurable integrated circuit for enhanced testing in a manufacturing environment
JPH09274793A (en) * 1996-04-04 1997-10-21 Kawasaki Steel Corp Dynamic random access memory
JPH10199296A (en) * 1997-01-09 1998-07-31 Mitsubishi Electric Corp Dynamic semiconductor memory device and its test method
JP3112870B2 (en) * 1997-09-26 2000-11-27 日本電気アイシーマイコンシステム株式会社 DRAM
US5949726A (en) * 1998-07-22 1999-09-07 Vanguard International Semiconductor Corporation Bias scheme to reduce burn-in test time for semiconductor memory while preventing junction breakdown
JP2002245795A (en) * 2001-02-19 2002-08-30 Fujitsu Ltd Semiconductor device
US6535439B2 (en) * 2001-05-08 2003-03-18 Micron Technology, Inc. Full stress open digit line memory device
JP4952137B2 (en) * 2006-08-17 2012-06-13 富士通セミコンダクター株式会社 Semiconductor memory and system
KR100802060B1 (en) * 2007-02-02 2008-02-11 삼성전자주식회사 Semiconductor memory device for preventing supply of excessing specific stress item and test method thereof
JP2009053130A (en) * 2007-08-29 2009-03-12 Nec Electronics Corp Semiconductor device
EP2208203A2 (en) 2007-10-29 2010-07-21 Agere Systems, Inc. Method and apparatus for testing a memory device
US8014214B2 (en) * 2007-11-08 2011-09-06 Hynix Semiconductor Inc. Semiconductor memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5297087A (en) * 1993-04-29 1994-03-22 Micron Semiconductor, Inc. Methods and devices for accelerating failure of marginally defective dielectric layers
EP0987717A1 (en) * 1998-08-19 2000-03-22 STMicroelectronics, Inc. Method and apparatus for testing dynamic random access memory
US6324108B1 (en) * 2000-02-29 2001-11-27 Advanced Micro Devices, Inc. Application of external voltage during array VT testing
US20040130957A1 (en) * 2003-01-08 2004-07-08 International Business Machines Corp; Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to dram mosfet array transistor

Also Published As

Publication number Publication date
US20100182859A1 (en) 2010-07-22
KR20100085946A (en) 2010-07-29
WO2009058125A2 (en) 2009-05-07
JP2011502326A (en) 2011-01-20
EP2208203A2 (en) 2010-07-21
KR101492667B1 (en) 2015-02-12
US8023348B2 (en) 2011-09-20

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