WO2009051012A2

WO2009051012A2 - Signal processing circuit for realizing different types of convolutional encoders, scramblers and crc generators

Info

Publication number: WO2009051012A2
Application number: PCT/JP2008/067873
Authority: WO
Inventors: Sheng Wei Chong
Original assignee: Nec Corporation
Priority date: 2007-10-17
Filing date: 2008-09-25
Publication date: 2009-04-23
Also published as: WO2009051012A3

Abstract

In the basic circuit of the signal processing circuit in current invention, by connecting the first input of a selector 11-n of all basic circuits 10 to a common input, and by providing a control circuit connected to output of the selector 11-n, output of a holding circuit and the second input of the selector 14-n, where the control circuit outputs either the output of selector 11-n or the exclusive-OR result of its inputs, arbitrary basic circuits 10 can output the common input or the result of the exclusive-OR operation to multiple inputs of the adjacent basic circuit. Therefore, an array of basic circuits 10 can be separated into arbitrary numbers of sub-arrays with common inputs at flip-flops FF(n-1) and selectors 11-(n-1) of desired basic circuits 10-(n-1), by using arbitrary basic circuits 10-n and not using circuits or arrays that are dedicated for convolutional encoders.

Description

DESCRIPTION

SIGNAL PROCESSING CIRCUIT

[Technical field]

The present invention relates to a signal processing circuit capable of performing circuit operations of convolution encoder, scrambler and CRC (cyclic redundancy check) generator. [Background Art] Baseband processing of many communication standards such as wireless LAN IEEE802.11a and WiMAX IEEE802.16 involves circuit operations of different types of convolutional encoder, scrambler and CRC generator. Examples of convolutional encoders are shown in FIG. 1 and FIG. 2, while examples of a scrambler and a CRC generator are shown in FIG. 3 and FIG. 4, respectively. A circuit that is flexible for the standards should realize different types of convolutional encoder, scrambler and CRC generator.

The following Patent Documents 1 and 2 describe a circuit capable of performing circuit operations of various types of convolutional encoder, scrambler and CRC generator.

The following Non-Patent Document 1 describes a circuit capable of performing circuit operations of various types of convolutional encoder and CRC generator.

Conventionally, each of the convolutional encoder, scrambler and CRC generator is realized using separated programmable circuits. As a result, the total hardware amount required to realize convolutional encoder, scrambler and CRC generator is large. Moreover, hardware utilization of the separated circuits is low if operations of the convolutional encoder, scrambler, and CRC generator are not performed at the same time.

To reduce the total hardware amount mentioned above, in the above Patent Documents 1 and 2 and Non-Patent-Document 1 , convolutional encoder, scrambler, and CRC generator can be realized using a single signal processing circuit. However, the problem of the Patent Document 1 shown in FIG. 5, Patent Document 2 shown in FlG. 6 and Non-Patent-Document 1 shown in FIG. 7 is large hardware amount because they require circuit arrays dedicated for convolutional encoder, and the dedicated circuit arrays are not used in the realization of scrambler and CRC generator. For example, signal processing circuit of Patent Document 2 consists of two identical arrays (81 , 82) as shown in FIG. 6(A) (FIG. 6(A) is redrawn as FIG. 6(B) to illustrate inputs of flip-flops), and one of the arrays is dedicated for convolutional encoder. Dedicated arrays are required for convolutional encoder because the input of convolutional encoders is connected to different EOR circuits (for example, EOR circuits 31 and 32 in FIG. 1) that are realized separately in different said arrays (81 , 82). On the other hand, the input of scrambler and CRC generator is only connected to single EOR circuit (for example, EOR circuits 42 in FIG. 3, EOR circuit 51 in FIG. 4) that is realized in single array.

Moreover, in the above Patent Documents 1 and 2 and Non-Patent- Document 1 , for a convolutional encoder with coding rate 1/R (R is a natural number), the larger the R, the larger the total area required. This is because for coding rate 1/R, the input of convolutional encoder will be connected to R different EOR circuits that are realized separately in R different arrays.

Therefore, R identical arrays are required where R - 1 of them are dedicated for convolutional encoder.

In the above Patent Documents 1 and 2 and Non-Patent-Document 1 , the maximum constraint length of convolutional encoder can be higher than the maximum register length of scrambler and CRC generator. However, in practical baseband processing, to reduce complexity of a Viterbi decoder that decodes output of a convolutional encoder, maximum constraint length of convolutional encoder is 50% less than the maximum register length of CRC generator and scrambler. For example, in practical baseband processing, maximum register length of CRC generator is 32 and maximum constraint length of convolutional encoder is 9.

[Patent Document 1] JP-A-2005-101753(Page 36, FIG. 14) [Patent Document 2] JP-A-2005-341299(Page 15, FIG. 8) [Non-Patent Document 1] S. Leung, A. Postula and A. Hemani, r Development of programmable architecture for base-band processingj , Proceedings of the 26th Euromicro Conference, 5-7 Sept. 2000. Volume 1 , Page(s):362 - 367 vol.1 Page 366, FIG. 3 [Disclosure of the invention]

An object of the present invention is to reduce total area of a single signal processing circuit that can realize various types of convolutional encoders, scramblers and CRC generators.

In the signal processing circuit of current invention, by using a common input to update multiple inputs of R arbitrary basic circuits in an N-register array (R and N are natural number), the array can be separated into R sub- arrays with common data to their inputs. The sub-arrays can realize R number of EOR arrays, as required by convolutional encoder with coding rate 1/R and maximum constraint length N/R. The N-register array can realize single EOR array required by CRC generator and scrambler with maximum register length N. Note that current invention is targeted to convolutional encoder with coding rate 1/R and maximum constraint length M (M is a natural number), and CRC generator with maximum register length of R times of M and scrambler with maximum register length of R times of M.

By using arbitrary basic circuit to pass-through the said common input to an adjacent basic circuit, which is the first basic circuit in a sub-array, a long array is separated into sub-arrays without using dedicated separation circuits. (operation)

In the basic circuits of the signal processing circuit in current invention, by connecting the first input of the first selector of all basic circuits to a common input, and by providing a 2-input 1 -output control circuit between the output of the first selector and the second input of a second selector, where the control circuit outputs either output of the first selector or result of an EOR operation, arbitrary basic circuit can output the common input or result of the EOR operation, to multiple inputs of an adjacent basic circuit. (Effects of the Invention)

The effect of the current invention is reduction of total area for a single circuit that can realize convolution encoder with coding rate 1/R and maximum constraint length M (R and M are natural number), a scrambler with maximum register length of R times of M, and CRC generator with maximum register length of R times of M. In the above Patent Documents 1 and 2 and Non-Patent-Document 1 , it is possible to use a single circuit to realize a convolutional encoder with coding rate 1/R and maximum constraint length M, a scrambler with M-1 maximum register length, and a CRC generator with M-1 maximum register length. However, in practical baseband processing, to reduce complexity of a Viterbi decoder that decodes output of a convolutional encoder, maximum constraint length of convolutional encoder is 50% less than the maximum register length of CRC generator and scrambler. For example, in practical baseband processing, maximum register length of CRC generator is 32 and maximum constraint length of convolutional encoder is 9.

There are two reasons for the reduction of total area. The first reason is not using arrays dedicated for convolution encoder, by separating an array having a large number of register length to realize scrambler and CRC generator, into sub-arrays that realize a convolutional encoder.

The second reason of the area reduction is not using dedicated circuits to separate an array required by scrambler and CRC generator into sub- arrays required by convolutional encoder. Arbitrary basic circuits can be used to separate an array into sub-arrays. Area overhead of the basic circuits used for separation is ignorable because the separation is realized using basic circuit that are required for computations in scrambler and CRC generator, but not required for computation in convolutional encoder. For example, in practical baseband processing where maximum register length of CRC generator is 32 and maximum constraint length of convolutional encoder is 9, CRC generator requires 32 basic circuits for computation and convolutional encoder requires 24 basic circuits for computation, assuming coding rate is 1/3. Therefore, eight remaining basic circuits are not used for computation in convolutional encoder. As a result, separation employs 3 out of 8 remaining basic circuits without area overhead. Note that in the basic circuit, there is no dedicated circuit required for the separation because the said pair of first and second selectors, and control circuit, and connection of common input to first selector are used to realize CRC function.

[Brief Description of the Drawings]

[FIG. 1] A circuit diagram showing an example of the configuration of a convolutional encoder (coding rate 1/2, constraint length 5);

[FIG. 2] A circuit diagram showing an example of the configuration of a convolutional encoder (coding rate 1/3, constraint length 4);

[FIG. 3] A circuit diagram showing an example of the configuration of a scrambler; [FIG. 4] A circuit diagram showing an example of the configuration of a CRC generator;

[FIG. 5] A circuit diagram showing the configuration of a conventional encoder composing a signal processing circuit of combine-type (Patent Document 1);

[FIG. 6] A circuit diagram showing the configuration of a conventional encoder composing a signal processing circuit of combine-type (Patent Document 2);

[FIG. 7] A circuit diagram showing the configuration of a conventional encoder composing a signal processing circuit of combine-type (Non-patent

Document 1);

[FIG. 8] A circuit diagram showing an exemplary configuration of a basic circuit of a signal processing circuit of the first embodiment of the present invention;

[FIG. 9] A circuit diagram showing an exemplary configuration of a signal processing circuit of the first embodiment of the present invention;

[FIG. 10] A diagram for explaining a control method of the operation of a convolutional encoder of a signal processing circuit of the first embodiment of the present invention (coding rate 1/2, constraint length 5); [FIG. 11] A diagram for explaining a control method of the operation of a convolutional encoder of a signal processing circuit of the first embodiment of the present invention (coding rate 1/3, constraint length 4); [FIG. 12] A diagram for explaining a control method of the operation of a scrambler and a CRC generator of a signal processing circuit of the first embodiment of the present invention;

[FIG. 13] A circuit diagram showing an exemplary configuration of a basic circuit of a signal processing circuit of the second embodiment of the present invention; [FIG. 14] A circuit diagram showing an exemplary configuration of a signal processing circuit of the second embodiment of the present invention; [Best Mode for Carrying out the invention] (First embodiment)

FIG. 8 is a circuit diagram showing an exemplary configuration of a basic circuit 10 composing the signal processing circuit of the first embodiment. The basic circuit 10 consists of an AND circuit 12, an exclusive- OR circuit (referred to as "EOR circuit", hereinafter) 13, a flip-flop FF, 2 control memory circuits (15, 16), and two selection circuits (referred to as "selector", hereinafter) 11 , 14. Selectors 11 , 14 are 2-1 selectors selectively output one of two inputs. Note that AND circuit 12, EOR circuit 13 and control memory 16 are components of a 2-input 1 -output control circuit 17.

The selector 11 receives an input signal IN1 as the first input, and an input signal IN2 as the second input. The selector 11 selects the input signal IN1 or the input signal IN2 in an alternative way, and output the selected one as an input signal of EOR circuit 13.

The flip-flop FF receives input from third input signal 1N3. The AND circuit 12 receives input from flip-flop FF as the first input and an output from a control memory 16 as the second input. The AND circuit 12 performs AND operation of these input signals, and outputs a result of the operation.

The EOR circuit 13 receives the output from the selector 11 as the first input and the output from the AND circuit 12 as the second input. The EOR circuit 13 performs EOR operation of these input signals, and outputs a result of the operation.

The selector 14 receives an output from the flip-flop FF as the first input, and the output from the EOR circuit 13 as the second input. The selector 14 selects the output of the flip-flop FF or the output from the EOR circuit 13 in an alternative way, and output the selected input. The selectors 11 and 14 are controlled using control memory 15.

The signal processing circuit in the first embodiment is configured by using two or more said basic circuits 10 shown in FIG. 8, and by connecting them in series. FIG. 9 is a circuit diagram showing an exemplary configuration of a signal processing circuit 20 of the first embodiment. Note that FIG. 9 illustrates the signal processing circuit 20 as one example comprises m (m is an arbitrary natural number) basic circuits 10.

In FIG. 9, reference numeral 10-i (i is a suffix and a natural number from 1 to m) denotes the basic circuit. Each basic circuit 10-i comprises of selectors 11 and 14, the AND circuit 12, and EOR circuit 13, control memory 15, 16 and a flip-flop FFi. Note that the internal configuration of each basic circuit 10-i is same to those in FIG. 8 and will therefore not to be detailed here. An output of the EOR 13 of the basic circuit 10-i is supplied to the basic circuit 10-(i-1) as the input signal IN2. An output of the selector 14 of the basic circuit 10-i is supplied as an update value for the flip-flop FF(i-1) of the basic circuit 10-(i-1).

The external input signal, INPUT of signal processing circuit 20 is connected to input signal IN2 of basic processing circuit 10-m. Output of EOR circuit 13-1 of basic processing circuit 10-1 is outputted as output signal OUTPUT1 of signal processing circuit 20. Output of EOR circuit 13-i of basic circuit 10-i can be connected as an output of signal processing circuit 20, depending on coding rate of convolutional encoder.

Reference numeral 21 denotes an EOR circuit 21 , to which external input signal INPUT of signal processing circuit 20 and output of selector 14 in basic circuit 10-1 are inputs. The EOR circuit 21 performs EOR operations of these input signals, and outputs a result of the operation as output signal OUTPUT2 of the signal processing circuit 20.

Reference numeral 22 denotes a selector circuit, to which input from an external input signal INPUT to the signal processing circuit 20, the output signal OUTPUT2 of EOR circuit 21 are input. Under the control of a control memory, the selector 22 selects one signal out of the external input signal INPUT and the output signal OUTPUT2, and output the selected input. Output of selector 22 is connected to input IN1 of all of the basic circuits 10-1 to 10-m and the update value of the flip-flop FFm of basic circuit 10-m.

Note that the selector 14-n of basic circuit 10-n, which receives an inputs from flip-flop FF and EOR circuit 13, and output its output to update an adjacent flip-flop FF, can be controlled to output an external input signal INPUT, that is connected to selector 11-n through selector 22, depends on control memory 15, and 16, and control memory of selector 22. FIG. 6 shows that in the Patent document 2, the selector that receives input from flip-flop FF and EOR circuit, and output its output to an adjacent flip-flop FF, cannot be controlled to select a common external input.

Note that the selector 11-n of basic circuit 10-n, which output its results to EOR circuit 13-n, receives its input from output of EOR circuit 13-(n-1) and a common input. FIG. 6(A) shows that in the Patent document 2, the selector which outputs its result to an EOR circuit, receives the output of another EOR circuit and output of another selector, and not from a common input.

As described above, the configuration in which two or more basic circuits 10 are connected in series, and proper control of the selectors 11 , 14, 22 and AND circuit 12 make it possible for the signal processing circuit 20 to perform circuit operations of different types of convolutional encoder, scrambler and CRC generator. Note that dedicated circuit array and separation circuits are not required in the current invention. Therefore, total area of the signal processing circuit in the current invention is reduced. The signal processing circuit 20 is configured by connecting the input signals IN1 of the basic circuits 10-i (where, i is a natural number from m to 1) to an output of an external selector, and by connecting the output signal OUTPUT2 of basic circuit 10-j (where j is a natural number from m to 2) to input signal IN2 of basic circuit 10-(j-1), and by connecting output of the EOR circuit 13-j to selector 14-j, by connecting output signal OUTPUT1 of basic circuit 10-j to input IN3 of basic circuit 10-(j-1), it is made possible to separate a signal processing circuit 20 into multiple groups of basic circuits 10 connected in series, which shares a common input connected to an external selector. As a result, it is not necessary to use arrays dedicated for convolutional encoder, as found in conventional architectures. It is also not necessary to use dedicated separation circuits. Therefore, area reduction is achieved in the current invention.

The following paragraphs will specifically describe realization of convolutional encoders, a scrambler, and a CRC generator using the signal processing circuit in the first embodiment of current invention. A convolutional encoder, a scrambler, and a CRC generator using the signal processing circuit 20 will be described referring to FIG. 1 to FIG. 4. The convolutional encoder herein are exemplified as having constraint length 5 and coding rate 1/2 as shown in FIG 1 ; and constraint length 4 and coding rate 1/3 as shown in FIG 2. The CRC generator and scrambler herein are exemplified as having register length 11 , wherein the present invention is by no means limited thereto allowing an arbitrary register length. [Example 1]

First, next paragraphs will describe a convolutional encoder using the signal processing circuit of the first embodiment. Note that the following description deals with an exemplary convolutional encoder shown in FIG. 1.

FIG. 1 is a drawing that shows an exemplary configuration of the convolutional encoder 30. Four flip-flop FF1 to FF4 are connected in series, wherein an output of a flip-flop FFn (where, n is natural number from 4 to 2) is inputted to flip-flop FF(n-1). Input signal INPUT is inputted to flip-flop FF4, EOR circuits 31 and 32. The EOR circuit 31 performs EOR operation of the input signal INPUT and output signals of flip-flops FF2 and FF1 , and outputs a result as the output signal OUTPUT1. The EOR circuit 32 performs EOR operation of the input signal INPUT and output signals of flip-flops FF3 and FF1 , and outputs a result as the output signal OUTPUT2. The following paragraphs will describe a case where the convolutional encoder shown in FIG. 1 is realized by signal processing circuit 20 of the first embodiment, referring to FIG. 10. A configuration of the signal processing circuit 20 shown in FIG. 10 is same as that of the signal processing circuit 20 previously shown in FIG. 9.

The array in signal processing circuit 20 is separated into 2 sub-arrays (sub-array1 and sub-array2), where sub-array1 and sub-array2 generates output signal OUTPUT1 and OUTPUT2 of FIG. 1 , respectively.

The circuit operations of the convolutional encoder shown in FIG. 1 can be realized by controlling the selectors 11-10 and 11-5 of the basic circuit 10- 10 and 10-5 so as to select and output the output from the external selector 22, and by controlling the selectors 11 of the other basic circuits 10 so as to select and output the input signal IN2 of the basic circuits 10. AND circuits 12-8, 12-6, 12-2, 12-1 of the basic circuit 10-8, 10-6, 10-2, 10-1 are controlled so as to output the output of internal flip-flop FF, and other AND circuits 12 of the rest of the basic circuits 10 are controlled so as to output zero. Selectors 14-10, 14-5 of the basic circuits 10-10, 10-5 are controlled so as to select and output the output of EOR circuit 13-10, 13-5 of basic circuits 10-10, 10-5, and the selectors 14 of rest of the basic circuits are controlled so as to select and output the output of the internal flip-flops FF. Selector 22 is controlled to select and output external input signal INPUT. Signals INPUT, OUTPUT1 and OUPUT3 in FIG. 10 are correspondent to INPUT, OUTPUT1 and OUTPUT2 in FIG. 1 , respectively.

Note that, initial values for flip-flops FF9 and FF4 in the signal processing circuit 20 are the same. Similarly, initial values for flip-flops FF8 and FF3, FF7 and FF2, FF6 and FF1 are the same. By controlling the selector 22 of the signal processing circuit 20 and the selectors 11 , 14, and AND circuits 12 of the individual basic circuits 10 as described above, the input signal INPUT in the signal processing circuit 20 is sequentially shifted through the flip-flops FF9 to FF6, and is subjected to EOR operations of the input signal INPUT and the output signals from flip- flops FF8, FF6, and a result is output as the output signal OUTPUT3. Similarly, the input signal INPUT in the signal processing circuit 20 is sequentially shifted through the flip-flops FF4 to FF1 , and is subjected to EOR operations of the input signal INPUT and the output signals from flip- flops FF2, FF1 , and a result is output as the output signal OUTPUT! It is therefore made possible to realize the circuit operation of the convolutional encoder shown in FIG. 1, by properly controlling selectors 11 , 14, AND circuit 12, EOR circuit 13 in the individual basic circuits 10 and by controlling the selector 22.

Note that basic circuits 10-10 is controlled to passthrough output of selector 22 selecting input signal INPUT to flip-flop FF9 for sub-array2. Similarly, that basic circuits 10-5 is controlled to passthrough output of selector 22 selecting input signal INPUT to flip-flop FF4 for sub-array1. The rest of the basic circuits are controlled to perform EOR operations as required by convolutional encoders. Therefore, dedicated separation circuits are not required. [Example 2]

FIG. 2 is a drawing that shows an exemplary configuration of the convolutional encoder 120. Three flip-flops FF1 to FF3 are connected in series, wherein an output of a flip-flop FFn (where, n is natural number from 3 to 2) is inputted to flip-flop FF(n-1). Input signal INPUT is inputted to flip-flop FF3, EOR circuits 121 , 122 and 123. The EOR circuit 121 performs EOR operation of the input signal INPUT and output signals of flip-flops FF2 and FF1 , and outputs a result as the output signal OUTPUT1. The EOR circuit 122 performs EOR operation of the input signal INPUT and output signals of flip-flops FF3 and FF1 , and outputs a result as the output signal OUTPUT2. The EOR circuit 123 performs EOR operation of the input signal INPUT and output signals of flip-flops FF3, FF2 and FF1 , and outputs a result as the output signal OUTPUT3.

The following paragraphs will describe a case where the convolutional encoder shown in FIG. 2 is realized by signal processing circuit 20 of the first embodiment, referring to FIG. 11. A configuration of the signal processing circuit 20 shown in FIG. 11 is same as that of the signal processing circuit 20 previously shown in FIG. 9 and will not be detailed here.

The array in signal processing circuit 20 is separated into 3 sub-arrays (sub-array1 , sub-array2 and sub-array3), where sub-array1 , sub-array2 and sub-array3 generate output signals OUTPUT1 , OUTPUT2 and OUTPUT3 shown in FIG. 2, respectively.

The circuit operations of the convolutional encoder shown in FIG. 2 can be realized by controlling the selectors 11-12, 11-8 and 11-4 of the basic circuit 10-12, 10-8 and 10-4 so as to select and output the output from the external selector 22, and by controlling the selectors 11 of the other basic circuits 10 so as to select and output the input signal IN2 of the basic circuits 10. In addition, AND circuits 12-11 , 12-10, 12-9, 12-7, 12-5, 12-2 and 12-1 of the basic circuit 10-11 , 10-10, 10-9, 10-7, 10-5, 10-2 and 10-1 are controlled so as to output the output of internal flip-flop FF, and AND circuits 12 of the rest of the basic circuits 10 are controlled so as to output zero. Selectors 14- 12, 14-8, 14-4 of the basic circuits 10-12, 10-8, 10-4 are controlled so as to select and output the output of EOR circuit 13-12, 13-8, 13-4 of basic circuits 10-12, 10-8, 10-4 and the selectors 14 of rest of the basic circuits are controlled so as to select and output the output of the internal flip-flops FF. Selector 22 is controlled to select and output external input signal INPUT. Signals INPUT, OUTPUT1, OUPUT3 and OUTPUT4 in FIG. 11 are correspondent to INPUT, OUTPUT1 , OUTPUT2 and OUTPUT3 in FIG. 2, respectively.

Note that, initial values for flip-flops FF11 , FF7 and FF3 in the signal processing circuit 20 are the same. Similarly, initial values for flip-flops FF10, FF6 and FF2 are the same and initial values for flip-flops FF9, FF5 and FF1 are the same.

By controlling the selector 22 of the signal processing circuit 20 and the selectors 11 , 14, and AND circuits 12 of the individual basic circuits 10 as described above, the input signal INPUT in the signal processing circuit 20 is sequentially shifted through the flip-flops FF11 to FF9, and is subjected to EOR operations of the input signal INPUT and the output signals from flip- flops FF11 , FF10 and FF9, and a result is output as the output signal OUTPUT4.

Similarly, the input signal INPUT in the signal processing circuit 20 is sequentially shifted through the flip-flops FF7 to FF5, and is subjected to EOR operations of the input signal INPUT and the output signals from flip- flops FF7, FF5, and a result is output as the output signal OUTPUT3.

Similarly, the input signal INPUT in the signal processing circuit 20 is sequentially shifted through the flip-flops FF3 to FF1 , and is subjected to EOR operations of the input signal INPUT and the output signals from flip- flops FF2, FF1 , and a result is output as the output signal OUTPUT1. It is therefore made possible to realize the circuit operation of the convolutional encoder shown in FIG. 2, by properly controlling selectors 11 , 14, AND circuit 12, EOR circuit 13 in the individual basic circuits 10 and by controlling the selector 22.

Note that basic circuits 10-12 is controlled to passthrough output of selector 22 selecting input signal INPUT to update flip-flop FF11 for sub- array3. Similarly, basic circuits 10-8 is controlled to passthrough output of selector 22 selecting input signal INPUT to update flip-flop FF7 for sub- array2. Similarly, basic circuits 10-4 is controlled to passthrough output of selector 22 selecting input signal INPUT to update flip-flop FF3 for sub- arrayi . Note that the single array in signal processing circuit 20 is separated into 2 and 3 sub-arrays depends on control of controlling selectors 11 , 14, and AND circuit 12 in the individual basic circuit 10 and by controlling the selector 22, without using dedicated separation circuit. Therefore, area reduction is achieved in the current invention. In conventional architectures, dedicated separation circuit is required to separate the single array because there is no path to connect external input signal INPUT to both arbitrary flip-flops and arbitrary EOR circuit input. To separate an array of conventional architecture into sub-arrays, every EOR circuit of EOR arrays and flip-flops of conventional architectures requires a dedicated separation circuit. The dedicated separation circuits will cause area overhead.

In the signal processing circuit 20, dedicated array is not required for convolutional encoder, therefore all of the basic circuits in the signal processing circuit 20 can be used to realize scrambler and CRC generator, as will be shown in next paragraphs. As a result, area of the signal processing circuit 20 is smaller than the signal processing circuit in the conventional architectures that require dedicated arrays for convolutional encoder.

[Example 3]

Next paragraphs will describe a scrambler using the signal processing circuit of the first embodiment, referring to FIG. 3 and FIG. 12. A configuration of the signal processing circuit 20 shown in FIG. 12 is same as that of the signal processing circuit 20 previously shown in FIG. 9. Note that the description below will deal with an exemplary scrambler having a register length of 11. FIG. 3(A) is a drawing showing an exemplary configuration of a scrambler circuit 40. Eleven flip-flops FF1 to FF11 are connected in series, wherein an output of the flip-flop FFn (n is a natural number 11 to 2) is inputted to flip-flop FF(n-1). EOR circuit 41 receives the outputs of flip-flops FF4, FF1 , and performs EOR operation of these signals and output a result of the operation. The output of the EOR circuit 41 is inputted to the flip-flop FF11. An EOR circuit 42 receives an input from the input signal INPUT and an output signal of the EOR circuit 41 , and performs EOR operations of these signals, and outputs a result of the operation as output signal OUTPUT from the scrambler circuit 40. Scrambler circuit shown in FIG. 3(A) is redrawn as an equivalent circuit shown in FIG. 3(B). Scrambler circuit shown in FIG. 3(B) is configured to be same as the one in FIG. 3(A) except the following: An EOR circuit 43 receives input from FF4 and external input signal INPUT, and performs EOR operations on these input signals, and output a result of the operation; An EOR circuit 44 receives an output of the EOR circuit 43 and output of flip-flop FF1 , and performs EOR operations on these input signals, and output a result of the operation as output signal OUTPUT of the scrambler circuit 40. An EOR circuit 45 receives input from the output of EOR circuit 44 and the external input signal INPUT, and performs EOR operations on these input signals, and output a result as an input to update the value of flip-flop FF11. The circuit operations of the scrambler circuit 40 shown in FIG. 3(B) can be realized using signal processing circuit 20 shown in FIG. 12, by controlling the selectors 11-12 of basic circuit 10-12 to select and output the external input signal INPUT, and by controlling other selectors 11 of other the basic circuits 10 to select input IN2 of basic circuit 10. The selector 14-1 of the basic circuit 10-1 is controlled to select and output the output of EOR circuit 13-1 of the basic circuit 10-1. The AND circuit 12-5 and 12-2 of basic circuit 10-5 and 10-2 are controlled to output the output of the flip-flop FF5 and FF2. The rest of the AND circuits are controlled to output zero. Output signal of signal processing circuit 20 is OUTPUT1. EOR circuit 21 receives input from external input signal INPUT and output of selector 14-1 of basic circuits 10-1 and performs EOR operations on these signals, and output a result. The external selector 22 is controlled to select and output the output of the EOR circuit 21.

By controlling the selectors 11, 14, 22 and AND circuits 12 as described above, the input signal entered to the signal processing circuit 20 is subjected to EOR operation together with output from the flip-flops FF5 and FF2 in the EOR circuits 11-5, 11-2 of the basic circuits 10-5, 10-2 respectively, and the EOR result is output from basic circuits 10-1 without any processing as the output signal OUTPUT1 of the signal processing circuit 20. By controlling the selectors 11 , 14 as described above, an output of the FFi is supplied as an update value to the flip-flop FF(H). Note that the OUTPUT1 (which is an EOR result of signals INPUT, outputs of flip-flop FF5, FF2) is EORed with input signal INPUT again using EOR circuit 21 to get the EOR result of flip-flops FF5, FF2. By controlling selector 22 as described above, output of EOR circuit 21 updates flip-flop FF 12. It is therefore made possible to realize the circuit operation of the scrambler circuit 40 shown in FIG. 3(B), by using the signal processing circuit 20 of the first embodiment and by properly controlling the selectors 11 , 14, 22 and AND circuits 12.

In the realization of scrambler using signal processing circuit 20, all of the basic circuits in the signal processing circuit 20 can be used to realize the scrambler, because there is no dedicated array required for convolutional encoders. As a result, area of the signal processing circuit 20 is smaller than the signal processing circuit in the conventional architectures that require dedicated array for convolutional encoder. [Example 4] Next paragraphs will describe a CRC generator using the signal processing circuit of the first embodiment, referring to FIG. 4 and FIG. 12. Note that the description below deals with an exemplary CRC generator having a register length of 11.

FIG. 4 is a drawing showing an exemplary configuration of CRC generator 50. Flip-flops FF11 to FF4 and flip-flops FF3 to FF1 are connected in series. Output of the flip-flop FFn (where n is a natural number from 11 to 5, and 3 to 2) is inputted to the flip-flop FF(n-1). An EOR circuit 51 receives the input signal INPUT and an output signal of the flip-flop FF1 , and performs EOR operations on these signals, and output a result of the operation. The output of the EOR circuit 51 is inputted as an update value of flip-flop FF11 and as an input of EOR circuits 52. The EOR circuit 52 receives an output signal from the flip-flop FF4 and the output of the EOR circuit 51 , performs EOR operations of the these inputs, and outputs a result of the operation to update the flip-flop FF3.

To realize the circuit operation of CRC generator 50 shown in FIG. 4 using the signal processing circuit 20 shown in FIG. 12, the control is made so that selector 22 selects and outputs the output of the EOR circuit 21. Selectors 11 of all basic circuits 10 are controlled to select and output the output of selector 22. The AND circuit 12-4 of the basic circuits 10-4 is controlled to output the output of internal flip-flop FF. AND circuits 12 of the rest of the individual basic circuits 10 are controlled to output zero. Selectors 14-12, 14-4 of the basic circuits 10-12, 10-4 are controlled to select and output the output of EOR circuit 13-12, 13-4 of the basic circuits 10-12, 10-4. Selectors 14 of the rest of the basic circuits 10-i are programmed select and output the output of flip-flop FFi. By controlling the selectors 14-1 in the basic circuit 10-1 as described above, the input signal INPUT to the signal processing circuit 20 is subjected to EOR operation together with the output from the flip-flop FF1 using the EOR circuit 21. By controlling selectors 22 and 11-4, 14-4 and AND circuit 12-4 as described above, an output of the flip-flop FF4 and an output from the EOR circuit 21 is subjected to EOR operation in the EOR circuit 13-4 in the basic circuit 10-4, and the result updates flip-flop FF3. By controlling selectors 14 as described above, outputs of the flip-flop FFi (i is a natural number from 11 to 2) other than the flip-flop FF4 are supplied as update values to the flip-flops FF(i-1). By controlling AND circuit 12-12, and selectors 14-12, 11-12 and 22 as described above, the output of the EOR circuit 21 is supplied as an update value of to the flip-flop FF11. It is therefore made possible to realize the circuit operation of the CRC generator 50 shown in FIG. 4, by using the signal processing circuit 20 of the first embodiment and by properly controlling the selectors 11 , 14, 22 and AND circuits 12.

In the realization of CRC generator using signal processing circuit 20, all of the basic circuits in the signal processing circuit 20 can be used to realize CRC generator. As a result, area of the signal processing circuit 20 is smaller than the signal processing circuit in the conventional architectures that require dedicated array for convolutional encoder.

Note that selector 11-n that selects output of selector 22 for CRC generator is also used to select output of selector 22 for convolutional encoder, and the AND circuit 12-n and EOR circuit 13-n that perform EOR operations for CRC generator are also used to passthrough the output of selector 22 for convolutional encoder, and the selector 14-n that select inputs for FF(n-1) for CRC are used to passthrough the output of selector 22 for convolutional encoder. Therefore, the basic circuit does not require dedicated circuit to separate an array into sub-arrays. As a result, signal processing circuit in the current invention is smaller than the signal processing circuit in the conventional architectures that require dedicated separation circuits. As described above, by proper control of selectors 11 , 14, AND circuit 12 in the individual basic circuits 10, and the selector 22 in signal processing circuit 20, it is made possible to realize the circuit operations of the convolutional encoders 30 and 120, scrambler 40 and CRC generator 50. Moreover, area reduction is achieved by not using dedicated arrays for convolutional encoder and for separation. As described above, the signal processing circuit of the first embodiment is configured using a plurality of basic circuits 10 connected in series, each of the basic circuit 10 composed of the selectors 11 , 14, AND circuit 12, EOR circuit 13, control memory circuit 15, 16 and flip-flop FF. It is also designed so that the input IN1 of the basic circuits are connected to an external selector selecting external input signal Input or output of EOR circuit 21 performing EOR operation on output of basic circuit 10-1 and external input signal INPUT. It is also designed so that the selector 11 properly selects and output either one of inputs IN1 and IN2 of basic circuit 10, and so that the selector 14-i properly selects and output either of an output of the EOR circuit 13-i or output of flip-flop FFi of basic circuit 10-i, the AND circuit 12 properly outputs zero or output of flip-flop FFi. It is made possible to change signals to be supplied to other basic circuits 10 connected thereto, and alter the circuit operations depending on selection by the selectors 11 , 14, 22 and depending on control of AND circuit 12, and to realize convolutional encoder, scrambler and CRC generator on a single signal processing circuit. Note that dedicated arrays for convolutional encoders and dedicated separation circuits are not required. Therefore, area reduction in the first embodiment is achieved. (Second embodiment)

Next paragraphs will explain the second embodiment of the present invention.

FIG. 13 is a circuit diagram showing an exemplary configuration of a basic circuit 130 composing the signal processing circuit of the second embodiment. Note that the configuration of basic circuit 130 of the second embodiment is same to the basic circuit 10 of the first embodiment shown in FIG. 8, except the control circuit 18 of basic circuit 130 that is functionally equivalent to control circuit 17 in FIG. 8. Both control circuit 17 of the first embodiment and control circuit 18 of the second embodiment receive inputs of selector 11 and flip-flop FF, and output to the output signal OUTPUT2. The control circuits 17 and 18 output either output of selector 11 or EOR result of output of selector 11 and flip-flop FF. Therefore, explanation of basic circuit 130 will focus on its circuit 18. Circuit 18 consists of an EOR circuit 181 and a selector 182 and a control memory circuit 19.

The EOR circuit 181 receives the output of the selector 11 as the first input and the output from the flip-flop FF as the second input. The EOR circuit 181 performs EOR operation of these input signals, and outputs a result of the operation.

The selector 182 receives output of selector 11 as the first input, and the output signal of EOR circuit 181 as the second input. The selector 182 selects the output of selector 11 or the output signal of EOR circuit 181 in an alternative way, and output the selected one as an input signal of output signal OUTPUT2 of basic circuit 130, depends on the control of control memory 19.

FIG. 14 is a circuit diagram showing an exemplary configuration of a signal processing circuit 140 of the second embodiment. The signal processing circuit in the second embodiment is configured by using two or more said basic circuits 130 shown in FIG. 13, and by connecting them in series. Note that the configuration of signal processing circuit 140 is same to the signal processing circuit 20 in FIG. 9, except the circuit 18 of basic circuit 130 that is functionally equivalent to circuit 17 in FIG. 8. Therefore, only operations of circuit 18 equivalents to the functions of circuit 17 in FIG. 8, as required to realize circuit operations of convolutional encoder, scrambler and CRC generator, will be detailed here. Note that the EOR circuit 181-n of basic circuit 130-n, has a fan-out of 1 , where its output is connected only to selector circuit 182-n. FIG. 6 shows that in the Patent document 2, the EOR circuit has a fan-out of 2, where its output is connected to two selectors. Operation of controlling AND circuits 12 of basic circuit 10 in FIG. 8 to output the output of internal flip-flop FF is equivalent to operation of controlling selector 182 of signal processing circuit 130 in FIG. 13 to output the output of EOR circuit 181 of signal processing circuit 130.

Operation of controlling AND circuits 12 of basic circuit 10 in FIG. 8 to output the zero is equivalent to operation of controlling selector 182 of signal processing circuit 130 in FIG. 13 to output the output of selector 11 of signal processing circuit 130.

The signal processing circuit 140 can realize a convolutional encoder, a scrambler, and a CRC generator shown in FIG. 1 to FIG. 4, by following the control applied to signal processing circuit 20 as described in the first embodiment, and by proper control of selector 182 to achieve equivalent function on both control circuit 18 of signal processing circuit 140 and control circuit 17 of signal processing circuit 20. Moreover, area reduction show in description of the first embodiment is also achieved in the second embodiment, because not using dedicated arrays for convolutional encoder and for separation of an array into sub-arrays.

It is to be understood that the aforementioned embodiment is merely expression of materialization of the present invention, with which the technical scope of the present invention should not be limited by interpretation. In other words, the present invention can be embodied in various modified forms without departing from the technical spirit and essential features thereof.

Claims

CLAIMS [Claim 1]

A signal processing circuit comprising a plurality of basic circuits connected in series, each of said basic circuits comprising: a first selection circuit outputting a first input signal or a second input signal; a holding circuit that holds data and subjecting to a third input signal; a control circuit subjecting the output of the said holding circuit and the output of the said first selection circuit; a second selection circuit outputting an output of the said holding circuit or an output signal of said control circuit; the said first and second selection circuit are controlled by a forth input signal.

[Claim 2] The signal processing circuit according to claim 1 , the said control circuit comprising either an AND circuit subjecting the output of the said holding circuit and a fifth input signal; a first exclusive-OR circuit subjecting output of the said AND circuit and the output of the said first selection circuit; or a second exclusive-OR circuit subjecting the output of the said first selection circuit and output of the said holding circuit; a third selection circuit subjecting the output of the said first selection circuit and the output of said second exclusive-OR circuit.

[Claim 3]

The signal processing circuit according to claim 2, wherein an output signal of said control circuit is supplied as said second input signal to said basic circuit connected to the succeeding stage, and an output signal of said second selection circuit is supplied as said third input signal to said basic circuit connected to the succeeding stage, and said first input of said first selection circuit of said basic circuits are connected to output of an external selector selecting an external input and output of a third exclusive-OR circuit.

[Claim 4]

The signal processing circuit according to claim 3, configured as arbitrary number of sub-arrays consists of separated basic circuits connected in series, to which an external input signal is passthrough to the first and third input of arbitrary basic circuits, and identical values are set as the initial value of said correspondent holding circuit and so as to enable operation of a convolutional encoder with coding rate 1/R and N/R maximum constraint length using N-bit register length, depending on selection made on said first, second, and external selection circuits, and depending on control made on said control circuit.

[Claim 5]

The signal processing circuit according to claim 4, configured as being capable of performing two or more types of operations of a convolutional encoder depending on selection made on said first, second, and external selection circuits, and depending on control made on said control circuit.

[Claim 6]

The signal processing circuit according to claim 3, configured as being capable of performing two or more types of operations of a scrambler depending on selection made on said first, second, and external selection circuits, and depending on control made on said control circuit. [Claim 7]

The signal processing circuit according to claim 6, configured as being capable of performing operations of the scrambler corresponding to any arbitrary register length having the number not larger than the number of said basic circuits connected in series, depending on selection made on said first, second, and external selection circuits, and depending on control made on said control circuit. [Claim 8] The signal processing circuit according to claim 3, configured as being capable of performing two or more types of operations of a CRC generator depending on selection made on said first, second, and external selection circuits, and depending on control made on said control circuit. [Claim 9] The signal processing circuit according to claim 8, configured as being capable of performing operations of the CRC generator corresponding to any arbitrary register length having the number not larger than the number of said basic circuits connected in series, depending on selection made on said first, second, and external selection circuits, and depending on control made on said control circuit.