WO2009044917A1 - 半導体基板および半導体装置 - Google Patents

半導体基板および半導体装置 Download PDF

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Publication number
WO2009044917A1
WO2009044917A1 PCT/JP2008/068183 JP2008068183W WO2009044917A1 WO 2009044917 A1 WO2009044917 A1 WO 2009044917A1 JP 2008068183 W JP2008068183 W JP 2008068183W WO 2009044917 A1 WO2009044917 A1 WO 2009044917A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
semiconductor
semiconductor device
substrate
terraces
Prior art date
Application number
PCT/JP2008/068183
Other languages
English (en)
French (fr)
Inventor
Tadahiro Ohmi
Akinobu Teramoto
Tomoyuki Suwa
Rihito Kuroda
Hideo Kudo
Yoshinori Hayami
Original Assignee
National University Corporation Tohoku University
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National University Corporation Tohoku University, Shin-Etsu Handotai Co., Ltd. filed Critical National University Corporation Tohoku University
Priority to KR1020107007609A priority Critical patent/KR101536020B1/ko
Priority to CN2008801102861A priority patent/CN101816060B/zh
Priority to US12/681,576 priority patent/US8492879B2/en
Priority to EP08835197.8A priority patent/EP2197023A4/en
Publication of WO2009044917A1 publication Critical patent/WO2009044917A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

　半導体基板表面に原子ステップで段状とされた複数のテラスを実質的に同一方向に形成する。さらにこの半導体基板を使用し、キャリア走行方向（ソース－ドレイン方向）にステップが存在しないようにＭＯＳトランジスタを形成する。
PCT/JP2008/068183 2007-10-04 2008-10-06 半導体基板および半導体装置 WO2009044917A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020107007609A KR101536020B1 (ko) 2007-10-04 2008-10-06 반도체 기판 및 반도체 장치
CN2008801102861A CN101816060B (zh) 2007-10-04 2008-10-06 半导体基板及半导体装置
US12/681,576 US8492879B2 (en) 2007-10-04 2008-10-06 Semiconductor substrate and semiconductor device
EP08835197.8A EP2197023A4 (en) 2007-10-04 2008-10-06 SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR ASSEMBLY

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007261096A JP2009094156A (ja) 2007-10-04 2007-10-04 半導体基板および半導体装置
JP2007-261096 2007-10-04

Publications (1)

Publication Number Publication Date
WO2009044917A1 true WO2009044917A1 (ja) 2009-04-09

Family

ID=40526329

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/068183 WO2009044917A1 (ja) 2007-10-04 2008-10-06 半導体基板および半導体装置

Country Status (6)

Country Link
US (1) US8492879B2 (ja)
EP (1) EP2197023A4 (ja)
JP (1) JP2009094156A (ja)
KR (1) KR101536020B1 (ja)
CN (1) CN101816060B (ja)
WO (1) WO2009044917A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8445386B2 (en) 2010-05-27 2013-05-21 Cree, Inc. Smoothing method for semiconductor material and wafers produced by same
JP5906463B2 (ja) * 2011-06-13 2016-04-20 パナソニックＩｐマネジメント株式会社 半導体装置の製造方法
JP2016006870A (ja) * 2014-05-30 2016-01-14 住友電気工業株式会社 半導体装置
KR20200015086A (ko) 2018-08-02 2020-02-12 삼성전자주식회사 기판과 이를 포함하는 집적회로 소자 및 그 제조 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004265918A (ja) 2003-02-07 2004-09-24 Shin Etsu Handotai Co Ltd シリコン半導体基板及びその製造方法
JP2004356114A (ja) 2003-05-26 2004-12-16 Tadahiro Omi Ｐチャネルパワーｍｉｓ電界効果トランジスタおよびスイッチング回路
JP2007261096A (ja) 2006-03-28 2007-10-11 Ricoh Co Ltd インクジェットプリンタ、印刷方法、印刷プログラム、及び記録媒体

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2172233C (en) 1995-03-20 2001-01-02 Lei Zhong Slant-surface silicon wafer having a reconstructed atomic-level stepped surface structure
EP0746041B1 (en) * 1995-05-31 2001-11-21 Matsushita Electric Industrial Co., Ltd. Channel region of MOSFET and method for producing the same
US6559518B1 (en) * 1998-10-01 2003-05-06 Matsushita Electric Industrial Co., Ltd. MOS heterostructure, semiconductor device with the structure, and method for fabricating the semiconductor device
JP4651207B2 (ja) * 2001-02-26 2011-03-16 京セラ株式会社 半導体用基板とその製造方法
DE10237247B4 (de) * 2002-08-14 2004-09-09 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe aus Silicium

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004265918A (ja) 2003-02-07 2004-09-24 Shin Etsu Handotai Co Ltd シリコン半導体基板及びその製造方法
JP2004356114A (ja) 2003-05-26 2004-12-16 Tadahiro Omi Ｐチャネルパワーｍｉｓ電界効果トランジスタおよびスイッチング回路
JP2007261096A (ja) 2006-03-28 2007-10-11 Ricoh Co Ltd インクジェットプリンタ、印刷方法、印刷プログラム、及び記録媒体

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
A .TERAMOTO ET AL.: "Very High Carrier Mobility for High-Performance CMOS on a Si(110) Surface", IEEE ELECTRON DEVICES, vol. 54, no. 6, June 2007 (2007-06-01), pages 1438 - 1445, XP011184975, DOI: doi:10.1109/TED.2007.896372
S.TAKAGI ET AL.: "On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration", IEEE ELECTRON DEVICES, vol. 41, no. 12, December 1994 (1994-12-01), pages 2357 - 2362
See also references of EP2197023A4
T. OHMI ET AL.: "Revolutional Progress of Silicon Technologies Exhibiting Very High Speed Performance Over a 50-GHz Clock rate", IEEE ELECTRON DEVICES, vol. 54, no. 6, June 2007 (2007-06-01), pages 1471 - 1477, XP011184969, DOI: doi:10.1109/TED.2007.896391
T. OHMI: "Total room temperature wet cleaning Si substrate surface", J. ELECTROCHEM. SOC., vol. 143, no. 9, September 1996 (1996-09-01), pages 2957 - 2964
Y MORITA ET AL.: "Atomic scale flattening and hydrogen termination of the Si(001) surface by wet-chemical treatment", J. VAC. SCI. TECHNOL. A, VAC. SURF. FILM, vol. 14, no. 3, May 1996 (1996-05-01), pages 854 - 858, XP000620556, DOI: doi:10.1116/1.580403

Also Published As

Publication number Publication date
US20100213516A1 (en) 2010-08-26
EP2197023A1 (en) 2010-06-16
CN101816060A (zh) 2010-08-25
CN101816060B (zh) 2012-01-11
KR20100067107A (ko) 2010-06-18
US8492879B2 (en) 2013-07-23
JP2009094156A (ja) 2009-04-30
KR101536020B1 (ko) 2015-07-10
EP2197023A4 (en) 2013-05-22

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