WO2009043062A2

WO2009043062A2 - Wafer level packaged mems device

Info

Publication number: WO2009043062A2
Application number: PCT/US2008/080691
Authority: WO
Inventors: Peter H. Lafond; Lianzhong Yu
Original assignee: Honeywell International Inc.
Priority date: 2007-09-28
Filing date: 2008-10-22
Publication date: 2009-04-02
Also published as: EP2193542A4; US8685776B2; EP2193542B1; WO2009043062A3; EP2193542A2; US20090085194A1; US20110092018A1; JP2012506616A

Abstract

An apparatus and method for sensor architecture based on bulk machining of silicon wafers and fusion bond joining which provides a nearly all-silicon, hermetically sealed, microelectromechanical system (MEMS) device. An example device includes a device sensor mechanism (34) formed in an active semiconductor layer and separated from a handle layer (32) by a dielectric layer (36), and a silicon cover plate (40) having a handle layer (42) with a dielectric layer (44) being bonded to portions of the active layer. Pit are included in one of the handle layers (32, 42) and corresponding dielectric layers (36, 44) to access electrical leads on the active layer (44). Another example includes set backs from the active components formed by anisotropically etching the handle layer while the active layer has been protectively doped.

Description

WAFER LEVEL PACKAGED MEMS DEVICE

BACKGROUND OF THE INVENTION

[0001] Microelectromechanical systems or "MEMS" devices are generally well-known. In the most general form, MEMS devices consist of mechanical microstructures, microsensors, microactuators and electronics integrated in the same environment, i.e., on a silicon chip. MEMS technology is an enabling technology in the field of solid-state transducers, i.e., sensors and actuators. The microfabrication technology enables fabrication of large arrays of devices, which individually perform simple tasks but in combination can accomplish complicated functions. Current applications include accelerometers, pressure, chemical and flow sensors, micro-optics, optical scanners, and fluid pumps. For example, one micromachining technique involves masking a body of silicon in a desired pattern, and then deep etching the silicon to remove unmasked portions thereof. The resulting three-dimensional silicon structure functions as a miniature mechanical force sensing device, such as an accelerometer that includes a proof mass suspended by a flexure.

[0002] What is needed are methods and devices that are simpler and more cost-effective, while still adhering as closely as possible to "best practice" design principles.

SUMMARY OF THE INVENTION

[0003] The present invention provides an apparatus and method for sensor architecture based on bulk machining of Silicon-On-Oxide (SOI) and Double-Sided Polished (DSP) wafers and fusion bond joining that simplifies manufacturing and reduces costs by providing a nearly all-silicon, hermetically sealed, microelectromechanical system (MEMS) device, such as an electrostatic accelerometer or rate gyro device.

[0004] In one aspect of the present invention, the device includes a device sensor mechanism formed in an active semiconductor layer separated from a handle layer by a dielectric layer, and a first silicon cover plate having a relatively thicker handle portion with a thin dielectric layer. The dielectric layer of the cover plate is bonded to an active layer face of the device sensor mechanism. Cavities are formed in one or both of the handle layers and corresponding dielectric layer to expose electrical leads.

[0005] In another aspect of the present invention, the cover is an SOI wafer and set backs from the active components are anisotropically etched into the handle layer while the active layer has been protectively doped. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Preferred and alternative embodiments of the present invention are described in detail below with reference to the following drawings: [0007] FIGURE 1 is a cross-sectional view of a sensor mechanism device formed in accordance with an embodiment of the present invention;

[0008] FIGURES 2A-E illustrate a fabrication process for creating a sensor mechanism device;

[0009] FIGURE 3 is a cross-sectional view of another sensor mechanism device formed in accordance with an embodiment of the present invention;

[0010] FIGURES 4A-G illustrate a fabrication process for creating the device of FIGURE 3; and

[0011] FIGURE 5 is a perspective view of an isolator flange of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0012] FIGURES 1, 2A-E illustrate a sensor mechanism device 20 and process for making same. A first silicon- on-insulator (SOI) wafer 30 has a mechanism layer 34 on a dielectric (e.g., Siθ2) layer 36 which is on a handle layer (Si) 32. The dielectric layer 36 has a thickness from about 0.5 to 3.0 microns that is sandwiched between the handle layer 32 and the mechanism layer 34. The dielectric layer 36 is oxide or some other insulator.

[0013] First, as shown in FIGURE 2A, the mechanism layer 34 is etched using a known etchant (e.g., RIE (Reactive Ion Etch) or DRIE (Deep Reactive Ion Etch)) according to a predefined etching pattern(s). The dielectric layer 36 acts as an etch stop. Etching exposes appropriate actuator and/or sensor mechanical features (e.g. 38) in the mechanism layer 34. Next as shown in FIGURE 2B, hydrogen fluoride (HF) etching and/or carbon dioxide (CO2) is used to etch away the dielectric below and around the features 38. Other etchants may be used provided the handle layer 32 acts as an etch stop. [0014] FIGURE 2C is a cross-sectional view that illustrates fabrication of a silicon cover 40 from a double sided polished (DSP) wafer. The cover 40 includes a dielectric layer 44 on one side of a handle layer 42. The dielectric layer 44 is etched to expose a pattern of cooperating interior cover plate features that correspond to the location of the etched features 38. The dielectric layer 44 is etched using known etching techniques (see above) with the handle layer 42 being an etch stop.

Next, at a FIGURE 2D, the silicon cover 40 is fusion or Au-eutectic bonded to the SOI wafer 30. The remaining portions of the dielectric layer 44 are bonded to non- feature components of the mechanical layer 34. Next, as shown in FIGURE 2E, one or both of the handle layers 32 and 42 are etched away at locations relative to some of the non- feature portions of the mechanism layer 34 using a conventional wet etching process, such as potassium hydroxide (KOH). Next, one or both of the exposed dielectric material from the dielectric layers 36 and 44 are then etched away, using a standard etching process, to expose a portion of the non- featured portion of the mechanism layer 34. Next, metallized connectors 50 are applied to portions of the exposed non-featured sections of the mechanism layer 34. The metallized connectors 50 provide electrical connections to exposed electrical traces on the mechanism layer 34 that are in electrical communication with the active internal components (features 38). Lastly, dicing (not shown) occurs in order to separate sealed functional components and associated externally exposed metallized connectors 50.

[0015] FIGURES 3 and 4A-G illustrate an alternate sensor mechanism device 100 and process for making same. The sensor mechanism device 100 is similar to the sensor mechanism device 20 as shown in FIGURES 1 and 2A-E except that a cover 120 (FIGURE 4D) is an SOI wafer. Also, FIGURE 4C illustrates additional steps for producing a set-back from active components 112. First, at FIGURES 4A and 4B, a base SOI wafer 102 is processed in a similar manner as the steps as shown in FIGURES 2A and 2B to produce active components 112. The surfaces of the components 112 and other portions of the mechanism layer 106 are or have been previously doped. Next, at FIGURE 4C, an anisotropic etch (e.g., Ethylene-Diamene-Pyrocatechol (EDP), KOH, Tetra- Methyl Ammonium Hydroxide (TMAH)) is performed of the handle layer 110 to produce set backs 128 from the active components 112.

[0016] Next, at FIGURE 4D, the cover 120 is etched to expose a handle layer 122 at positions that would correspond to the active components 112 from the base wafer 102. Then, an optional mechanical isolation peripheral device 130 is etched using DRIE or comparable etching technique. Next, at FIGURE 4E, the cover 120 is attached to the base wafer 102 using a fusion bond, Au-eutectic bond, or comparable type of bonding process. Next, at FIGURE 4F, a KOH etch or comparable etching technique is used to etch away a handle layer 110 of the base wafer 102 and the handle layer 122 is etched by DRIE process in order to complete the mechanical isolation around the periphery and to expose portions of a dielectric layer 124. The mechanical isolation around the periphery reduces the amount of mechanical loads that can impinge upon the components 112 when they are in a package. Then, the exposed dielectric material in the dielectric layer 124 is etched to expose the surface of the mechanism layer 106. Metalized contacts 140 are then applied to the exposed surface of the mechanism layer 106 in order to allow for connection of the active components 112 within corresponding hermetically sealed cavities to external devices (not shown). Dicing (not shown) of the entire package is then performed. [0017] While the preferred embodiment of the invention has been illustrated and described, as noted above, many changes can be made without departing from the spirit and scope of the invention. For example, steps described and claimed may be performed in a different order without departing from the spirit and scope of the invention - e.g., doping of the active layer may be performed before etching the same layer. Accordingly, the scope of the invention is not limited by the disclosure of the preferred embodiment. Instead, the invention should be determined entirely by reference to the claims that follow.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A wafer level packaged sensor device comprising: a base section formed of a silicon-on-insulator (SOI) wafer comprising: an active layer (34) having one or more etched active components; a handle layer (32); and a dielectric layer (36) located between the active layer and the handle layer (32); and a cover plate having a handle layer and dielectric layer (44), wherein the dielectric layer of the cover plate is etched to correspond with the one or more active components, the cover plate being bonded to the base, at least one of the base wafer handle layer (32) or cover plate handle layer (42) and corresponding dielectric layer (36, 44) having one or more etched pit features for exposing a portion of the surface of the active layer.

2. The device of Claim 1, further comprising metallization located on the exposed surface of the active layer, the metallization being in electric communication with one or more of the active components.

3. The device of Claim 2, further comprising at least one isolator flange formed by selectively etching the base section and the cover plate at an exterior edge of the device.

4. The device of Claim 1, wherein the active layer (34) of the base section having a level of dopant for resisting an anisotropic etching process and one or more set backs formed into the handle layer (32) of the base section near the active components, the one or more set backs being formed by an anisotropic etch.

5. A method for forming a wafer level package device, the method comprising: etching at least one active component in an active layer (34) of a base silicon-on-insulator (SOI) wafer (30), the SOI wafer (30) having a handle layer (32) separated from the active layer (34) by a dielectric layer (36); etching the dielectric layer (36) in the vicinity of the formed active component; etching a dielectric layer (44) of a cover plate wafer (40) to form cavities to coincide with the at least one active components, the cover plate (40) having a handle layer (42) attached to the cover plate wafer dielectric layer (44), etching at least one of the handle layers (32, 42) and corresponding dielectric layer (36, 44) to expose the surface of the active layer

(34); and forming a metallization (50) on a portion of the exposed surface of the active layer (34).

6. The method of Claim 5, further comprising etching at least one isolator flange into the base wafer and the cover plate wafer at an exterior edge.

7. A method for forming a wafer level package device, the method comprising: forming at least one active component in an active layer (34) of a base silicon-on-insulator (SOI) wafer (30); applying a dopant to the active layer (34); anisotropically etching a handle layer (32) of the SOI wafer (30) in the vicinity of the at least one active component; etching an active layer and a dielectric layer (44) of a cover plate SOI wafer (40) to form one or more cavities to coincide with the active components of the base wafer; bonding the SOI wafer (30) to the cover plate SOI wafer (40); etching at least one of the handle layers (32, 42) and corresponding dielectric layer (36, 44) to expose the surface of the corresponding active layer (34) from the base SOI wafer (30) or from the cover plate SOI wafer (40); and forming a metallization (50) on at least a portion of the exposed active layer (34).

8. The method of Claim 7, further comprising etching the SOI wafers in order to form one or more isolation flanges.