WO2009043023A2 - Commutation électronique, mémoire et dispositifs de détecteurs à partir de feuilles de carbone sur des matériaux diélectriques - Google Patents

Commutation électronique, mémoire et dispositifs de détecteurs à partir de feuilles de carbone sur des matériaux diélectriques Download PDF

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WO2009043023A2
WO2009043023A2 PCT/US2008/078152 US2008078152W WO2009043023A2 WO 2009043023 A2 WO2009043023 A2 WO 2009043023A2 US 2008078152 W US2008078152 W US 2008078152W WO 2009043023 A2 WO2009043023 A2 WO 2009043023A2
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Prior art keywords
electronic device
carbon sheet
nanocable
current
voltage
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PCT/US2008/078152
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WO2009043023A3 (fr
WO2009043023A4 (fr
Inventor
James M. Tour
Yubao Li
Alexander Sinitskiy
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William Marsh Rice University
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Publication of WO2009043023A3 publication Critical patent/WO2009043023A3/fr
Publication of WO2009043023A4 publication Critical patent/WO2009043023A4/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/253—Multistable switching devices, e.g. memristors having three or more electrodes, e.g. transistor-like devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors
    • H10N70/8845—Carbon or carbides

Definitions

  • Transistors are a bulwark of electronic switching and memory applications due to their extreme reliability and high ON/OFF ratios of 10 4 -10 5 .
  • Transistors are three-terminal devices that include source, drain, and gate electrode terminals.
  • Two-terminal electronic devices can be operable in switching and memory applications, provided the devices display a non-linear current-versus-voltage response and have a great enough and reliable ON/OFF ratio.
  • Molecular-based devices and one-dimensional carbon nanostructures having non-linear current-versus-voltage response and current peak-to-valley ratios (PVRs) generally on the order of 2 to 100 have been reported.
  • two-terminal memory devices have been described that are based upon metal filamentary mechanisms. These include molecular-spaced devices, nanowire crossbar memories, and resistive random access memories using transition metal oxides.
  • Coaxial multi-layer nanocables which may include various materials, including carbon nanotubes, are of potential interest in molecular-based devices, since nanocables retain the one- dimensional features of both nanowires and nanotubes in the axial direction and form a heterojunction in the radial direction.
  • the electronic devices include a dielectric material, at least one carbon sheet, and two electrode terminals.
  • the at least one carbon sheet is deposited on the dielectric material.
  • a first of the two electrode terminals forms a source and a second of the two electrode terminals forms a drain.
  • the electronic devices exhibit nonlinear current-versus-voltage response when operated over a voltage sweep range.
  • the electronic devices may, for example, be used as two-terminal memory devices, logic switches, and sensors.
  • electronic devices are prepared by a process including: 1) providing a dielectric material; 2) depositing at least one carbon sheet on the dielectric material; and 3) positioning two electrode terminals on the dielectric material.
  • the at least one carbon sheet lies between the two electrode terminals.
  • a first of the two electrode terminals forms a source and a second of the two electrode terminals forms a drain.
  • the electronic device prepared by the process further includes applying a voltage sweep between the two electrode terminals, such that the voltage sweep produces a nonlinear current-versus-voltage response.
  • analytical methods comprise: 1) providing an electronic device; 2) operating the electronic device over a voltage sweep range; and 3) observing current-versus-voltage performance of the electronic device.
  • the operating and observing steps occur in the presence of at least one analyte.
  • Figure 1 shows an embodiment of C-SiO 2 -SiC, C-SiO 2 -Si, and C-SiO 2 nanocables.
  • Figure 2 shows a high-resolution TEM image of a C-SiO 2 -SiC nanocable embodiment.
  • Figure 3 shows a selected-area electron diffraction pattern of a C-SiO 2 -SiC nanocable embodiment.
  • Figure 4 shows an embodiment of a two-terminal electronic device and exemplary process steps for preparing the device.
  • Figure 5 shows a representative embodiment of an SEM image of a long channel C-SiO 2 -SiC nanocable electronic device.
  • Figure 6 shows a representative embodiment of an SEM image of a short channel C-SiO 2 -SiC nanocable electronic device.
  • Figure 7 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various long channel C-SiO 2 -SiC nanocable electronic devices.
  • Figure 8 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15 V for various short channel C-SiO 2 -SiC nanocable electronic devices.
  • Figure 9 shows an embodiment of a reverse bias sweep of +15 V to -15 V for a C-SiO 2 -SiC nanocable device having a channel length of 2.7 ⁇ m.
  • Figure 10 shows an embodiment of variable temperature conductance of C-SiO 2 -SiC nanocable devices over a temperature range of 100 K to 295 K and a bias voltage sweep of -1 V to +1 V.
  • Figure 11 shows an embodiment of a repetitive bias voltage sweep of a C-SiO 2 -SiC nanocable electronic device.
  • Figure 12 shows an embodiment of the memory performance of a long channel C-SiO 2 -SiC nanocable electronic device having a channel length of 2.8 ⁇ m, as obtained from a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s.
  • Figure 13 shows an embodiment of the memory performance of a long channel C-SiO 2 -SiC nanocable electronic device having a channel length of 4.5 ⁇ m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s.
  • Figure 14 shows an embodiment of the long term memory reading performance of a long channel C-SiO 2 -SiC nanocable electronic device having a channel length of 4.5 ⁇ m, as obtained from a +5 V write bias pulse for 1 s and +15 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at +1 V.
  • Figure 15 shows an embodiment of the memory reading performance of a short channel C-SiO 2 -SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 10 consecutive current reads at +1 V.
  • Figure 16 shows an embodiment of the long term memory reading performance of a short channel C-SiO 2 -SiC nanocable electronic device having a channel length of 280 nm, as obtained from a +2.5 V write bias pulse for 1 s and +5 V erase bias pulse for 1 s, followed by 1000 consecutive current reads at +1 V.
  • Figure 17 shows an embodiment of the memory reading performance of a short channel C-SiO 2 -SiC nanocable electronic device having a channel length of 430 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
  • Figure 18 shows an embodiment of the memory reading performance of a short channel C-SiO 2 -SiC nanocable electronic device having a channel length of 360 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse.
  • Figure 19 shows embodiments of the memory reading performance of a short channel C-SiO 2 -SiC nanocable electronic device having a channel length of 700 nm, as obtained from a +3 V write bias pulse and a +6 V erase bias pulse, with a write/erase bias pulse times of either 0.1 or 1 second.
  • Figure 20 shows embodiments of BIV behavior over a bias sweep range of -15 V to +15
  • Figure 21 shows an embodiment of the memory reading performance of a C-SiO 2 -Si nanocable electronic device, as obtained from a +4 V write bias pulse for 1 second and a +8 V erase bias pulse for 1 second.
  • Figure 22 shows an embodiment of BIV behavior over a bias sweep range of -8 V to +8
  • Figure 23 shows an embodiment of BIV behavior over a bias sweep range of -10 V to +10 V for a C-SiO 2 nanocable electronic device having a channel length of 2.5 ⁇ m, as conducted in the presence of -20, 0, and +20 V gate biases.
  • Figure 24 shows an embodiment of a five-cycle bias sweep sequence from 0 to +8 V for a C-SiO 2 nanocable electronic device having a channel length of 2.4 ⁇ m.
  • Figure 25 shows an embodiment of a three-cycle bias sweep sequence from 0 to +10 V for a C-SiO 2 nanocable electronic device having a channel length of 2.5 ⁇ m and a nanocable diameter of 110 nm.
  • Figure 26 shows an embodiment of the memory reading performance of a C-SiO 2 nanocable electronic device having a channel length of 2.5 ⁇ m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being followed by reading 10 consecutive times at +1 V.
  • Figure 27 shows an embodiment of a two-cycle bias sweep sequence from 0 to +8 V for a C-SiO 2 nanocable electronic device having a channel length of 1.9 ⁇ m and a nanocable diameter of l lO nm.
  • Figure 28 shows an embodiment of the memory reading performance of a C-SiO 2 nanocable electronic device having a channel length of 1.9 ⁇ m and a nanocable diameter of 110 nm, as conducted with a +4 V write bias pulse for 1 ms and a +6 V erase bias pulse for 1 ms, each write/erase operation being followed by reading 1000 consecutive times at +1 V.
  • Figure 29 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-SiO 2 nanocable electronic device having a channel length of 2.6 ⁇ m and a nanocable diameter of 140 nm.
  • Figure 30 shows an embodiment of the memory reading performance of a C-SiO 2 nanocable electronic device having a channel length of 2.6 ⁇ m and a nanocable diameter of 140 nm, as conducted with a +4 V write bias pulse for 1 ms and a +8 V erase bias pulse for 1 ms, each write/erase operation being followed by reading 5 consecutive times at +1 V.
  • Figure 31 shows an embodiment of a one-cycle read/write bias sweep sequence from 0 to +8 V for a C-SiO 2 nanocable electronic device having a channel length of 1.5 ⁇ m and a nanocable diameter of 200 nm.
  • Figure 32 shows an embodiment of the memory reading performance of a C-SiO 2 nanocable electronic device having a channel length of 1.5 ⁇ m and a nanocable diameter of 200 nm, as conducted with a +6 V write bias pulse for 1 ⁇ s and a +8 V erase bias pulse for 100 ⁇ s, each write/erase operation being followed by reading 10 consecutive times at +1 V.
  • Figure 33 shows an embodiment of the memory reading performance of two C-SiO 2 nanocable electronic devices, set to either the ON or OFF state prior to testing, over two weeks of testing time and exposure to different conditions.
  • Figure 34 shows an embodiment of the BIV behavior for a first C-SiO 2 nanocable device whose memory performance is shown in Figure 33, prior to exposure to different testing conditions.
  • Figure 35 shows an embodiment of the BIV behavior for a second C-SiO 2 nanocable device whose memory performance is shown in Figure 33, prior to exposure to different testing conditions.
  • Figure 36 shows embodiments of SEM images of C-SiO 2 nanocable electronic devices before and after the extended electrical property measurements presented in Figure 33. The high magnification inset is denoted by an arrow.
  • Figure 37 shows embodiments of SEM images of multi-wall carbon nanotube (MWCNT) electronic devices, both before and after electrical breakdown.
  • MWCNT multi-wall carbon nanotube
  • Figure 38 shows embodiments of SEM images of C-SiO 2 nanocable electronic devices, where graphite comprises the nanocable, both before and after electrical breakdown.
  • Figure 39 shows an embodiment of a proposed NEM switching mechanism responsible for BIV behavior in grapheme or graphitic nanocable electronic devices.
  • Figure 40 shows embodiments of BIV behavior for a C-SiO 2 nanocable electronic device over a temperature range between 200 K and 400 K.
  • Figure 41 shows embodiments of SEM images of a two-terminal electronic device fabricated according to Figure 4, both before and after electrical breakdown.
  • Figure 42 shows an embodiment of BIV behavior over a bias sweep range of 0 V to +15 V for the two-terminal electronic device presented in Figure 41 having a channel length of 2 ⁇ m, width of 2 ⁇ m and carbon sheet thickness of 20 nm.
  • Figure 43 shows an embodiment of the memory reading performance for the two- terminal electronic device presented in Figure 42 over 10000 write/erase cycles, as conducted with a +8 V write bias pulse for 1 ⁇ s and a +15 V erase bias pulse for 1 ⁇ s.
  • Table 1 shows a summary of embodiments of the dependence of V th and PVR on C-SiO 2 -SiC nanocable channel length.
  • Bias is a predetermined voltage applied to an electronic device that causes the device to operate in a certain desired fashion or to set a certain operating point, hi the various embodiments presented herein, a voltage bias may be established at the source electrode terminal or through a third electrode not comprising the source or drain electrode terminals.
  • Channel length refers to the length of at least one carbon sheet bridging between source and drain electrodes of the electronic devices described herein. In other words, channel length is the inter-electrode separation distance.
  • discontinuous carbon layer refers to a discontinuous graphene layer or discontinuous graphite layer between source and drain electrodes, where at least two independent sheets of graphene or graphite span the distance between the source and drain electrodes, because no one sheet of graphene or graphite is long enough to completely span the distance between the source and drain electrodes, hi forming the discontinuous graphene layer or discontinuous graphite layer, the at least two independent sheets of graphene or graphite have at least one overlapping region between the sheets.
  • NDR Negative differential resistance
  • PVR Peak-to-valley ratio
  • Threshold voltage (V th ), is the voltage at which a maximum or minimum current peak occurs in a device exhibiting BIV behavior.
  • the electronic devices include at least one nanocable.
  • Nanocables may be formed from coaxial sheets of carbon and a dielectric material in an embodiment.
  • a nanowire core optionally further comprises the nanocables.
  • Exemplary but non-limiting nanocables utilized in the various embodiments presented herein include C-SiO 2 -SiC, C-SiO 2 -Si, and C-SiO 2 nanocables.
  • the nanocables may be represented in a generic form X-Y-Z. In this generic representation, a layer of dielectric material Y is covered by at least one carbon sheet of layer X.
  • nanocable C-SiO 2 -SiC includes a SiC nanowire core, covered by a SiO 2 dielectric coating, which is in turn covered by at least one carbon sheet.
  • C may, for example, refer to graphite, graphene, or graphene sheets.
  • Figure 1 shows pictorial representations of the three types of nanocables.
  • 101 is a C-SiO 2 -SiC nanocable
  • 102 is a C-SiO 2 -Si nanocable
  • 103 is a C-SiO 2 nanocable.
  • Embodiments of a C-SiO 2 -SiC nanocable high-resolution TEM image and corresponding selected-area electron diffraction pattern are respectively presented in Figures 2 and 3. Further description of the nanocable devices used within the present disclosure are provided as experimental examples hereinbelow.
  • an electronic device in some embodiments herein, includes a dielectric material, at least one carbon sheet, and two electrode terminals.
  • the at least one carbon sheet is deposited on the dielectric material.
  • a first of the two electrode terminals forms a source and a second of the electrode terminals forms a drain.
  • the electronic device exhibits nonlinear current-versus-voltage response when operated over a voltage sweep range between the source and drain electrodes.
  • the at least one carbon sheet comprising the electronic device forms a discontinuous carbon layer.
  • the discontinuous carbon layer may be comprised by graphene sheets or graphite sheets in an embodiment. The discontinuous carbon layer is advantageous for fabricating certain embodiments of the electronic device, since the discontinuous carbon layer may be formed by, for example, chemical vapor deposition.
  • the at least one carbon sheet comprising the electronic device may be in a form that includes, but is not limited to, graphite, graphene, and graphene sheets. In some embodiments of the electronic device, the at least one carbon sheet is selected from a group consisting of graphene, graphite, and combinations thereof.
  • the dielectric material forming the electronic device may include, but is not limited to, silicon dioxide, silicon nitride, ceramics, glass, and plastic. In some embodiments of the electronic device, the dielectric material is selected from a group consisting of silicon dioxide, silicon nitride, glass, and plastic.
  • the device further includes a semiconductor.
  • the dielectric material maintains continuous contact with the semiconductor.
  • the semiconductor comprises a stacked silicon-on-insulator structure. Such arrangements are well known to those of skill in the relevant art.
  • Semiconductors may be elemental semiconductors, binary semiconductors, ternary semiconductors, ternary semiconductor alloys, quaternary semiconductor alloys, quinary semiconductor alloys, and organic semiconductors.
  • Exemplary but non-limiting semiconductor materials may include, but are not limited to, diamond, silicon, germanium, silicon carbide, silicon germanide, aluminium antimonide, aluminium arsenide, aluminium nitride, aluminium phosphide, boron nitride, boron phosphide, boron arsenide, gallium antimonide, gallium arsenide, gallium nitride, gallium phosphide, indium antimonide, indium arsenide, indium nitride, indium phosphide, cadmium selenide, cadmium sulfide, cadmium telluride, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, lead selenide, lead sulfide, lead telluride, tin sulfide, tin telluride, bismuth telluride, cadmium phosphide, cadmium arsenide,
  • Organic semiconductors suitable for practicing the disclosure may include single molecules, oligomers, and semiconducting polymers.
  • Exemplary but non-limiting organic semiconductors that may be used in practice of the embodiments disclosed herein may include pentacene, anthracene, rubrene, ⁇ oly(thio ⁇ hene)s, poly(aniline)s, poly(pyrrole)s, poly(p-phenylene vinylene), poly(acetylene), and derivatives and combinations thereof.
  • the semiconductor is selected from a group consisting of silicon, silicon carbide, gallium arsenide, and germanium.
  • a gate electrode further comprises the electronic device.
  • a gate electrode distinct from the source and the drain electrode terminals further comprises the electronic device.
  • the gate electrode influences performance of the semiconductor.
  • the gate electrode may be constructed on a material such as, but not limited to, silicon-on-insulator (SOI). Gated operation of the electronic device may beneficially alter the performance of the device in an embodiment.
  • the at least one carbon sheet is deposited from a gas comprising at least one carbon-containing compound.
  • the gas comprises hydrogen.
  • the at least one carbon-containing compound may be selected from a group consisting of acetylene, ethylene, methane, ethane, carbon monoxide, and combinations thereof in various embodiments.
  • the at least one carbon sheet is deposited at a temperature between about 400°C and about 900 0 C.
  • the at least one carbon sheet is deposited at a temperature between about 800 0 C and about 900 0 C.
  • the at least one carbon sheet is deposited by a process selected from a group consisting of ink-jet printing and solution-spin coating. Material deposited by the ink-jet printing and solution-spin coating techniques may be selected from a group consisting of exfoliated graphene, graphite, or combinations thereof in an embodiment.
  • the source and drain electrode terminals may be formed from various conductor or semiconductor materials in constructing the electronic devices.
  • Exemplary, but non-limiting, materials that may be used to form the source and drain may be selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof in an embodiment. Selection of the materials for constructing the source and drain electrodes is conducted independently.
  • One skilled in the art will recognize that the properties of the various electrode materials may confer advantageous properties to certain embodiments of the electronic device, and all such combinations of materials are fully within the spirit and scope of the present disclosure.
  • Certain electrical properties of the electronic devices disclosed herein give the devices advantageous benefits, particularly as two-terminal devices for switching and memory applications.
  • the devices disclosed herein exhibit BIV behavior and high PVRs in their current- versus- voltage response. Further, the transition from a low conduction state to a high conduction state is characterized by a sharp threshold voltage (V th ) occurring over a very narrow voltage transition.
  • V th threshold voltage
  • the switching and memory performance of the devices is somewhat variable from device to device based on variations in construction parameters, the electronic devices provide considerably advanced properties over existing two-terminal devices. All such operational variation lies within the spirit and scope of the disclosure.
  • Parameters which may affect the switching and memory performance of the electronic devices may include, but are not limited to, separation between the electrode terminals (channel length), dielectric material thickness, and thickness of the at least one carbon layer.
  • Threshold voltages are typically in the range of 6 - 12 V for devices with a channel length of 2 - 5 ⁇ m and below 5 V for devices with a channel length of ⁇ 1 ⁇ m.
  • ON/OFF switching ratios of 10 4 to 10 6 are typically observed.
  • the operational parameters presented hereinabove are merely exemplary and should not be considered limiting.
  • the nonlinear current-versus-voltage response includes at least about a 10-fold change in current over a voltage sweep range of about 0.5 V. In other embodiments of the electronic device, the nonlinear current-versus-voltage response includes a change in current between about 10-fold and 10 9 -fold over a voltage sweep range of about 0.5 V. In still other embodiments of the electronic device, the nonlinear current- versus-voltage response includes a change in current between about 10 5 -fold and 10 9 -fold over a voltage sweep range of about 0.5 V.
  • the electronic device is operated over a voltage sweep range of less than about 15 V. In other embodiments, the electronic device is operated over a voltage sweep range of less than about 5 V. In still other embodiments, the electronic device is operated over a voltage sweep range of less than about 1 V.
  • the electronic device comprises a two-terminal memory device having an ON/OFF memory state.
  • the electronic device has an ON/OFF ratio of at least about 100:1 for measuring recorded currents in the ON and OFF states.
  • High ON/OFF ratios are characteristic of the electronic devices as a result of their beneficial electronic properties noted hereinabove.
  • the ON/OFF ratios characteristic of the electronic devices make the devices well suited in applications in which two-terminal memory may be used.
  • a gate electrode further comprises the electronic device.
  • the gate electrode is above the at least one carbon layer.
  • the gate electrode is below the at least one carbon layer.
  • the gate electrode may modify current flow through the carbon sheet.
  • the electronic device may also include at least one nanowire in an embodiment.
  • the at least one nanowire lies between the source and the drain electrode terminals. Nanowires may be formed from several different types of nanomaterials and may be metallic, semiconducting, or insulating. Nanowires may be formed from either organic or inorganic materials, the choice of which and methods for formation thereof are well known to those versed in the relevant art.
  • the electronic device comprises at least one nanocable.
  • the at least one nanocable lies between the source and the drain electrode terminals.
  • the at least one nanocable comprises at least two layers.
  • the at least one nanocable comprises two layers.
  • the at least one nanocable comprises three layers.
  • An exemplary but non-limiting two-layer nanocable presented herein is a C-SiO 2 nanocable, which is defined and described hereinabove.
  • Exemplary three-layer nanocables include, but are not limited to, C-SiO 2 -SiC and C-SiO 2 -Si nanocables. Applicability of a particular nanocable for a given embodiment of the electronic device will be evident to one skilled in the art in view of the experimental examples presented hereinbelow.
  • the electronic device comprises a sensor. Operating the electronic device as a sensor may allow the electronic device to detect a wide range of molecules based on alteration of the observed electrical properties or BIV behavior of the device.
  • a molecule may become adsorbed to the at least one carbon sheet of the device and alter its electrical properties or BIV behavior. Such adsorption comprises an embodiment of non-covalent bonding.
  • a molecule may become covalently bound to the at least one carbon sheet of the device and alter its electrical properties or BIV behavior.
  • a wide range of molecules may be detected when the electronic device is operated as a sensor.
  • the at least one carbon sheet may be modified to alter its affinity for a given molecule, either in its low-conductance state, high-conductance state, or both low and high-conductance states.
  • Methods for modifying carbon sheets, such as graphene and graphite, are well known in the art, and any of these modification methods may be combined to provide affinity of the at least one carbon layer toward a given molecule.
  • Exemplary but non-limiting chemistries for modifying the carbon sheets may include the Billups reaction or Tour diazonium-based functionalization.
  • the Billups reaction includes reaction of the carbon sheet with an alkali metal, such as Li or Na, in liquid ammonia, followed by reaction with an electrophile, such as an alkyl halide, aryl halide, or carbonyl.
  • the Tour diazonium-based functionalization includes a radical-based introduction of aryl groups to the graphene or graphite sheet.
  • Related chemistries for covalently introducing functional groups to carbon nanotubes may be envisioned for functionalizing carbon sheets by those skilled in the art
  • the at least one carbon sheet is chemically functionalized with covalent bonds.
  • the covalent bonds may attach to a component selected from a group including, but not limited to, alkyl groups, aryl groups (arenes), halides, carboxylic acids, amines, substituted amines, amides, carboxylic esters, sulfonic acids, sulfonamides, alkoxy groups, and aryloxy groups.
  • the at least one carbon sheet may be bonded to a group capable of coordinating a metal ion, such as but not limited to a chelating group.
  • Functionalized graphene or graphite sheets may be covalently attached to biomolecules including, but not limited to, nucleic acids, DNA, RNA, oligonucleotides, polynucleotides, nucleosides, nucleotides, amino acids, peptides, oligopeptides, polypeptides, proteins, glycoproteins, enzymes, lipids, phospholipids, glycolipids, hormones, peptide hormones, neurotransmitters, carbohydrates, sugars, monosaccharides, disaccharides, trisaccharides, oligosaccharides, polysaccharides, antibodies, antibody fragments, and synthetic derivatives and analogs thereof.
  • the non-limiting functionalizations presented hereinabove may be used to alter the affinity of the at least one carbon sheet toward binding of a given molecule, biomolecule, or analyte.
  • the functionalizations may themselves alter the electrical properties of the at least one carbon sheet or provide greater affinity toward binding of a particular molecule, biomolecule, or analyte.
  • covalent bonds connect the at least one carbon sheet to at least one moiety chosen from a group consisting of alkyls, arenes, saccharides, peptides, nucleotides, halides, and combinations thereof.
  • operation of the electronic devices or sensors derived therefrom within the voltage sweep range promotes chemical functionalization of the at least one carbon sheet with covalent bonds.
  • chemical functionalization with covalent bonds may comprise functionalization of the at least one carbon sheet of the electronic devices or sensors derived therefrom, where the at least one carbon sheet is not previously functionalized with covalent bonds.
  • chemical functionalization with covalent bonds may comprise functionalization of the at least one carbon sheet of the electronic device or sensors derived therefrom, where the at least one carbon sheet previously comprised covalent bonds and is further modified.
  • operation of the electronic devices or sensors derived therefrom within the voltage sweep range promotes further modification through non- covalent bonding.
  • the carbon sheets coating the electronic device or sensors derived therefrom may adsorb molecules.
  • the carbon sheets are modified through non-covalent bonding.
  • the adsorbed molecules may change the electronic properties of the electronic devices or sensors derived therefrom.
  • Adsorbed molecules may comprise alkyl groups, aryl groups (arenes), halides, carboxylic acids, amines, substituted amines, amides, carboxylic esters, sulfonic acids, sulfonamides, alkoxy groups, aryloxy groups, and styrenes.
  • the electronic devices or sensors derived therefrom may be used for detecting a range of analytes based on changes in the observed BIV characteristics upon adsorption or desorption of molecules.
  • the carbon sheets may adsorb any of the biomolecules listed hereinabove to improve sensor sensitivity.
  • the at least one carbon sheet is modified through non-covalent bonding.
  • non-covalent bonding comprises adsorption of at least one moiety to the at least one carbon sheet.
  • the at least one moiety is chosen from a group consisting of alkyls, arenes, saccharides, peptides, nucleotides, halides, styrenes, and combinations thereof.
  • operation of the electronic devices or sensors derived therefrom within the voltage sweep range promotes chemical functionalization of the at least one carbon sheet with non-covalent bonds.
  • Non-covalent bonds may comprise adsorption of at least one molecule in an embodiment.
  • chemical functionalization with non- covalent bonds may comprise functionalization of the at least one carbon sheet of the electronic devices or sensors derived therefrom, where the at least one carbon sheet is not previously functionalized with non-covalent bonds.
  • chemical functionalization with non-covalent bonds may comprise functionalization of the at least one carbon sheet of the electronic devices or sensors derived therefrom, where the at least one carbon sheet previously comprised non-covalent bonds and is further modified.
  • operation of the electronic devices or sensors derived therefrom within the voltage sweep range promotes further modification through non-covalent bonding.
  • operation of the electronic device within the voltage sweep range promotes displacement of at least one molecule from the at least one carbon sheet comprising the electronic devices or sensors derived therefrom.
  • the at least one molecule displaced is covalently bound to the at least one carbon sheet.
  • the at least one molecule displaced is non- covalently bound to the at least one carbon sheet.
  • the at least one molecule displaced is adsorbed to the at least one carbon sheet.
  • the at least one molecule displaced comprises at least one analyte.
  • the electronic device comprises a logic switch. In some embodiments, the electronic device comprises a logic switch, where the electronic device further comprises a gate electrode above the at least one carbon sheet of the device. In some other embodiments, the electronic device comprises a logic switch, where the electronic device further comprises a gate electrode below the at least one carbon sheet of the device. In any of the various embodiments comprising a gate electrode, the gate electrode modifies current flow through the at least one carbon sheet of the electronic device comprising the logic switch.
  • analytical methods comprise: 1) providing the electronic device described hereinabove; 2) operating the electronic device over a voltage sweep range, where the operating step occurs in the presence of at least one analyte; and 3) observing current-versus-voltage performance of the electronic device in the presence of the at least one analyte.
  • the at least one analyte becomes bound to the at least one carbon sheet of the electronic device.
  • the methods further comprise removing the at least one analyte from the as least one carbon sheet after the operating step.
  • the methods comprise comparing the current-versus-voltage performance of the electronic device in the absence of the at least one analyte to the current-versus-voltage performance of the electronic device in the presence of the at least one analyte as described hereinabove. Such operation of the electronic device in the absence of an analyte permits the background performance of the electronic device to be obtained.
  • the magnitude of response of the electronic device may be proportional to the quantity of at least one analyte present. Operation of the device in the presence of known quantities of the at least one analyte may allow the electronic device to quantitate an unknown amount of the at least one analyte present.
  • Non-limiting techniques whereby such quantitation may be performed include calibration curve techniques and standard additions techniques. Analytical methods utilizing these techniques are within the capabilities of those having skill in the art. Use of the electronic devices described hereinabove in analytical methods using these techniques are within the capabilities of the ordinarily skilled artisan.
  • an electronic devices are prepared by a process comprising: 1) providing a dielectric material; 2) depositing at least one carbon sheet on the dielectric material; and 3) positioning two electrode terminals on the dielectric material, where the at least one carbon sheet lies between the two electrode terminals.
  • the electronic devices are prepared by a process that further comprises: applying a voltage sweep between the two electrode terminals, wherein the voltage sweep produces a nonlinear current-versus-voltage response.
  • a first of the two electrode terminals comprises a source and a second of the two electrode terminals comprises a drain.
  • the at least one carbon sheet forms a discontinuous carbon layer.
  • the at least one carbon sheet may be in a form that includes, but is not limited to graphite, graphene sheets, and graphene.
  • the at least one carbon sheet is selected from a group consisting of graphene and graphite.
  • the dielectric material may include, but is not limited to, silicon dioxide, silicon nitride, ceramics, glass, and plastic. In certain embodiments of the electronic devices prepared by the process disclosed hereinabove, the dielectric material is selected from a group consisting of silicon oxide, silicon nitride, glass, and plastic. In certain embodiments of the electronic devices prepared by the process disclosed hereinabove, the dielectric material maintains continuous contact with a semiconductor. Semiconductors suitable for use in the process of preparing the product include, but are not limited to, any of the semiconductors previously listed hereinabove.
  • the semiconductor is selected from a group consisting of silicon, silicon carbide, gallium arsenide, and germanium.
  • the process further comprises attaching a gate electrode to the electronic device.
  • the performance of the semiconductor is influenced by a gate electrode.
  • the gate electrode is distinct from the source and drain electrode terminals.
  • the electronic devices prepared by the process disclosed herein may utilize several different methods to deposit the at least one carbon sheet on the electronic device.
  • the process for forming the at least one carbon sheet of the devices comprises a depositing step performed with a gas comprising at least one carbon- containing compound.
  • Suitable carbon-containing compounds may include, but are not limited to, acetylene, ethylene, methane, ethane, carbon monoxide, and combinations thereof.
  • Deposition of the at least one carbon sheet may occur at a temperature between about 400 0 C and about 900 0 C in various embodiments, hi other embodiments, deposition of the at least one carbon sheet may occur at a temperature between about 800 0 C and about 900 0 C.
  • the process for forming the at least one carbon sheet of the device comprises a depositing step performed by ink-jet printing. In other embodiments of the electronic devices, the process for forming the at least one carbon sheet of the device comprises a depositing step performed by solution-spin coating. In embodiments of the electronic devices prepared by a process comprising ink-jet printing or solution-spin coating techniques, the at least one carbon sheet deposited by the technique may comprise graphene, graphite, or combinations thereof. The graphite or graphene may be previously exfoliated.
  • the electronic devices prepared by the process disclosed herein may utilize several different materials in constructing the two electrode terminals comprising the electronic device.
  • positioning the two electrodes comprises constructing the two electrodes from at least one material selected from a group consisting of platinum, palladium, gold, silver, silicon, gallium arsenide, titanium, tin, copper, and combinations thereof.
  • the selections of the at least one material for the source and for the drain are conducted independently of one another.
  • the process comprises applying a voltage sweep between the two electrode terminals comprising the device.
  • the voltage sweep produces a nonlinear current-versus-voltage response.
  • Application of a voltage sweep in preparing the electronic device may comprise a means whereby quality of the device fabrication is monitored. For example, in representative examples of the electronic devices not displaying BIV behavior, subsequent analyses of the electronic devices have revealed a simple open or closed circuit.
  • Application of a voltage sweep during electronic device fabrication may also comprise setting the electronic device into an initial conduction state for further processing.
  • applying a voltage sweep in preparing the electronic device may comprise a means of functionalizing the at least one carbon sheet with at least one molecule.
  • Functionalizing the at least one carbon sheet may comprise a covalent modification of the at least one carbon sheet during the step of applying a voltage sweep.
  • Functionalizing the at least one carbon sheet may also comprise a non-covalent modification of the at least one carbon sheet.
  • An exemplary state of non-covalent modification may include, but is not limited to, adsorption of at least one molecule to the carbon sheet.
  • a nonlinear current-versus- voltage response comprises a change in current between about 10-fold and 10 9 -fold over a voltage sweep range of about 0.5 V.
  • a nonlinear current-versus-voltage response comprises a change in current between about 10 5 -fold and 10 9 -fold over a voltage sweep range of about 0.5 V.
  • the process further comprises placing a gate electrode above the at least one carbon sheet. In certain other embodiments of the electronic devices prepared by the process disclosed hereinabove, the process further comprises placing a gate electrode below the at least one carbon sheet. In various embodiments, the gate electrode modifies current flow through the at least one carbon sheet.
  • the electronic devices prepared by the process disclosed hereinabove further comprise chemically functionalizing the at least one carbon sheet with covalent bonds. Such functionalization with covalent bonds may be carried out prior to depositing the at least one carbon sheet or after depositing the at least one carbon sheet. Functionalization with covalent bonds may also occur during operation of the electronic device, such as during the step of applying a voltage sweep to the device.
  • the electronic devices prepared by the process disclosed hereinabove further comprise chemically functionalizing the at least one carbon sheet with non-covalent bonds. Such functionalization with non-covalent bonds may be carried out prior to depositing the at least once carbon sheet or after depositing the at least one carbon sheet.
  • Functionalization with non- covalent bonds may also occur during operation of the electronic devices, such as during the step of applying a voltage sweep to the device.
  • functionalization of the at least one carbon sheet may comprise adsorption of at least one molecule to the at least one carbon sheet, where the at least one molecule is adsorbed on the at least one carbon sheet.
  • fiinctionalization of the at least one carbon sheet may comprise ionic bonding of at least one molecule to the at least one carbon sheet.
  • FIG. 4 An exemplary but non-limiting embodiment of a two-terminal electronic device and a process for preparing the device is described below and illustrated in Figure 4.
  • a wafer of dielectric material 401 such as " SiO 2 , for example, is presented and a pattern 402 is made on wafer 401.
  • the pattern 402 is made with chromium metal.
  • a protective layer 403 is then applied, coating the exposed dielectric material 401 and the pattern 402.
  • the protective layer comprises AI 2 O 3 applied in about a 10 nm thick layer.
  • the pattern 402 and the protective layer 403 overcoating 402 are removed, exposing a patterned surface of the dielectric material 401 following the removal process.
  • a carbon sheet 404 is then deposited, overcoating the exposed dielectric material 401 and the protective layer 403.
  • the carbon sheet 404 may comprise a discontinuous carbon layer in an embodiment.
  • the carbon sheet 404 typically includes graphene or graphite. Removal of the remaining protective layer 403 and its overcoating carbon sheet 404 leaves behind a patterned at least one carbon sheet 405 on the dielectric material 401. Positioning electrode terminals 406 at each end of the patterned at least one carbon sheet 405 completes assembly of this embodiment of the electronic device.
  • the electrode terminals 406 separately comprise a source electrode and a drain electrode.
  • Applying a voltage sweep to the completed device in an embodiment may be used as a non-limiting means of monitoring performance of the electronic device, setting an initial device conduction state, or functionalizing the patterned at least one carbon sheet 405.
  • All views shown in Figure 4 are side views of the electronic device, with the exception of the final view where the electrode terminals 406 are attached, which is a top view.
  • Example 1 C-SiO 2 -SiC Nanocable Electronic Devices
  • C-SiOi-SiC nanocables were prepared by a high temperature CVD process. As-synthesized C-SiO 2 -SiC nanocables were several ⁇ m in length and about 20 nm to about 50 nm in diameter.
  • the SiC nanowire core of each nanocable was comprised by a ⁇ -SiC single crystal.
  • the middle SiO 2 dielectric layer was about 2 nm to about 5 nm in thickness.
  • the outer carbon sheath was comprised by at least one graphene or graphite sheet or by multi-walled carbon nanorubes. Together, an assembly of multi-walled carbon nanorubes can be considered to comprise a defect-ridden graphene sheet wrapping the dielectric core of the nanocable.
  • C-SiO 2 -SiC nanocable-based two-terminal electronic device was prepared and characterized as follows.
  • C-SiO 2 -SiC nanocables were dispersed in ethyl alcohol with the aid of sonication and then deposited on the surface of Si 3 N 4 - or Si ⁇ 2 -covered highly doped Si substrates via spin coating.
  • the SisN 4 or SiO 2 dielectric layer was about 200 nm thick. Electrode terminals were then patterned over a deposited nanocable by either standard photolithography or electron-beam lithography techniques.
  • Photolithography produced long channel devices (>1 ⁇ m separation between source and drain electrode terminals), and electron-beam lithography produced short channel electronic devices ( ⁇ 1 ⁇ m separation between source and drain electrode terminals).
  • the electrode terminals were constructed from Pt and were about 100 nm thick for photolithography fabrication and about 50 nm thick for electron-beam lithography fabrication.
  • the nanocable electronic devices were characterized by SEM.
  • a representative embodiment of an SEM image of a long channel C-SiO 2 -SiC nanocable-based electronic device is shown in Figure 5 and that of a short channel C-SiO 2 -SiC nanocable-based electronic device is shown in Figure 6.
  • SEM observation only two-terminal electronic devices having a single nanocable bridging between the two electrode terminals were characterized.
  • Another C-SiO 2 -SiC nanocable electronic device with a channel length of 2.8 ⁇ m displayed BIV behavior at -8 V and +7.2 V with a PVR about 6700.
  • BIV was found on another C-SiO 2 -SiC nanocable electronic device with a channel length of 4.5 ⁇ m, producing V th values at -6.6 V and +8.4 V.
  • the PVR was -2800 at -6.6 V and 4.7 x 10 5 at +8.4 V in this device.
  • Repeatable BIV behavior was observed on more than 20 different long-channel nanocable devices with V th absolute values typically in the range of 6 - 12 V range and PVRs in the range of 10 3 -10 6 .
  • Short channel C-SiO?-SiC nanocable devices When the nanocable channel was shortened to below about 1 ⁇ m, the two-terminal C-SiO 2 -SiC nanocable electronic devices exhibited BIV behavior with lower V ⁇ . As shown in Figure 8, a C-SiO 2 -SiC nanocable electronic device with a channel length of 700 nm had BIV behavior at +5.2 V and -4.8 V with PVRs of 6500 and 2400, respectively. A C-SiO 2 -SiC nanocable electronic device having a channel length of 430 nm exhibited BIV behavior at +4.2 V and -4.0 V with PVRs of 7100 and 86000, respectively.
  • the short channel C-SiO 2 -SiC nanocable electronic devices have lower BIV V th than do the long channel C-SiO 2 -SiC nanocable devices, although the BIV V th is not directly proportional to channel length.
  • Table 1 A summary of the dependence of V th and PVR on C-SiO 2 -SiC nanocable channel length is presented in Table 1.
  • Example 2 ON/OFF Bias Switching Of C-SiO 2 -SiC Nanocable Electronic Devices
  • the two-terminal C-SiO 2 -SiC nanocable devices can be directly used for fast switching based on their BIV with high PVRs. To achieve an OFF state, the devices are operated at a relatively high reading bias (higher than V th ).
  • the nanocable electronic devices show distinct high- and low-conduction states under different bias sweeping protocols. As revealed in Figure 11, when a two-direction bias sweep (from 0 V to 10 V and then back to 0 V) was applied to a C- SiO 2 -SiC nanocable electronic device, the device exhibited BIV behavior similar to that described above for a one-direction bias sweep.
  • the device was in a low-conduction state at a bias below 3.6 V, in a high-conduction state at a bias between 3.8 - 7.1 V, and in an intermediate but relatively low conduction state at a bias higher than 7.1 V. Based on this bistable conduction feature, the two-terminal C-SiO 2 -SiC nanocable devices can be used in switching and memory applications.
  • a bias pulse higher than 7.1 V (for instance, 8 V) can be used as the erase bias 1101; a bias between 3.8 - 7.1 V (for instance, 4 V) can be used as the write bias 1102; and the low-conduction state and high-conduction state can be read at the same low-bias (for instance, 1 V) 1103.
  • Memory performance of long channel C-SiOi-SiC nanocable devices The memory performance of a C-SiO 2 -SiC nanocable electronic device having a long channel length of 2.8 ⁇ m is shown in Figure 12. As demonstrated in Example 1 above, this device exhibited BIV behavior at -8 V and +7.2 V with a PVR about 6700 for both V th . The ON/OFF memory states for this device could be switched by a +5 V write bias pulse for 1 s and +10 V erase bias pulse for 1 s, with an ON/OFF ratio of about 1.4 x 10 5 . After each write/erase operation, the deive current was read ten times consecutively at +1 V.
  • Figure 13 shows the performance of a long channel C-SiO 2 -SiC nanocable device having a channel length of 4.5 ⁇ m.
  • a pulse of +5 V for 1 s turns the device to the high-conduction ON state, and a +15 V pulse for 1 s changes the device to a low-conduction OFF state.
  • Figure 14 shows long term room-temperature memory reading performance of the C-SiO 2 -SiC nanocable device shown in Figure 13. After each write/erase operation, the current of the device was consecutively read at +1 V for 1000 times, in contrast to the shorter read times employed in Figure 13.
  • FIG. 17 Memory performance testing for additional short channel nanocable devices are presented in Figures 17 - 19.
  • the multi-cycle memory performance of a C-SiO 2 -SiC nanocable device having a channel length of 430 nm is presented in Figure 17.
  • the memory conduction states in this device were switched by a +3 V write bias pulse and a +6 V erase bias pulse.
  • the ON/OFF ratio of memory was higher than 5 x 10 4 .
  • Figure 18 shows the memory performance of a C-SiO 2 -SiC nanocable device having a channel length of 360 nm. This device exhibited BIV behavior at -4.4 V and +4.9 V, with respective PVRs of 12200 and 7100.
  • Figure 19 shows the memory performance of a C-SiO 2 -SiC nanocable device having a channel length of 700 nm.
  • the BIV behavior of this device was previously presented in Figure 8.
  • two different pulse times (0.1 or 1 second) were used to turn the memory ON with a +3 V write bias pulse or OFF with a +6 V erase bias pulse.
  • the results in Figure 19 showed that the shorter erasing pulse operation resulted in a higher OFF current, possibly due to an incomplete depletion process.
  • the ON currents did not show a clear difference. This result likely reveals that electron tunneling from C to SiC is faster than that from SiC to C.
  • Example 3 C-SiO 2 -Si and C-SiO 2 Nanocable Electronic Devices
  • SiNWs Single-crystal intrinsic silicon nanowires
  • SiCl 4 was used as the Si source.
  • a 5 nm Au thin film on a Si(IOO) substrate was used as the catalyst.
  • Catalytic growth of SiNWs occurred upon introducing a mixture of SiCl 4 , H 2 and Ar gases to the catalyst at 850 0 C.
  • the as-synthesized SiNWs were 50 - 120 nm in diameter.
  • the SiNWs were etched in 10 % HF etchant for 5 min to completely remove native oxide.
  • the SiNWs were then dry oxidized in air at 85O 0 C for 15 min to form a thin layer of SiO 2 approximately 5 nm in thickness for use in forming C-SiO 2 -Si nanocables. Oxidation at 1050 0 C for 2 hours to produced SiO 2 nanowires for use in forming C-SiO 2 nanocables.
  • a graphitic C layer was coated on the outer surface of SiO 2 -Si nanowires or SiO 2 nanowires by the thermal decomposition of C 2 H 2 , diluted with H 2 , at 900 0 C for 3 min in a tube furnace.
  • Two-terminal nanocable devices were thereafter fabricated using a similar photolithography route as described hereinabove for C-SiO 2 -SiC nanocable devices
  • a C-SiO 2 -Si nanocable device having a channel length of 1.9 ⁇ m showed a negative bias V t h of -10.5 V and a positive bias V th of +11.1 V, with PVRs of 1700 and 2100, respectively.
  • a C-SiO 2 -Si nanocable device with a channel length of 2.0 ⁇ m showed a negative bias V th of -9.6 V and a positive bias V th of +11.4 V, with PVRs of 1000 and 1100, respectively.
  • the PVR was 1.15 x 10 5 .
  • a gate bias was set at -20, 0, or +20 V, although application of a gate bias did little to influence the C-SiO 2 nanocable device performance.
  • the Si substrate of the device served as the gate electrode.
  • Figure 24 shows a bias sweeping sequence for another C-SiO 2 nanocable device having a channel length of 2.4 ⁇ m over 5 bias sweep cycles.
  • the device first remained in a low-conduction state at low bias, but the current sharply jumped from 37.5 nA at 3.06 V to 41.2 ⁇ A at 3.12 V.
  • the device remained in the high-conduction state until the bias increased to 6.84 V, where the current sharply decreased from a peak of 171 ⁇ A to a valley of 33 nA at 6.88 V, exhibiting a PVR of about 5200.
  • the device then remained in a low-conduction state as the bias was increased to 8 V, exhibiting similar behavior to that observed during the first sweep.
  • a third bias sweep from 0 V to 8 V produced a similar current-voltage curve.
  • the device During the reverse sweep, the device stayed in its low-conduction state until the bias reached 6.04 V where the current jumped from 26 nA to 118 ⁇ A at 5.99 V. Then the device remained in its high-conduction state when the bias decreased to 0 V.
  • FIG. 25 demonstrates the BIV read/write performance of a C-SiO 2 nanocable device having a channel length of 2.5 ⁇ m and a nanocable diameter of 110 nm.
  • Figure 26 shows the bistable memory switching performance of the same device switched to the high-conductance ON state with a pulse of +4 V and the low conductance OFF state with a pulse of +8 V, each pulse being conducted for 1 ms. After each write-erase operation, the device was read consecutively at +1 V ten times. For the C-SiO 2 nanocable device presented in Figure 26, the average ON/OFF ratio of this device is 4.6 x 10 5 .
  • Figure 27 presents the BIV read/write performance of another C-SiO 2 nanocable device having a channel length of 1.9 ⁇ m and a nanocable diameter of 110 nm.
  • a pulse of +4 V for 1 ms turns the device to the high-conduction ON state, and a pulse of +6 V for 1 ms returns the device to the low conduction OFF state.
  • the device current was read consecutively at +1 V 1000 times.
  • the average ON/OFF ratio was 4.4 x lO 7 .
  • Figure 29 presents the BIV read/write performance of another C-SiO 2 nanocable device having a channel length of 2.6 ⁇ m and a nanocable diameter of 140 nm.
  • the bistable memory switching performance of this device is shown in Figure 30.
  • a pulse of +4 V for 1 ms turns the device to the high conduction ON state, and a pulse of +8 V for 1 ms returns the device to the low conduction OFF state.
  • the device was read consecutively at +1 V five times. After 1000 cycles of write-read and erase-read operations, there was no degradation in the ON/OFF current readings.
  • the average ON/OFF ratio was 7.9 x 10 6 .
  • Figure 31 presents the BIV behavior of another C-SiO 2 nanocable device having a channel length of 1.5 ⁇ m and a nanocable diameter of 200 nm.
  • the bistable memory switching performance of this device is shown in Figure 32.
  • a pulse of +6 V for 1 ⁇ s turns the device to the high conduction ON state, and a pulse of +8 V for 100 ⁇ s returns the device to the low conduction OFF state.
  • the device was read consecutively at +1 V ten times.
  • the average ON/OFF ratio was 3.1 x 10 3 .
  • the data presented herein for nanocable electronic devices is for 1 ms bias pulses, the data presented in Figure 32 indicates that the devices can operate much faster. At shorter pulse times, however, a decrease in ON/OFF ratio was observed, and an increasing OFF current resulted.
  • the ON current was relatively invariant under the pulse conditions, which suggests that writing may be performed using shorter pulses than erasing.
  • FIG. 33 presents data obtained for two of the devices under these different testing conditions. BIV behaviors of these two devices before exposure to these different testing conditions are presented in Figures 34 and 35. As shown in Figure 33, one device was set to the OFF state with a +8 V pulse for 1 ms, and the other device was set to the ON state by a +6 V pulse for 1 ms. The device currents were then read consecutively every day at +1 V ten times. Some of the testing was performed at 200 0 C (data not shown), and there was no degradation in the devices or their memory retention properties.
  • both devices were exposed to ambient air for 24 hours and then returned to high vacuum conditions for testing. After eleven days, both devices were irradiated with 1 Grad(Si) of X-rays and returned to high vacuum conditions for testing. As shown in Figure 34, none of the extreme exposure conditions had significant effect on either the ON or OFF currents.
  • the level of radiation exposure provided to the samples is higher than that of the typical failure rate of conventional memory devices relying on charge storage, such as flash memories.
  • the nanocable electronic devices disclosed herein provide advantageous radiation stability.
  • Figure 36 shows SEM images of the C-Si ⁇ 2 nanocable devices presented in Figure 33 both before and after electrical property measurements presented hereinabove. Pre-testing image
  • 3603 is for the C-SiO 2 nanocable device set to the OFF state in Figure 33.
  • 3604 is for the C-SiO 2 nanocable device set to the ON state in Figure 33.
  • the regions of inset in images 3603 and 3604 are denoted by arrows in the respective images. Images 3603 and 3604 show a defect site following testing.
  • FIG. 37 shows the SEM images of a two-terminal MWCNT-based electronic device as prepared (image 3701) and after electrical breakdown (image 3702). As can be seen in Figure 37, electric breakdown occurred at a defect site. Recovery of conduction was not attainable for the MWCNT-based device. Similar defect site electrical breakdown occurred on the outer graphitic layer of a C-SiO 2 nanocable device similar to those presented hereinabove.
  • Example 7 Memory Performance of Two-Terminal Electronic Devices
  • a two-terminal electronic device having a carbon layer was fabricated according to the general procedure outlined hereinabove and demonstrated previously in Figure 4.
  • the two- terminal electronic device exhibited BIV properties, which were similar to those observed for C-SiO 2 , C-SiO 2 -Si and C-SiO 2 -SiC nanocable devices previously described hereinabove.
  • Figure 41 shows SEM images of the two-terminal electronic device both before (pre-testing image 4101) and after (post-testing image 4102) electrical breakdown.
  • the breakdown damage region 4103 in image 4102 is denoted by an arrow. Changes in the appearance of two-terminal electronic device observed after electrical property measurements were similar to the changes in the appearance of nanocable devices observed after electrical property measurements shown in Figure 36 and Figure 37.
  • a two-terminal carbon layer electronic device having a channel length of 2 ⁇ m, a width of 2 ⁇ m and a carbon layer thickness of 20 ran showed typical BIV characteristics.
  • the positive bias V th was +10.9 V.
  • the bistable memory switching performance of this device is shown in Figure 43.
  • a pulse of +8 V for 1 ⁇ s turned the device to the high conduction ON state, and a pulse of +15 V for 1 ⁇ s returned the device to the low conduction OFF state.
  • the device was read consecutively at +1 V 10 times. After 10000 cycles of write-read and erase-read operations, there was no degradation in the ON/OFF current readings.
  • the average ON/OFF ratio was 9.3 x 10 6 .

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Abstract

L'invention concerne ici des composants électroniques comprenant un matériau diélectrique, au moins une feuille de carbone et deux bornes d'électrodes. Les composants montrent des réponses courant - tension non linéaires sur une plage de balayage en tension dans divers modes de réalisation. L'invention concerne les utilisations des composants électroniques sous forme de dispositifs de mémoire à deux bornes, unités logiques, et capteurs. L'invention concerne des processus permettant de réaliser les composants électroniques. L'invention concerne des procédés pour utiliser les composants électroniques dans des procédés analytiques.
PCT/US2008/078152 2007-09-28 2008-09-29 Commutation électronique, mémoire et dispositifs de détecteurs à partir de feuilles de carbone sur des matériaux diélectriques WO2009043023A2 (fr)

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GB2471672B (en) * 2009-07-07 2015-12-09 Swansea Innovations Ltd Graphene biosensor
DE112010003772B4 (de) * 2009-09-25 2015-05-28 International Business Machines Corporation Aktivierung von Graphen-Pufferschichten auf Siliciumcarbid
US8481396B2 (en) 2009-10-23 2013-07-09 Sandisk 3D Llc Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same
US8551855B2 (en) 2009-10-23 2013-10-08 Sandisk 3D Llc Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same
US8551850B2 (en) 2009-12-07 2013-10-08 Sandisk 3D Llc Methods of forming a reversible resistance-switching metal-insulator-metal structure
US8389375B2 (en) 2010-02-11 2013-03-05 Sandisk 3D Llc Memory cell formed using a recess and methods for forming the same
US8237146B2 (en) 2010-02-24 2012-08-07 Sandisk 3D Llc Memory cell with silicon-containing carbon switching layer and methods for forming the same
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