WO2009041802A1 - Method in eliminating polycide stringer in double poly analog mixed signal (ams) device - Google Patents
Method in eliminating polycide stringer in double poly analog mixed signal (ams) device Download PDFInfo
- Publication number
- WO2009041802A1 WO2009041802A1 PCT/MY2008/000105 MY2008000105W WO2009041802A1 WO 2009041802 A1 WO2009041802 A1 WO 2009041802A1 MY 2008000105 W MY2008000105 W MY 2008000105W WO 2009041802 A1 WO2009041802 A1 WO 2009041802A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- poly
- polysilicon
- stringer
- eliminating
- poly2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
- H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
- H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
- H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
- H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
- H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components
Definitions
- the present invention relates generally to elimination of polycide stringer, and more particularly to a method of eliminating the polycide stringer formed during the fabrication of Poly-Insulator-poly (PIP) Analog Mixed Signal (AMS) device using 0.35 ⁇ rh-CMOS process technology.
- PIP Poly-Insulator-poly
- AMS Analog Mixed Signal
- a memory device for storing data has a great significance in a data processing system.
- Memory devices such as random access memory (RAM), read-only memory (ROM), and the like, are known in the art.
- Non-volatile memory devices and particularly so-called “flash” memory devices, have become increasingly more popular in data storage applications.
- a flash memory is a nonvolatile memory, which can preserve data within the memory even when an external power supply is lost.
- flash memory is re-writable and re-erasable, it has been widely applied in the fabrication of electrical products, such as mobile phones, digital cameras, video players, personal digital assistants (PDA) or system on a chip (SOC).
- PDA personal digital assistants
- SOC system on a chip
- the top plate capacitor (poly2) is formed by depositing polysilicon and tungsten silicide (WSix) sequentially, which is then patterned and etched using reactive ion etching (RIE) method.
- RIE reactive ion etching
- a type of residue was found alongside the PIP capacitor structure after the poly2 etching process.
- An electron microscope (FESEM) cross-sectional view ( Figure 1) of the capacitor and Energy dispersive X-ray spectroscopy (EDS) analysis confirmed that the residue consisted of poly and tungsten silicide material, hence called the polycide stringer. It was understood that the stringer was left unetched during poly2 etching process due to high topography of the PIP structure. The presence of polycide stringer may cause resistive short or unwanted electrical connection within the device, which will consequently deteriorate the operational characteristics and reliability of the PEP AMS devices.
- US-A-5,933,729 disclosed method of preventing the formation of poly stringers during the fabrication of a memory device by reducing the height of the ONO (oxide-nitride-oxide) fence during a self-aligned etch ("SAE") step.
- SAE self-aligned etch
- the shortened ONO fence provides reduced lateral shielding of polysilicon material during a subsequent polysilicon etch, thereby preventing poly stringers from being formed and improving the manufacturability of the memory device.
- a new ONO etch recipe is utilized which exhibits a substantially greater ONO-to-polysilicon selectivity. Consequently, a longer overetch of the ONO layer may be conducted without substantially impacting the underlying polysilicon.
- the overetch reduces the height of the ONO fence and thereby reduces its lateral shielding of polysilicon.
- the reduced lateral shielding prevents the formation of poly stringers during a subsequent etch of the polysilicon.
- AMS analog mixed signal
- AMS stringerless analog mixed signal
- a method for eliminating formation of stringers in an analog mixed signal (AMS) device comprising the steps of:-
- poly-insulator-poly capacitor having first polysilicon (polyl) (1) layer set at the bottom and second polysilicon (poly2) (2) layer set at the top;
- said dielectric layer sandwiched between said polyl (1) and said poly2 (2) layer, said dielectric layer includes an oxide-nitride-oxide (ONO);
- polyl (1) is undoped polysilicon film deposited on top of the Field Oxide after Sacrificial Oxidation.
- poly 2 (2) is a combination of doped poly and tungsten silicide films.
- FIG 1 shows FESEM cross-section image of poly stringer defects.
- FIG 2 shows FESEM cross-section image of stringer completely eliminated.
- a poly-insulator-poly (PIP) Analog Mixed Signal (AMS) device using 0.35 ⁇ m CMOS technology features has been fabricated.
- the advantage of a PEP capacitor as compared to the other types of capacitor is its higher capacitance density value.
- the PIP capacitor consists of a thin oxide-nitrite-oxide (ONO) film sandwiched between two polysilicon films.
- the bottom polysilicon (polyl) layer (1) is the capacitor bottom plate
- the thin ONO film stack acts as a dielectric layer
- the capacitor top plate (poly2) (2) is a combination of doped poly and tungsten silicide films.
- the fabrication of the PEP module starts with a layer of undoped polysilicon film deposited on top of the Field Oxide after Sacrificial Oxidation, to form the bottom plate capacitor. Then, the poly layer is implanted with phosphorus to achieve the targeted sheet resistance. The implanted poly is then annealed at 800°C for 30 minutes to activate the dopants. The next process step is the formation of the dielectric, ONO layer. 4OA of thermal oxide is grown on the polyl film followed by deposition of 200A LPCVD silicon nitride. The final oxide layer is formed on the nitride surface during the gate oxidation process. The next step is to pattern and etch the polysilicon bottom plate (polyl) (1).
- the top ONO layer is then etched away using dry oxide etcher followed by polysilicon reactive ion etch.
- the subsequent process step is to form the capacitor top plate (poly2) (2).
- the capacitor top plate will also function as the Logic Gate material in the CMOS area.
- a layer of LPCVD polysilicon film is deposited over the patterned polyl (1) structure.
- a PECVD tungsten suicide (WSix) filnr is then deposited followed by deposition of a thin PECVD silicon oxynitride (SiON).
- the SiON film acts as an anti-reflective coating (ARC) during the polysilicon gate patterning (lithography) process.
- the poly2 (2) film is then patterned and etched using a polysilicon reactive ion etcher.
- the process flow continues with a standard logic CMOS process.
- the second approach was aimed at reducing the WSix thickness by tapering the polyl sidewall profile to an angle of about 75°.
- the current etching recipe for the polyl (1) etch produced a near vertical sidewall profile.
- the baseline etch recipe consisted a combination of Cl 2 and HBr gases at 1:1.6 ratio, 480 Watt RF source power, 80 Watt RF bias power and 8mTorr pressure. Three factors i.e. Cl 2 and HBr gas flow and pressure were varied.
- the sidewall angle produced was then calculated based on FESEM cross-section.
- the best polyl (1) taper profile achieved was then integrated with the standard tungsten etch recipe and the height of the stringer remained was then measured from the FESEM cross-section.
- Another technique to reduce the WSix thickness at the polyl sidewall is by reducing the thickness of the polyl (1) itself.
- three thicknesses were experimented.
- Three types of PIP stack structure were prepared having polyl (1) thickness 2500A, 2000A and 1500A.
- the baseline poly2 (2) etch recipe was used in the experiment for all three types of structures.
- FESEM cross-section were carried out to measure the remaining height of the stringer (3).
- Figure 3 shows a summarization table of experiments undertook in optimizing the etching process for elimination of the stringers as mentioned above.
- the figures clearly show the improvement made on the etching process had resulted in reduction of the height of the stringers until the last process which the stringers had completely eliminated.
Landscapes
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a method of eliminating stringers (3) formed during a fabrication of poly-insulator-poly (PIP) Analog Mixed Signal (AMS) device using 0.35μm CMOS process technology. Using 1500A polyl (1) thickness with fine tuning of poly2 (2) etch process condition in the tungsten silicide and poly etch steps had been proven successful in eliminating the stringer (3) completely. The tungsten overetch was increased from 30% to 80%. The poly and WSix etch rates in the poly etch step were made about equal by increasing pressure from 4mTorr to 12mTorr and RF power was increased from 480 Watt to 620 Watt. In addition, the poly overetch step was increased from 90 to 130 seconds.
Description
METHOD IN ELIMINATING POLYCIDE STRINGER IN DOUBLE POLY ANALOG MIXED SIGNAL (AMS) DEVICE
1. TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to elimination of polycide stringer, and more particularly to a method of eliminating the polycide stringer formed during the fabrication of Poly-Insulator-poly (PIP) Analog Mixed Signal (AMS) device using 0.35 μrh-CMOS process technology.
2. BACKGROUND OF THE INVENTION
A memory device for storing data has a great significance in a data processing system. Memory devices, such as random access memory (RAM), read-only memory (ROM), and the like, are known in the art. Non-volatile memory devices, and particularly so-called "flash" memory devices, have become increasingly more popular in data storage applications. A flash memory is a nonvolatile memory, which can preserve data within the memory even when an external power supply is lost. Recently, because flash memory is re-writable and re-erasable, it has been widely applied in the fabrication of electrical products, such as mobile phones, digital cameras, video players, personal digital assistants (PDA) or system on a chip (SOC).
In the fabrication of PEP AMS devices using 0.35um CMOS process technology, the top plate capacitor (poly2) is formed by depositing polysilicon and tungsten silicide (WSix) sequentially, which is then patterned and etched using reactive ion etching (RIE) method. A type of residue was found alongside the PIP capacitor structure after the poly2 etching process. An electron microscope (FESEM) cross-sectional view (Figure 1) of the capacitor and Energy dispersive X-ray spectroscopy (EDS) analysis confirmed that the residue consisted of poly and tungsten silicide material, hence called the polycide stringer. It was understood that the stringer was left unetched during poly2
etching process due to high topography of the PIP structure. The presence of polycide stringer may cause resistive short or unwanted electrical connection within the device, which will consequently deteriorate the operational characteristics and reliability of the PEP AMS devices.
In US-A-5,342,801, there is disclosed a fabrication of EPROM devices in a way which avoids the creation of polysilicon stringers. More specifically, the plasma etching process of the invention, where instead of providing only vertical or anisotropic etching, it also provides controlled isotropic etching. In other words, horizontal etching can take place simultaneously with vertical etching, however, at a controlled and therefore, slower rate. Therefore, the polysilicon are eliminated during the row space forming etching process because material removal occurs in the horizontal direction as well as the vertical direction.
In US-A-5,723,374, it is disclosed a method of forming dielectric spacer along the slope of the bit line contact hole edge to prevent poly stringers in DRAM technology.
US-A-5,933,729 disclosed method of preventing the formation of poly stringers during the fabrication of a memory device by reducing the height of the ONO (oxide-nitride-oxide) fence during a self-aligned etch ("SAE") step. The shortened ONO fence provides reduced lateral shielding of polysilicon material during a subsequent polysilicon etch, thereby preventing poly stringers from being formed and improving the manufacturability of the memory device. According to one aspect of the invention, a new ONO etch recipe is utilized which exhibits a substantially greater ONO-to-polysilicon selectivity. Consequently, a longer overetch of the ONO layer may be conducted without substantially impacting the underlying polysilicon. The overetch reduces the height of the ONO fence and thereby reduces its lateral shielding of polysilicon. The reduced lateral shielding prevents the formation of poly stringers during a subsequent etch of the polysilicon.
There are quite a number of other US patent documents disclosing methods of eliminating stringers which formed during fabricating of memory devices. However, the proposed prior methods are either exceedingly complicated that require various steps thus raised the issue of complexity and cost, or difficult to perform thus raised the issue of reliability. The present invention overcomes such problems mentioned above by optimizing polysilicon gate etching condition.
3. SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating an analog mixed signal (AMS) using CMOS technology to solve the above-mentioned problems.
It is another object of the present invention to provide a method of fabricating a stringerless analog mixed signal (AMS) to achieve better reliability.
These and other objects of the present invention are achieved by,
A method for eliminating formation of stringers in an analog mixed signal (AMS) device comprising the steps of:-
forming of poly-insulator-poly capacitor having first polysilicon (polyl) (1) layer set at the bottom and second polysilicon (poly2) (2) layer set at the top;
a dielectric layer sandwiched between said polyl (1) and said poly2 (2) layer, said dielectric layer includes an oxide-nitride-oxide (ONO);
characterized in that,
said polysilicon bottom layer (poly 1) (1) having height of not more than 1500A, said polysilicon top layer (poly2) (2) is subjected to that etching process comprises of tungsten overetch increased to at least 80 %, maintaining the etching
rate of said poly2 (2) and tungsten silicide material (WSix) while increasing pressure from 4mTorr to 12mTorr, increasing RF power from 480 Watt to 620 Watt and poly overetch step increased from 90 seconds to 130 seconds.
Preferably, polyl (1) is undoped polysilicon film deposited on top of the Field Oxide after Sacrificial Oxidation.
More preferably, poly 2 (2) is a combination of doped poly and tungsten silicide films.
4. BRIEF DESCRIPTION OF THE DRAWINGS
Other aspect of the present invention and their advantages will be discerned after studying the Detailed Description in conjunction with the accompanying drawings in which :
FIG 1 shows FESEM cross-section image of poly stringer defects.
FIG 2 shows FESEM cross-section image of stringer completely eliminated.
5. DETAIL DESCRIPTION OF TBDE DRAWINGS
A poly-insulator-poly (PIP) Analog Mixed Signal (AMS) device using 0.35μm CMOS technology features has been fabricated. The advantage of a PEP capacitor as compared to the other types of capacitor is its higher capacitance density value. The PIP capacitor consists of a thin oxide-nitrite-oxide (ONO) film sandwiched between two polysilicon films. The bottom polysilicon (polyl) layer (1) is the capacitor bottom plate, the thin ONO film stack acts as a dielectric layer and the capacitor top plate (poly2) (2) is a combination of doped poly and tungsten silicide films.
The fabrication of the PEP module starts with a layer of undoped polysilicon film deposited on top of the Field Oxide after Sacrificial Oxidation, to
form the bottom plate capacitor. Then, the poly layer is implanted with phosphorus to achieve the targeted sheet resistance. The implanted poly is then annealed at 800°C for 30 minutes to activate the dopants. The next process step is the formation of the dielectric, ONO layer. 4OA of thermal oxide is grown on the polyl film followed by deposition of 200A LPCVD silicon nitride. The final oxide layer is formed on the nitride surface during the gate oxidation process. The next step is to pattern and etch the polysilicon bottom plate (polyl) (1). The top ONO layer is then etched away using dry oxide etcher followed by polysilicon reactive ion etch. The subsequent process step is to form the capacitor top plate (poly2) (2). The capacitor top plate will also function as the Logic Gate material in the CMOS area. A layer of LPCVD polysilicon film is deposited over the patterned polyl (1) structure. A PECVD tungsten suicide (WSix) filnr is then deposited followed by deposition of a thin PECVD silicon oxynitride (SiON). The SiON film acts as an anti-reflective coating (ARC) during the polysilicon gate patterning (lithography) process. The poly2 (2) film is then patterned and etched using a polysilicon reactive ion etcher. The process flow continues with a standard logic CMOS process.
An electron microscope (FESEM) cross-section (Figure 1) of the capacitor and EDS analysis confirmed that stringer (3) was formed during the poly2 (2) etching process due to topography of the PIP structure. The stringer (3) was consisted of poly and tungsten suicide material. The presence of poly stringer (3) defect could deteriorate the operational characteristics and reliability of the AMS device. Therefore, several experimental approaches were performed to find a solution to this issue. However, processing on both PIP module and CMOS device simultaneously is challenging. A process which avoids the formation of poly stringer (3) as well as maintaining a good polysilicon gate profile has to be developed.
Several experiments were conducted in order to solve the above mentioned problems. The first technique attempted in eliminating the stringer (3) was by increasing the overetch time in the tungsten etch recipe. Initial test using a
50% tungsten overetch step had resulted in undercut of polycide gate profile in logic area. Therefore, the etch selectivity of WSix:Poly is improved from the current selectivity of 1:1. The current baseline recipe for tungsten etch uses a combination of Cl2, O2 and N2 gases at 1400 Watt RP power and 8mTorr pressure. A few experiments had been performed varying some factors such as gas flow, pressure, and power setting in search of a good parameter combination to improve the WSix:Poly selectivity. Additional gas such as SF6, CF4 and Ar were also tested to check their effect on WSix and Poly etch rate.
The second approach was aimed at reducing the WSix thickness by tapering the polyl sidewall profile to an angle of about 75°. The current etching recipe for the polyl (1) etch produced a near vertical sidewall profile. The baseline etch recipe consisted a combination of Cl2 and HBr gases at 1:1.6 ratio, 480 Watt RF source power, 80 Watt RF bias power and 8mTorr pressure. Three factors i.e. Cl2 and HBr gas flow and pressure were varied. The sidewall angle produced was then calculated based on FESEM cross-section. The best polyl (1) taper profile achieved was then integrated with the standard tungsten etch recipe and the height of the stringer remained was then measured from the FESEM cross-section.
Another technique to reduce the WSix thickness at the polyl sidewall is by reducing the thickness of the polyl (1) itself. In order to find the optimum poly thickness to be used, three thicknesses were experimented. Three types of PIP stack structure were prepared having polyl (1) thickness 2500A, 2000A and 1500A. The baseline poly2 (2) etch recipe was used in the experiment for all three types of structures. In order to verify the effectiveness of each technique in eliminating the stringer, FESEM cross-section were carried out to measure the remaining height of the stringer (3).
Another approach gave a better result in term of reducing the height of the stringer (3). Using 1500A polyl (1) thickness with baseline poly2 (2) etch recipe, the height of the stringer (3) was reduced by 66%. A new optimized poly2 (2)
etch process was developed. The tungsten overetch was increased from 30% to 80%. The poly and WSix etch rates in the poly etch step were made about equal by increasing pressure from 4mTorr to 12mTorr and RF power was increased from 480 Watt to 620 Watt. In addition, the poly overetch step was increased from 90 to 130 seconds. FESEM cross-section view (Figure 2) of the PIP stack verified that the stringer (3) is no longer exists. A FESEM cross-section of the poly gate profile at the CMOS area also showed no poly undercut. The experimental results from the three types of approaches are summarized in Figure 3.
Figure 3 shows a summarization table of experiments undertook in optimizing the etching process for elimination of the stringers as mentioned above. The figures clearly show the improvement made on the etching process had resulted in reduction of the height of the stringers until the last process which the stringers had completely eliminated.
While a particular form of the present invention has been illustrated and described, it will be apparent that many varying embodiments with various modification can be made without departing from the scope of the invention. Therefore, it is understood that the detail herein are to be interpreted as illustrative and not in a limiting sense.
Claims
1. A method for eliminating formation of stringers in an analog mixed signal (AMS) device comprising the steps of:-
forming of poly-insulator-poly capacitor having first polysilicon (polyl) (1) layer set at the bottom and second polysilicon (poly2) (2) layer set at the top;
a dielectric layer sandwiched between said polyl (1) and said poly2 (2) layer, said dielectric layer includes an oxide-nitride-oxide (ONO);
characterized in that,
said polysilicon bottom layer (poly 1) (1) having height of not more than 1500A, said polysilicon top layer (ρoly2) (2) is subjected to that etching process comprises of tungsten overetch increased to at least 80 %, maintaining the etching rate of said poly2 (2) and tungsten suicide material (WSix) while increasing pressure from 4mTorr to 12mTorr, increasing RF power from 480 Watt to 620 Watt and poly overetch step increased from 90 seconds to 130 seconds.
2. A method for eliminating formation of stringers in a memory device as claimed in Claim 1, further characterized in that said polyl (1) is undoped polysilicon film deposited on top of the Field Oxide after Sacrificial Oxidation.
3. A method for eliminating formation of stringers in a memory device as claimed in Claim 1, further characterized in that said poly 2 (2) is a combination of doped poly and tungsten silicide films.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| MYPI20071620 | 2007-09-26 | ||
| MYPI20071620A MY144982A (en) | 2007-09-26 | 2007-09-26 | Method in eliminating polycide stringer in double poly analog mixed signal (ams) device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2009041802A1 true WO2009041802A1 (en) | 2009-04-02 |
Family
ID=40511634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/MY2008/000105 Ceased WO2009041802A1 (en) | 2007-09-26 | 2008-09-19 | Method in eliminating polycide stringer in double poly analog mixed signal (ams) device |
Country Status (2)
| Country | Link |
|---|---|
| MY (1) | MY144982A (en) |
| WO (1) | WO2009041802A1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10209309A (en) * | 1996-12-24 | 1998-08-07 | Hyundai Electron Ind Co Ltd | Method for manufacturing semiconductor device |
| KR19990026509A (en) * | 1997-09-25 | 1999-04-15 | 윤종용 | Capacitor Formation Method |
| US6548406B2 (en) * | 2001-08-17 | 2003-04-15 | Macronix International Co., Ltd. | Method for forming integrated circuit having MONOS device and mixed-signal circuit |
| KR100650860B1 (en) * | 2005-12-01 | 2006-11-27 | 동부일렉트로닉스 주식회사 | Capacitor Manufacturing Method |
-
2007
- 2007-09-26 MY MYPI20071620A patent/MY144982A/en unknown
-
2008
- 2008-09-19 WO PCT/MY2008/000105 patent/WO2009041802A1/en not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10209309A (en) * | 1996-12-24 | 1998-08-07 | Hyundai Electron Ind Co Ltd | Method for manufacturing semiconductor device |
| KR19990026509A (en) * | 1997-09-25 | 1999-04-15 | 윤종용 | Capacitor Formation Method |
| US6548406B2 (en) * | 2001-08-17 | 2003-04-15 | Macronix International Co., Ltd. | Method for forming integrated circuit having MONOS device and mixed-signal circuit |
| KR100650860B1 (en) * | 2005-12-01 | 2006-11-27 | 동부일렉트로닉스 주식회사 | Capacitor Manufacturing Method |
Also Published As
| Publication number | Publication date |
|---|---|
| MY144982A (en) | 2011-12-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8076230B2 (en) | Method of forming self-aligned contacts and local interconnects | |
| US6338994B1 (en) | Semiconductor device and method of fabricating thereof | |
| US7727893B2 (en) | Method of forming a dielectric layer pattern and method of manufacturing a non-volatile memory device using the same | |
| US7332775B2 (en) | Protruding spacers for self-aligned contacts | |
| US7303958B2 (en) | Semiconductor device and method of manufacturing the same | |
| US6455374B1 (en) | Method of manufacturing flash memory device | |
| US9287285B2 (en) | Self-aligned liner method of avoiding PL gate damage | |
| US7112486B2 (en) | Method for fabricating semiconductor device by using radical oxidation | |
| CN100428416C (en) | Method for producing semiconductor device | |
| CN100514595C (en) | Method for forming contact in semiconductor device | |
| US7741203B2 (en) | Method of forming gate pattern of flash memory device including over etch with argon | |
| KR100954107B1 (en) | Method of manufacturing semiconductor device | |
| US7846795B2 (en) | Bit line of a semiconductor device and method for fabricating the same | |
| US8026139B2 (en) | Method of fabricating a non-volatile memory device | |
| WO2009041802A1 (en) | Method in eliminating polycide stringer in double poly analog mixed signal (ams) device | |
| US6140218A (en) | Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation | |
| US7223657B2 (en) | Methods of fabricating flash memory devices with floating gates that have reduced seams | |
| US6548334B1 (en) | Capping layer | |
| US8039345B2 (en) | Methods of forming semiconductor devices | |
| US7067374B2 (en) | Manufacturing methods and structures of memory device | |
| US20050202631A1 (en) | Poly-etching method for split gate flash memory cell | |
| US20240381634A1 (en) | Semiconductor device manufacturing method | |
| US6133151A (en) | HDP-CVD method for spacer formation | |
| US20060011968A1 (en) | Semiconductor devices and methods of forming the same | |
| KR100964272B1 (en) | How to Form a Polymetal Gate Stack |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08834385 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 08834385 Country of ref document: EP Kind code of ref document: A1 |