MY144982A - Method in eliminating polycide stringer in double poly analog mixed signal (ams) device - Google Patents

Method in eliminating polycide stringer in double poly analog mixed signal (ams) device

Info

Publication number
MY144982A
MY144982A MYPI20071620A MYPI20071620A MY144982A MY 144982 A MY144982 A MY 144982A MY PI20071620 A MYPI20071620 A MY PI20071620A MY PI20071620 A MYPI20071620 A MY PI20071620A MY 144982 A MY144982 A MY 144982A
Authority
MY
Malaysia
Prior art keywords
poly
eliminating
stringer
mixed signal
etch
Prior art date
Application number
MYPI20071620A
Inventor
Ahmad Sabirin Bin Zoolfakar
Khairul Amalin Bin Abd Rahman
Azlina Bt Mohd Zain
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Priority to MYPI20071620A priority Critical patent/MY144982A/en
Priority to PCT/MY2008/000105 priority patent/WO2009041802A1/en
Publication of MY144982A publication Critical patent/MY144982A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

METHOD IN ELIMINATING POLYCIDE STRINGER IN DOUBLE POLY ANALOG MIXED SIGNAL (ANIS) DEVICE THE INVENTION RELATES TO A METHOD OF ELIMINATING STRINGERS (3) FORMED DURING A 5 FABRICATION OF POLY-INSLILATOR-POLY (PIP) ANALOG MIXED SIGNAL (AMS) DEVICE USING 035LTM CMOS PROCESS TECHNOLOGY. USING 1500A POLYL (1) THICKNESS WITH FINE TUNING OF POLY2 (2) ETCH PROCESS CONDITION IN THE TUNGSTEN SILICIDE AND POLY ETCH STEPS HAD BEEN PROVEN SUCCESSFUL IN ELIMINATING THE STRINGER (3) COMPLETELY. THE TUNGSTEN OVERETCH WAS INCREASED FROM 30TO 80THE POLY AND WSIX ETCH 10 RATES IN THE POLY ETCH STEP WERE MADE ABOUT EQUAL BY INCREASING PRESSURE FROM 4MTORR TO L2MTORR AND RF POWER WAS INCREASED FROM 480 WATT TO 620 WATT. IN ADDITION, THE POLY OVERETCH STEP WAS INCREASED FROM 90 TO 130 SECONDS. MOST ILLUSTRATIVEFIGURE IS
MYPI20071620A 2007-09-26 2007-09-26 Method in eliminating polycide stringer in double poly analog mixed signal (ams) device MY144982A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
MYPI20071620A MY144982A (en) 2007-09-26 2007-09-26 Method in eliminating polycide stringer in double poly analog mixed signal (ams) device
PCT/MY2008/000105 WO2009041802A1 (en) 2007-09-26 2008-09-19 Method in eliminating polycide stringer in double poly analog mixed signal (ams) device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MYPI20071620A MY144982A (en) 2007-09-26 2007-09-26 Method in eliminating polycide stringer in double poly analog mixed signal (ams) device

Publications (1)

Publication Number Publication Date
MY144982A true MY144982A (en) 2011-12-15

Family

ID=40511634

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI20071620A MY144982A (en) 2007-09-26 2007-09-26 Method in eliminating polycide stringer in double poly analog mixed signal (ams) device

Country Status (2)

Country Link
MY (1) MY144982A (en)
WO (1) WO2009041802A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100223769B1 (en) * 1996-12-24 1999-10-15 김영환 Method for forming dielectric film of memory device
KR19990026509A (en) * 1997-09-25 1999-04-15 윤종용 Capacitor Formation Method
US6548406B2 (en) * 2001-08-17 2003-04-15 Macronix International Co., Ltd. Method for forming integrated circuit having MONOS device and mixed-signal circuit
KR100650860B1 (en) * 2005-12-01 2006-11-27 동부일렉트로닉스 주식회사 Manufacturing method of capacitor

Also Published As

Publication number Publication date
WO2009041802A1 (en) 2009-04-02

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