WO2009037618A2

WO2009037618A2 - Method for restoring dc balance

Info

Publication number: WO2009037618A2
Application number: PCT/IB2008/053685
Authority: WO
Inventors: Gerrit Willem Den Besten
Original assignee: Nxp B.V.
Priority date: 2007-09-18
Filing date: 2008-09-12
Publication date: 2009-03-26
Also published as: WO2009037618A3

Abstract

The invention refers to a transmission system adapted to fulfill a signaling scheme comprising a start up signaling method, the start-up signaling method comprising a step of restoring DC balance upfront by inserting a Balance Equalization Sequence (BES).

Description

BALANCE EQUALIZATION METHOD

FIELD OF THE INVENTION

The invention relates to a DC balance equalization method.

BACKGROUND OF THE INVENTION The typically applied interconnect media for signal transport are dispersive, which means that the signal group delay varies over frequency. This causes the transported signals to distort as some signal frequencies are traveling faster through the interconnections than others, besides the effect of frequency dependent attenuation. For example in electrical conductors the traveling-speed can slow down significantly for low frequencies due to the skin effect. This becomes especially important for long interconnect as it there can take a long time before the signal is fully settled.

A typical transmission system is shown in Fig. 1.

One measure to tackle this problem is to use DC balanced coding, like for example 8Bl OB coding for high-speed binary data transmission. DC balanced coding highly reduces low- frequency content, especially if the Running (Digital) Sum (RDS), which is the integral of the data values relative to their average value, is tightly. In this way, acceptable signal integrity can be maintained even for severe losses on the interconnections signals. In many practical cases, this enables a higher effective available bandwidth then without a balanced coding. For clarity reasons, it should be mentioned that DC balance means here that the long-term average of the communicated data values remains constant. Therefore, when binary signaling is used, this implies on average the same number of "1" and "0" signals occur over a certain amount of time. DC balance is independent of the choice whether the signaling is implemented differentially. In a differential communication system the signal values representing the data are implemented in a balanced way. However, differential signaling can still be DC balanced or non-DC-balanced depending on the applied coding of the transmitted data.

In practice the data transmission will likely not continue forever. Sooner of later it will stop transmission for a while and enter a stand-by state. Keeping the DC balance during transmission is easy by applying any DC balanced coding scheme, but stopping and especially restarting the transmission may cause problems. If the signal is not put on its average value during these stand-by periods, the RDS will run away. Furthermore power will be drained if line terminations are used. However, using a signal value of zero requires a detection system to distinguish between a state with and without sufficient signal amplitude, which is sometimes called signal detect, squelch, or activity detect, below the valid signaling levels. In case of a binary signaling this enforces at least a 3-level detection. The additionally required detection means and the increased accuracy requirements can become a severe penalty for power consumption and may also reduce the achievable communication bandwidth.

SUMMARY OF THE INVENTION

Hence, it is a need, to provide a solution to overcome this dilemma.

It is therefore an object of the invention to provide a transmission system adapted to fulfill a signaling scheme comprising a start up signaling method, the start-up signaling method comprising a step of restoring DC balance upfront by inserting a Balance Equalization Sequence.

A start-up sequence starts with a transition, followed by a DC Balance Equalization Sequence (BES), and optionally followed by a synchronization sequence. The synchronization sequence itself may contain two parts: one part with a high edge-density for bit synchronization purposes e.g. toggling sequence, and a unique identifiable sequence e.g. a comma code word to obtain word synchronization.

The length and/or content of the BES may be set based on different criteria, for example: - Restored DC balance at the end of the DC-balance equalization sequence;

Partial restored DC balance, as the settling residue helps in dithering the phase-info of the (edge-dense) sync part. This has a similar effect as sending data that contains shorter and longer subsequences;

Length of the stand-by time; - Losses in the interconnect;

Length of the interconnect; Type of interconnect; Because some of these conditions depend on the actual physical realization of interconnect, it is advantageous to set these parameters during configuration of the link or find out a suitable or even the optimum value by means of negotiation.

The invention is defined by the independent claims. Dependent claims define advantageous embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages will be apparent from the exemplary description of the accompanying drawings in which

Fig. 1 depicts a state of the art communication system; Fig. 2 depicts a signaling sequence according to the invention; and Fig. 3 depicts possible start-up sequences for different applications, according to the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The start-up sequence that starts with a transition, followed by a DC

Equalization Sequence (BES), and optionally followed by a synchronization sequence. The synchronization sequence itself may contain two parts: one part with a high edge-density for bit synchronization purposes e.g. toggling sequence, and a unique identifiable sequence e.g. a comma code word to obtain word synchronization. Fig. 2 depicts possible parts of the startup sequence. The length and/or content of the BES are set based on various criteria, such as: Restored DC balance at the end of the DC-balance equalization sequence; Partial restored DC balance, as the settling residue helps in dithering the phase-info of the (edge-dense) sync part. This has a similar effect as sending data that contains shorter and longer subsequences; Length of the stand-by time; Loss in the interconnect; Length of the interconnect; - Type of interconnect.

Further criteria that may enhance this invention are not excluded. Because some of these conditions depend on the actual physical realization of interconnect, it might be advantageous to set these parameters during configuration of the link or find out a suitable or even the optimum value by means of negotiation. While the number of variables becomes pretty large, it may be useful to define one or more pre-defined sequences, which provide sufficient equalization for all practical cases.

Fig. 3 depicts possible start-up sequences for different cases. In case of an electrical binary differential low-swing interface with disconnectable far-end line termination(s) the interconnect state during standby state can be DIF-O without far-end termination connected. The BES can then consist of a certain number of bit periods with DIF-I line state, while DIF-O to DIF-I transition can be detected in the receiver, and used to enable its termination if applicable. In order to avoid or compensate for drifting away during this initial DIF-I state, it can be advantageous to add after that one or more states, DIF-O, DIF-I, with subsequent opposite polarities. The states can become gradually shorter in order to converge stepwise to the targeted average value. This also allows for compensating dispersion of longer interconnect lines. Fig. 3 shows for example a BES with an additional "zero" part after the initial "one" state.

In case of optical interconnect the two line states typically correspond with 'somewhat more' or 'somewhat less' light intensity; the latter state may equal no light at all. The standby state can be very low power without light being transmitted. The initial light pulse, or light pulse sequence, can be defined such as to enhance settling of filter stages and control loops in receiver RX and/or transmitter TX to their nominal operating points as appearing during DC balanced data transmission.

It is remarked that the scope of protection of the invention is not restricted to the embodiments described herein. Neither is the scope of protection of the invention restricted by the reference numerals in the claims. The word "comprising" does not exclude other parts than those mentioned in the claims. The word "a(n)" preceding an element does not exclude a plurality of those elements. Means forming part of the invention may both be implemented in the form of dedicated hardware or in the form of a programmed purpose processor. The invention resides in each new feature or combination of features.

Claims

1. A transmission system adapted to fulfill a signaling scheme comprising a start up signaling method, the start-up signaling method comprising a step of restoring DC balance upfront by inserting a Balance Equalization Sequence.

2. A transmission system as claimed in claim 1, wherein the Balance

Equalization Sequence with different lengths and patterns are provided.

3. A transmission system as claimed in claim 1, wherein the Balance Equalization Sequence comprises data values having an opposite polarity compared to a Running Digital Sum.

4. A transmission system as claimed in any of the preceding claims, wherein an average value of the Balance Equalization Sequence has an opposite polarity compared to a Running Digital Sum at the start of it.

5. A transmission system as claimed in any of the preceding claims, wherein the Balance Equalization Sequence has a variable length.

6. A transmission system as claimed in any of the preceding claims, wherein the sequence exists of subsequent states with alternating polarity and each state being equally sized or shorter than the previous state with the same polarity during the BES

7. A transmission system as claimed in any of the preceding claims, wherein a sub-state of the Balance Equalization Sequence is expanded, determining an overcompensation, which is re-equalized by the remainder of the BES.

8. A transmission system as claimed in any preceding claims, wherein the Balance Equalization Sequence is adapted to single-ended or differential systems.

9. A transmission system as claimed in claim 1, wherein the Balance

Equalization Sequence is adapted to terminated or unterminated operation.