WO2009031573A1 - 情報処理装置、プロセッサの状態遷移方法、プロセッサの状態遷移の制御装置、プロセッサ - Google Patents

情報処理装置、プロセッサの状態遷移方法、プロセッサの状態遷移の制御装置、プロセッサ Download PDF

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Publication number
WO2009031573A1
WO2009031573A1 PCT/JP2008/065853 JP2008065853W WO2009031573A1 WO 2009031573 A1 WO2009031573 A1 WO 2009031573A1 JP 2008065853 W JP2008065853 W JP 2008065853W WO 2009031573 A1 WO2009031573 A1 WO 2009031573A1
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WO
WIPO (PCT)
Prior art keywords
processor
status transition
information processing
processing apparatus
processor status
Prior art date
Application number
PCT/JP2008/065853
Other languages
English (en)
French (fr)
Inventor
Hiroaki Inoue
Tsuyoshi Abe
Shigeyoshi Shima
Junji Sakai
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Publication of WO2009031573A1 publication Critical patent/WO2009031573A1/ja

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Hardware Redundancy (AREA)

Abstract

課題　複数のＣＰＵを有する情報処理装置において、全てのＣＰＵ上で実行環境を動作させることが可能で、かつ、異なる実行環境を確実に分離して分離させることを可能にする。 解決手段　複数のＣＰＵを有する情報処理装置であって、複数のプロセッサ（１０Ｐ１～１０Ｐｎ、３００）で、複数の異なる実行環境を動作させ、特定の実行環境を動作させる特定のプロセッサ（３００）の状態を、他の実行環境を動作させる状態に切り替えるＣＰＵ制御手段（１００）を含む。  
PCT/JP2008/065853 2007-09-07 2008-09-03 情報処理装置、プロセッサの状態遷移方法、プロセッサの状態遷移の制御装置、プロセッサ WO2009031573A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007232757 2007-09-07
JP2007-232757 2007-09-07

Publications (1)

Publication Number Publication Date
WO2009031573A1 true WO2009031573A1 (ja) 2009-03-12

Family

ID=40428887

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/065853 WO2009031573A1 (ja) 2007-09-07 2008-09-03 情報処理装置、プロセッサの状態遷移方法、プロセッサの状態遷移の制御装置、プロセッサ

Country Status (1)

Country Link
WO (1) WO2009031573A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102135900A (zh) * 2010-01-26 2011-07-27 株式会社Ntt都科摩 信息处理装置和信息处理方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003518287A (ja) * 1999-12-23 2003-06-03 ジェネラル・インスツルメント・コーポレイション デュアルモードプロセッサ
JP2005535953A (ja) * 2002-08-13 2005-11-24 ノキア コーポレイション セキュアモードまたは非セキュアモードでプログラムを実行するコンピュータアーキテクチャ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003518287A (ja) * 1999-12-23 2003-06-03 ジェネラル・インスツルメント・コーポレイション デュアルモードプロセッサ
JP2005535953A (ja) * 2002-08-13 2005-11-24 ノキア コーポレイション セキュアモードまたは非セキュアモードでプログラムを実行するコンピュータアーキテクチャ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102135900A (zh) * 2010-01-26 2011-07-27 株式会社Ntt都科摩 信息处理装置和信息处理方法

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