WO2009028782A1

WO2009028782A1 - Apparatus and method for symbol error correctable modulation and demodulation using frequency selective baseband

Info

Publication number: WO2009028782A1
Application number: PCT/KR2008/002398
Authority: WO
Inventors: In Gi Lim; Hyung Il Park; Sung Weon Kang; Tae Wook Kang; Jung Hwan Hwang; Kyung Soo Kim; Jung Bum Kim; Chang Hee Hyoung; Duck Gun Park; Sung Eun Kim; Jin Kyung Kim; Ki Hyuk Park; Hyuk Kim
Original assignee: Electronics And Telecommunications Research Institute
Priority date: 2007-08-30
Filing date: 2008-04-28
Publication date: 2009-03-05
Also published as: KR100942702B1; CN101842989A; EP2188897A4; US8488648B2; EP2188897A1; CN101842989B; KR20090022495A; JP2010538518A; US20110029825A1; JP5130367B2

Abstract

Provided are symbol-error-correctable modulation and demodulation methods and apparatuses using a frequency selective baseband.The symbol-error-correctable frequency modulation method using a frequency selective baseband, includes: generating a plurality of subgroups by dividing 2N (N is a real number) spread codes or orthogonal codes used for frequency spreading into 2M (M<N, M is a real number) spread codes or orthogonal codes; selecting (P+L) (P and L is a real number) subgroups selected among the generated subgroups; acquiring P spread codes by inputting M data bits to each of the selected P subgroups so as for one spread code to be selected among the 2M spread codes of each subgroup; generating L*M parity bits for symbol error correction by using P*M data bits inputted to the selected P subgroups; selecting one spread code among the 2M spread codes of the L subgroups by inputting the L*M parity bits to the L subgroups; and selecting the dominant values among the (P+L) spread codes acquired from the (P+L) subgroups to generate transmitting data including the dominant values. Accordingly, it is possible to increase a processing gain of the entire system, to increase a transmission data rate, and to implement more stable digital communication with low power consumption.

Description

APPARATUS AND METHOD FOR SYMBOL ERROR CORRECTABLE MODULATION AND DEMODULATION USING FREQUENCY SELECTIVE BASEBAND

Technical Field

[1] The present invention relates to symbol-error-correctable modulation and demodulation methods and apparatuses using a frequency selective baseband, and more particularly, to symbol-error-correctable modulation and demodulation methods and apparatuses using a frequency selective baseband, capable of increasing a transmission data rate and implementing more stable digital communication with low power consumption through adaptation of a symbol error correction process by using a limited frequency band where an amplitude of internal-human-body transmitting signal propagating through a human body as a waveguide is lager than that of an external- human-body radiating signal excluding a frequency band of DC to 5MHz where noise power near the human body is concentrated.

[2] The work related to the present invention was partly supported by the IT R&D program of MIC/IITA [2006-S-072-02, Controller SoC for Human Body Communications]. Background Art

[3] Human-body communication is a technique for transmitting signals between apparatus connected to a human body by using the human body having conductivity as a communication channel. In the human-body communication technique, a communication network to various portable apparatuses such as personal digital assistants (PDAs), portable personal computers, digital cameras, MP3 players, and mobile phones or a communication network to fixed-type apparatuses such as printers, TVs, and entrance systems can be implemented by a user simply contacting the apparatuses.

[4] An existing human-body communication methods, there have been proposed a method using a limited passband, a method using scrambling with user's unique ID, a method of using channel coding, a method using interleaving, a method using spreading, and the like.

[5] In the existing human-body communication method, a passband having a central frequency fc which is used for most communication systems needs to be used in order to use the limited frequency band. Therefore, a digital-to-analog converter, an analog- to-digital converter, a central frequency converter, and the like needs to be provided to analog transmission and reception stages. Accordingly, the existing human-body communication methods have a problem in terms of low power consumption. [6] In addition, recently, a human-body communication method using a time- domain/frequency-domain spreading scheme for increasing a processing gain has been proposed. However, due to a limited frequency band, the human-body communication method has a problem in terms of increase in transmission data rate and efficiency of stable data communication.

[7] On the other hand, in case of transmitting or receiving data, error detection is performed so as to check a data-transmission success ratio. In this case, parity bits are used for the error detection and correction.

[8] In current digital communication, various linear block codes for the error correction have been researched.

[9] In general, in the linear block codes including a Hamming code, (n-k) parity bits are added to k information bits, so that the linear block codes constitutes a code word having a total of n bits. Encoding of the linear block codes can be simply implemented by calculation of a (kxn)-dimensional generating matrix. In addition, in decoding of the linear block codes, (lx(n-k))-dimensional syndrome bits are calculated by using a ((n-k)xn)-dimensional parity check matrix and a receiving signal, error pattern bits are generated from the syndrome bits, and an XOR operation is performed on the error pattern bits and the receiving signal so as to correct the error included in the receiving signal.

[10] As an example of the linear block codes, in case of setting the number of parity bits to 4, (15, 11) Hamming code is available. In this case, the 4 parity bits are added to 11 information bits, so that a total of 15 bits are transmitted, and 1-bit error correction can be performed. In addition, in case of setting the number of parity bits to 3 (reduced parity bits), (12, 8) reduced Hamming code is available. In this case, 4 parity bits are added to 8 information bits, so that a total of 12 bits are transmitted, and 1-bit error correction can also be performed. Disclosure of Invention Technical Problem

[11] The present invention provides symbol-error-correctable modulation and demodulation methods and apparatuses using a frequency selective baseband in digital communication, particularly, in human-body communication, capable of implementing more stable human-body communication with low power consumption through adaptation of a symbol error correction process. Technical Solution

[12] According to an aspect of the present invention, there is provided a symbol- error-correctable frequency modulation method using a frequency selective baseband, comprising: generating a plurality of subgroups by dividing 2^N (N is a real number) spread codes or orthogonal codes used for frequency spreading into 2^M (M<N, M is a real number) spread codes or orthogonal codes; selecting (P+L) (P and L is a real number) subgroups among the generated subgroups; acquiring P spread codes by inputting M data bits to each of the selected P subgroups so as for one spread code to be selected among the 2^M spread codes of each subgroup; generating L*M parity bits for symbol error correction by using P*M data bits inputted to the selected P subgroups; selecting one spread code among the 2^M spread codes of the L subgroups by inputting the L*M parity bits to the L subgroups; and selecting the dominant values among the (P+L) spread codes acquired from the (P+L) subgroups to generate transmitting data including the dominant values.

[13] In the above aspect of the present invention, the symbol-error-correctable frequency modulation method may further comprise converting serial data provided from an upper layer to P*M-bit parallel data, wherein the M parallel data bits are inputted to the selected P subgroups.

[14] In addition, the symbol-error-correctable frequency modulation method may further comprise: converting serial data provided from an upper layer to (P*M+l)-bit parallel data; and generating transmitting data by performing an XOR operation on the dominant values selected from the (P+L) spread codes acquired from the (P+L) subgroups and one bit of the (P*M+1) bits.

[15] In addition, in the selecting of the dominant values among the (P+L) spread codes acquired from the (P+L) subgroups, an AND operation may be performed on groups of two spread codes among the acquired (P+L) spread codes, an OR operation may be performed on the resulting values of the AND operation, and only the most significant bit may be selected from the resulting values of the OR operation for the (P+L) spread codes.

[16] According to another aspect of the present invention, there is provided a symbol- error-correctable frequency demodulation method using a frequency selective baseband, comprising: generating a plurality of subgroups by dividing 2^N (N is a real number) spread codes used for frequency spreading into 2^M (M<N, M is a real number) spread codes; when modulated data are transmitted from a transmitting stage, acquiring frame synchronization and timing synchronization from the transmitting data; selecting (P+L) subgroups determined to be used for modulation of the transmitting data among the plurality of subgroups and synchronizing the spread codes of the selected subgroups with the frame synchronization and the timing synchronization; calculating correlation values between the spread codes of the (P+L) subgroups and the transmitting data and detecting one spread code determined to be selected for the modulation of the transmitting data from each of the (P+L) subgroups; generating an M-bit index value of the detected spread code of each of the (P+L) subgroups and generating L*M syndrome bits from the generated (P+L)*M index values by using a parity check matrix; generating M*P error pattern bits from the L*M syndrome bits and performing an XOR operation on the generated error pattern bits and the M*P index values generated from the P subgroups to correct symbol error; and converting the M*P index values of the symbol-error-corrected parallel data to serial data.

[17] In the above aspect of the present invention, the symbol-error-correctable frequency demodulation method may further comprise: acquiring 1-bit data according to the correlation values of the index values generated the individual P subgroups; and obtaining parallel data by adding the acquired 1-bit data and the symbol-error-corrected M*P-bit parallel data and converting the parallel data to the serial data.

[18] According to still another aspect of the present invention, there is provided a symbol- error-correctable frequency modulation apparatus using a frequency selective baseband, comprising: a plurality of sub-frequency selective spreaders each including one subgroup among a plurality of subgroups generated by dividing 2^N (N is a real number) spread codes used for frequency spreading into 2^M (M<N, M is a real number) spread codes, each of the sub-frequency selective spreaders selecting and outputting one spread code among the 2^M spread code of the corresponding subgroup when M data bits are input; a serial-to-parallel conversion unit converting serial data provided from an upper layer to P*M-bit parallel data, outputting the M data bits to each of the P sub-frequency selective spreaders selected among the plurality of sub-frequency selective spreaders; a parity bit generation unit acquiring P*M data bits outputted from the serial-to-parallel conversion unit to the P sub-frequency selective spreaders and generating L*M parity bits for symbol error correction from the acquired P*M data bits to the L*M parity bits to the L sub-frequency selective spreaders; and a dominant- value selection unit selecting dominant values from (P+L) spread codes outputted from the (P+L) sub-frequency selective spreaders.

[19] In the above aspect of the present invention, the serial-to-parallel conversion unit may convert the serial data provided the upper layer to (P*M+l)-bit parallel data, output M data bits to each of the selected p sub-frequency selective spreaders, and output one bit in separation from the P*M bits.

[20] In addition, the symbol-error-correctable frequency modulation apparatus may further comprise an XOR logic circuit performing an XOR operation on the dominant values selected by the dominant- value selection unit and the 1 bit separately outputted from the serial-to-parallel conversion unit so as to increase a transmission data rate.

[21] In addition, the dominant-value selection unit may perform an AND operation on groups of two spread codes among the selected (P+L) spread codes, perform an OR operation on the resulting values of the AND operations, and select only the most significant bit from the resulting values of the OR operation for the (P+L) spread codes. [22] According to further still another aspect of the present invention, there is provided a symbol-error-correctable frequency demodulation apparatus using a frequency selective baseband, comprising: an orthogonal code generator generating a plurality of subgroups by dividing 2^N (N is a real number) spread codes used for frequency spreading into 2^M (M<N, M is a real number) spread codes, acquiring frame synchronization and timing synchronization from transmitting data which is modulated data transmitted from a transmitting stage, selecting P+L subgroups determined to be used for modulation of the transmitting data among the plurality of subgroups, and synchronizing and outputting the spread codes of the P+L subgroups with the acquired frame synchronization and timing synchronization; a plurality of sub-frequency selective despreaders each receiving, in a case where the modulated transmitting data is received from the transmitting stage, 2^M spread codes from the orthogonal code generator, calculating correlation values between the provided spread codes and the transmitting data, detecting one spread code determined to be selected for the modulation of the transmitting data, and outputting an M-bit index value of the detectted spread code; a syndrome generation unit inputted with (P+L)*M index values from the(P+L) sub-frequency selective despreaders provided with the spread codes of each of the (P+L) subgroups from the orthogonal code generator and generating L*M syndrome bits from the input index values by using a parity check matrix; an error pattern generation unit which generating M*P error pattern bits from the L*M syndrome bits; an error bit correction unit performing an XOR operation on the M*P index values outputted from the P sub-frequency selective despreaders and the M*P error pattern bits generated by the error pattern generation unit to correct symbol error of the M*P index values; and a parallel-to-serial conversion unit converting the M*P index values of the symbol-error-corrected parallel data to serial data.

[23] In the above aspect of the present invention, the symbol-error-correctable frequency demodulation apparatus may further comprise a correlation value determination unit receiving the correlation values of the index values outputted from the (P+L) sub- frequency selective despreaders and outputing different 1-bit data according to the provided correlation values.

[24] In addition, in a case where 1-bit data outputted from the correlation value determination unit together with the P*M index values outputted from the error bit correction unit are inputted, the parallel-to-serial conversion unit may convert parallel data obtained by adding the P*M index values and the 1-bit data to the serial data.

Advantageous Effects

[25] According to symbol-error-correctable modulation and demodulation methods and apparatuses using a frequency selective baseband of the present invention, it is possible to increase a processing gain of an entire system and to increase a transmission data rate by using serial-to-parallel conversion, frequency selective baseband transmission, and the limited number of spread codes in a digital communication.

[26] In addition, according to symbol-error-correctable modulation and demodulation methods and apparatuses using a frequency selective baseband of the present invention, configurations of analog transmitting and receiving stages can be minimized by using a frequency selective baseband transmission scheme, and parity bits for symbol error correction instead of a portion of transmitting bits are added for configuration of symbols in serial-to-parallel conversion, so that it is possible to reduce power consumption of an entire digital communication system. Brief Description of the Drawings

[27] FIG. 1 is a graph illustrating a relationship among a frequency selective baseband for human-body communication, a frequency-varying internal-human-body transmitting signal power, and an external-human-body noise power.

[28] FIG. 2 is a view illustrating subgroups of 64 Walsh codes according to an embodiment of the present invention.

[29] FIG. 3 is a view illustrating a configuration of a symbol-error-correctable frequency selective modulation apparatus according to an embodiment of the present invention.

[30] FIG. 4 is a view illustrating a configuration of a symbol-error-correctable frequency selective modulation apparatus according to another embodiment of the present invention.

[31] FIG. 5 is a view illustrating a configuration of a sub-frequency selective spreader according to an embodiment of the present invention.

[32] FIG. 6 is a view illustrating a configuration of a symbol-error-correctable frequency selective demodulation apparatus according to an embodiment of the present invention.

[33] FIG. 7 is a view illustrating a configuration of a symbol-error-correctable frequency selective demodulation apparatus according to another embodiment of the present invention.

[34] FIG. 8 is a view illustrating a configuration of a human-body communication system using a symbol-error-correctable frequency selective baseband according to an embodiment of the present invention. Best Mode for Carrying Out the Invention

[35] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that the ordinarily skilled in the art can easily implement the embodiments. However, in the detailed description of operational principles of the embodiments of the present invention, detailed description of well- known construction and operations will be omitted for clarifying the present invention. [36] In addition, in the drawings, elements having similar functions and operations are denoted by the same reference numerals.

[37] The present invention can be adapted to a digital communication system, particularly, a human-body communication system. Hereinafter, for the convenience of description, the human-body communication system will be exemplified.

[38] FIG. 1 is a graph illustrating a relationship among a frequency selective baseband for human-body communication, a frequency-varying internal-human-body transmitting signal power, and an external-human-body noise power.

[39] The graph of FIG. 1 illustrates results of measurement of interference signals induced into a human body in various measurement positions.

[40] As shown in FIG. 1, in the human-body communication according to the embodiment of the present invention, a frequency selective baseband within a frequency band of 5MHz to 40MHz excluding a frequency band of DC to 5MHz where the largest noise power occurs and a frequency band of 40MHz or more where an external- human-body radiating signal power is larger than an internal-human-body transmitting signal power.

[41] In the present invention, a frequency selective baseband transmission scheme denotes a transmission scheme where an analog transceiver can obtain a desired frequency band and a processing gain during baseband transmission by only "the spread codes having the most dominant frequency characteristics in a user's desired frequency band" among all the spread codes used for obtaining a processing gain of data.

[42] FIG. 1 exemplifies a case of using the spread codes for frequency selection. As an example, 64 Walsh codes are used as the spread codes. The 64 Walsh codes obtained by dividing a frequency band of 0 to 32MHz by 64 are sequentially and uniformly distributed with most dominant frequencies. The first subgroup using a frequency band of DC to 5MHz having the largest noise power is excluded, and the remaining 3 subgroups using the other frequency bands are selected, so that the frequency selective baseband transmission using a desired frequency band can be performed.

[43] FIG. 2 is a view illustrating subgroups of the 64 Walsh codes according to the embodiment of the present invention.

[44] As shown in FIG. 2, the 64 Walsh codes are used for the spread codes according to the embodiment of the present invention. The 64 Walsh codes may be divided into 4 subgroups having 16 Walsh codes. As a result, subgroup 0, subgroup 1, subgroup 2, and subgroup 3 include 16 Walsh codes W₀ to Wi₅, 16 Walsh codes Wi₆ to W₃i, 16 Walsh codes W32 to W47, and 16 Walsh codes W₄₈ to W₆₃, respectively.

[45] On the other hand, the 64 Walsh codes W₀ to W₆₃ can be used to exactly divide a using frequency band into 64 frequency bands, so that most dominant frequencies fd of the Walsh codes can be sequentially mapped to the divided frequency bands. [46] As an example, in a case where a spreading frequency band for the entire Walsh codes is assumed to be 32MHz, an interval of a most dominant frequency fd for a Walsh code is 0.5MHz (=32MHz/64). Therefore, the Walsh codes W₁, W₄₈, and W₆₃ have the most dominant frequencies fd of IMHz, 24.5MHz, and 32MHz, respectively.

[47] In the embodiment of the present invention shown in FIG. 1, the subgroup 1 (Wi₆ to

W₃i), the subgroup 2 (W₃₂ to W₄₇), and the subgroup 3 (W₄₈ to W₆₃) excluding the subgroup 0 are selected., so that the Walsh codes having the most dominant frequencies fd in a frequency band of 8.5MHz to 32MHz among the entire frequency band of 0 to 32MHz are used.

[48] Now, modulation and demodulation methods and apparatuses using the Walsh codes and a symbol-error-correctable frequency selective baseband will be described in detail.

[49] In the modulation and demodulation methods and apparatuses using the frequency selective baseband according to the embodiment of the present invention, the 64 Walsh codes are used as the spread codes, and the human-body communication frequency band shown in FIG. 1 is used as the frequency band. In addition, the subgroup 1 (Wi₆ to W31), the subgroup 2 (W₃₂ to W₄₇), and the subgroup 3 (W₄₈ to W₆₃) excluding the subgroup 0 are selected among the 4 subgroups shown in FIG. 2, so that the 48 Walsh codes among the entire 64 Walsh codes are selectively used.

[50] In addition, the modulation and demodulation methods and apparatuses using the frequency selective baseband according to the embodiment of the present invention, (12,8) reduced Hamming codes are used as an example of a linear block code for symbol error correction.

[51] FIG. 3 is a view illustrating a configuration of a symbol-error-correctable frequency selective modulation apparatus according to an embodiment of the present invention.

[52] As shown in FIG. 3, the symbol-error-correctable frequency selective modulation apparatus 100 includes a serial-to-parallel conversion unit (hereinafter, referred to as 'S2P') 110, a plurality of sub-frequency selective spreaders 121 to 123, a parity bit generation unit 130, and a dominant-value selection unit 140.

[53] In the frequency selective modulation apparatus 100, the S2P 110 converts an inputted serial data to 8-bit parallel data and outputs groups of 4 bits of the converted parallel data to the sub-frequency selective spreader 1 (121) and the sub-frequency selective spreader 2 (122). In addition, the S2P 110 outputs the converted 8-bit parallel data b7 to b0 to the parity bit generation unit 130.

[54] As an example, when the S2P 110 is inputted with a bit sequence of to- be-transmitted data at a transmission rate of 8Mbps, the S2P 110 converts the bit sequence to 8-bit parallel data b7 to b0 and outputs the converted parallel data at a transmission rate of IMbps. [55] In the frequency selective modulation apparatus 100, the parity bit generation unit

130 generates 4 parity bits p3 to pO for error detection and correction from the inputted 8-bit parallel data.

[56] On the other hand, the frequency selective modulation apparatus 100 does not use the

Walsh codes (W₀ to Wi₅) for a frequency band having the large noise power.

[57] Therefore, the sub-frequency selective spreader 1 (121) is inputted with 4 bits b7 to b4 among outputs of the S2P 110 and selects one Walsh code among the Walsh codes Wi₆ to W_3I to output the bit DOi at a transmission rate of 64Mbps. The sub-frequency selective spreader 2 (122) is inputted with 4 bits b3 to b0 among the outputs of the S2P 110 and selects one Walsh code among the Walsh codes W₃₂ to W₄₇ to output the bit DO₂ at a transmission rate of 64Mbps. The sub-frequency selective spreader 3 (123) is inputted with 4 bits p3 to p0 from the parity bit generation unit 130 and selects one Walsh code among the Walsh codes W₄₈ to W₆₃ to output the bit DO₃ at a transmission rate of 64Mbps.

[58] The dominant-value selection unit 140 is inputted as A, B, and Ci (Carry-in) with the

3 bits DOi, DO₂, and DO₃ outputted from the sub-frequency selective spreaders 121 to 123, respectively, and calculates Co (Carry-out) as a final output of the corresponding frequency selective modulation apparatus 100 by using the following Equation 1.

[59] [Equation 1]

[60] Co = (A and B) or (B and Ci) or (Ci and A)

[61] In Equation 1, operators "or" and "and" denote an OR gate and an AND gate, respectively.

[62] Therefore, due to the aforementioned configuration and operations, the symbol- error-correctable frequency selective modulation apparatus 100 can increase the transmission data rate by using serial-to-parallel conversion, frequency selective baseband transmission scheme, and the limited number of spread codes and transmits the spread code groups having the parity bits added into a portion of spread code groups for frequency selective multiple transmission, so that a receiving stage can corrects errors in symbols by using the parity bits.

[63] In addition, in order to further increase the transmission data rate, in the symbol- error-correctable frequency selective modulation apparatus 100, the S2P 110 may be constructed with 9 bits (with 1 bit added) and a value obtained by performing an XOR operation on the output of the dominant- value selection unit 140 and the added 1 bit may be generated as a final output value of the frequency selective modulation apparatus 100.

[64] FIG. 4 is a view illustrating a configuration of a symbol-error-correctable frequency selective modulation apparatus 100 according to another embodiment of the present invention. [65] As shown in FIG. 4, the frequency selective modulation apparatus 100 according to another embodiment of the present invention may include an S2P 110, a plurality of sub-frequency selective spreaders 121 to 123, a parity bit generation unit 130, a dominant- value selection unit 140, and an XOR logic circuit 150.

[66] In the frequency selective modulation apparatus 100 having such a configuration, the

S2P 110 is inputted with a serial data bit sequence at a transmission rate of 9Mbps and converts the serial data bit sequence to 9-bit parallel data b8 to b0 to output the 9-bit parallel data at a transmission rate of IMbps.

[67] In addition, as shown in FIG. 3, in the frequency selective modulation apparatus 100, the subgroup 0 including the Walsh codes in a frequency band having the large noise power is not used, and the sub-frequency selective spreaders 1 (121) and 2 (122) are inputted with the bits b7 to b4 and b3 to b0 among the outputs of the S2P 110, respectively. The parity bit generation unit 130 of the frequency selective modulation apparatus is inputted with the bit b7 to b0 among the outputs of the S2P 110 and generates 4 parity bits p3 to p0 for the error detection and correction to output the 4 parity bits to the sub-frequency selective spreader 3 (123).

[68] Therefore, each of the sub-frequency selective spreaders 1 (121), 2 (122), and 3 (123) selects on Walsh code included in each of the subgroups 1, 2, and 3 to output the bits DOi, DO₂, and DO₃ at a transmission rate of 64Mbps, respectively.

[69] In the frequency selective modulation apparatus 100, the bits DOi, DO₂, and DO₃ are input as input values A, B, and Ci to the dominant- value selection unit 140, and the dominant- value selection unit 140 calculates the output value Co by using Equation 1 and inputs the output value Co to the XOR logic circuit 150.

[70] The XOR logic circuit 150 performs an XOR operation on the output value Co of the dominant- value selection unit 140 and the output b8 of the S2P 110 to generate the resulting value of the XOR operation as a final output value of the frequency selective modulation apparatus 100.

[71] Now, the sub-frequency selective spreaders included in the frequency selective modulation apparatus 100 will be described in brief.

[72] FIG. 5 is a view illustrating a configuration of a sub-frequency selective spreader 120 according to an embodiment of the present invention.

[73] Referring to FIG. 5, the sub-frequency selective spreader 120 includes a 6-bit counter

1200 which is driven with a 64MHz clock, 5 XOR logic circuits 1201 to 1205 for gray indexing using 2-bit frequency selection control bits fs 1 and fsO, the least significant 4 data input bits b3, b2, bl, and bθ, 6 AND logic circuits 1206 to 1211, and an XOR logic circuit 1213 for performing an XOR operation on the outputs of the AND logic circuits.

[74] The two frequency selection control bits fsl and fsO are set to be different among the subgroups. For example, the two frequency selection control bits fsl and fsO of the sub-frequency selective spreader 1 (121) for the subgroup 1 (Wi₆ to W₃O are set to 0 and 1, respectively. The two frequency selection control bits fsl and fsO of the sub- frequency selective spreader 2 (122) for the subgroup 2 (W₃₂ to W₄₇) are set to 1 and 0, respectively. The two frequency selection control bits fs 1 and fsO of the sub-frequency selective spreader 3 (123) for the subgroup 3 (W₄₈ to W₆₃) are set to 1 and 1, respectively.

[75] The 6 AND logic circuits 1206 to 1211 are inputted with outputs C₅ to C₀ of the 6-bit counter 1200, the most significant bit fsl among the frequency selection control bits, and output bits of the 5 XOR logic circuits 1201 to 1205 and performs AND operations thereon to output the resulting value of the AND operation thereof, respectively.

[76] Finally, the sub-frequency selective spreader 120 generates an output DO_n by using the following Equation 2 and output the output DO_n.

[77] [Equation 2]

[78] DO_n = (fsl and C₀) xor [(fsl xor fsO) and Ci] xor [(fsO xor b3) and C₂] xor [(b3 xor b2) and C₃] xor[(b2 xor bl) and C₄] xor [(bl xor bθ) and C₅]

[79] FIG. 6 is a view illustrating a configuration of a symbol-error-correctable frequency selective demodulation apparatus 200 according to an embodiment of the present invention.

[80] Referring to FIG. 6, the symbol-error-correctable frequency selective demodulation apparatus 200 may include a orthogonal code generation unit 210, 3 sub-frequency selective despreaders 221 to 223, a syndrome generation unit 240, an error pattern generation unit 250, an error bit correction unit 260, a parallel-to-serial conversion unit (hereinafter, referred to as 'P2S') 270.

[81] In FIG. 6, a receiving signal of the frequency selective demodulation apparatus 200 is assumed to be a receiving signal of which frame synchronization and timing synchronization are acquired by a receiving- signal synchronization unit (not shown) disposed at a front stage thereof.

[82] The orthogonal code generation unit 210 generates 48 Walsh codes synchronized with the acquired frame synchronization and timing synchronization and outputs the 48 Walsh codes to the sub-frequency selective despreaders 221 to 223. Particularly, the orthogonal code generation unit 210 can output the Walsh codes Wi₆ to W₃₁ of the subgroup 1, the Walsh codes W₃₂ to W₄₇ of the subgroup 2, and the Walsh codes W₄₈ to W₆₃ of the subgroup 3 to the sub-frequency selective despreaders 1 (221), 2 (222), and 3 (223), respectively.

[83] Each of the sub-frequency selective despreaders 221 to 223 is inputted with the synchronized receiving signal at a transmission rate of 64Mbps and calculates a correlation value between the receiving signal and the Walsh codes provided from the or- thogonal code generation unit 210. Each of the sub-frequency selective despreaders 221 to 223 detects Walsh codes used for modulation by using the correlation value and outputs a 4-bit index value of the detected Walsh code at a transmission rate of IMbps.

[84] Now, the sub-frequency selective despreaders 221 to 223 will be described in detail.

Firstly, the sub-frequency selective despreader 1 (221) calculates the correlation value between the receiving signal and the 16 Walsh codes Wi₆ to W₃₁ provided from the orthogonal code generation unit 210. The sub-frequency selective despreader 1 (221) detects the Walsh code (one of the Walsh codes Wi₆ to W₃₁) used for modulation by using the correlation value and outputs a 4-bit parallel index value b7 to b4 at a transmission rate of IMbps.

[85] The sub-frequency selective despreader 2 (222) calculates the correlation value between the receiving signal and the 16 Walsh codes W₃₂ to W₄₇ provided from the orthogonal code generation unit 210. The sub-frequency selective despreader 2 (222) detects the Walsh code (one of the Walsh codes W₃₂ to W₄₇) used for modulation by using the correlation value and outputs a 4-bit parallel index value b3 to bθ. The sub- frequency selective despreader 3 (223) calculates the correlation value between the receiving signal and the 16 Walsh codes W₄₈ to W₆₃ provided from the orthogonal code generation unit 210. The sub-frequency selective despreader 3 (223) detects the Walsh code (one of the Walsh codes W₄₈ to W₆₃) used for modulation by using the correlation value and outputs a 4-bit parallel index value p3 to pθ.

[86] The syndrome generation unit 240 generates 4 syndrome bits s3 to s0 through a parity check matrix by using the index values outputted from the sub-frequency selective despreaders 221 to 223, that is, the 12 bits d7 to d0 and p3 to pθ.

[87] The error pattern generation unit 250 generates 8 error pattern bits e7 to e0 by using the 4 syndrome bits generated by the syndrome generation unit 240. Herein, the 8 error pattern bits are used to be indicated as 1 in an error bit included in the current symbol.

[88] The error bit correction unit 260 performs an XOR operation on the 8 bits d7 to d0 outputted from the sub-frequency selective despreaders 1 (221) and 2(222) and the 8 error pattern bits e7 to e0 outputted from the error pattern generation unit 250 to correct error included in the data symbol transmitted from the frequency selective modulation apparatus 100. As a result, the error bit correction unit 260 outputs symbol- error-corrected 8 bits u7 to uθ.

[89] The P2S 270 converts the 8 bits u7 to u0 outputted from the error bit correction unit

260 to a 1-bit output having a transmission rate of 8Mbps of the frequency selective demodulation apparatus 200.

[90] In addition, the frequency selective demodulation apparatus 200 may perform a demodulation function corresponding to the frequency selective modulation apparatus 100 of FIG. 4 in order to further increase the transmission data rate. [91] FIG. 7 is a view illustrating a configuration of a symbol-error-correctable frequency selective demodulation apparatus 200 according to another embodiment of the present invention.

[92] Referring to FIG. 7, the symbol-error-correctable frequency selective demodulation apparatus 200 according to another embodiment of the present invention may include a orthogonal code generation unit 210, 3 sub-frequency selective despreaders 221 to 223, a correlation value determination unit 230, a syndrome generation unit 240, an error pattern generation unit 250, an error bit correction unit 260, and a P2S 270.

[93] Similarly to FIG. 6, in FIG. 7, a receiving signal of the frequency selective demodulation apparatus 200 is assumed to be a receiving signal of which frame synchronization and timing synchronization are acquired by the receiving- signal synchronization unit disposed at a front stage thereof.

[94] The orthogonal code generation unit 210 generates 48 Walsh codes synchronized according to the acquired frame synchronization and timing synchronization and outputs the Walsh codes Wi₆ to W₃₁ of the subgroup 1, the Walsh codes W₃₂ to W₄₇ of the subgroup 2, and the Walsh codes W₄₈ to W₆₃ of the subgroup 3 to the sub- frequency selective despreaders 1 (221), 2 (222), and 3 (223), respectively.

[95] Each of the sub-frequency selective despreaders 221 to 223 is inputted with the synchronized receiving signal at a transmission rate of 64Mbps and calculates a correlation value between the receiving signal and the Walsh codes provided from the orthogonal code generation unit 210. Each of the sub-frequency selective despreaders 221 to 223 detects Walsh codes used for modulation by using the correlation value and outputs a 4-bit index value of the detected Walsh code at a transmission rate of IMbps.

[96] The sub-frequency selective despreaders 1 (221), 2 (222), and 3 (223) calculate the corresponding correlation value between the receiving signal and the Walsh codes of the subgroups 1, 2, and 3, respectively. The sub-frequency selective despreaders 1 (221), 2 (222), and 3 (223) detect the corresponding Walsh codes used for modulation by using the corresponding correlation values and output 4-bit parallel index values d7 to d4, d3 to dθ, and p3 to p0 at a transmission rate of IMbps, respectively.

[97] The sub-frequency selective despreaders 221 to 223 finally select the index values and provide correlation values of the finally-selected index values to the correlation value determination unit 230.

[98] The correlation value determination unit 230 outputs to the P2S 270 the bit u8 at a transmission rate of IMbps according to the correlation values provided from the sub- frequency selective despreaders 221 to 223.

[99] For example, in a case where there is no noise-originated error in a transmission channel, if the bit u8 is 0 in a transmitting stage, that is, the frequency selective modulation apparatus 100 according to another embodiment of the present invention, all the correlation values of the finally-selected index values of the sub-frequency selective despreaders 221 to 223 may be 16, and remaining index values may be 32. If the bit U8 is 1 at the transmitting stage, all the correlation values of the finally-selected index values of the sub-frequency selective despreaders 221 to 223 may be 48, and remaining index values may be 32.

[100] Therefore, if the sub-frequency selective despreaders 221 to 223 provide the correlation values of 16, the correlation value determination unit 230 outputs the bit u8 of 0 to the P2S 270. If the sub-frequency selective despreaders 221 to 223 provide the correlation values of 48, the correlation value determination unit 230 outputs the bit u8 of 1 to the P2S 270.

[101] The syndrome generation unit 240 generates 4 syndrome bits s3 to s0 through a parity check matrix by using the index values outputted from the sub-frequency selective despreaders 221 to 223, that is, the 12 bits d7 to d0 and p3 to pθ. The error pattern generation unit 250 generates 8 error pattern bits e7 to e0 by using the 4 syndrome bits generated by the syndrome generation unit 240. Herein, the 8 error pattern bits are used to be indicated as 1 in an error bit included in the current symbol.

[102] The error bit correction unit 260 performs an XOR operation on the 8 bits d7 to d0 outputted from the sub-frequency selective despreaders 1 (221) and 2(222) and the 8 error pattern bits e7 to e0 outputted from the error pattern generation unit 250 to correct error included in the data symbol transmitted from the frequency selective modulation apparatus 100. As a result, the error bit correction unit 260 outputs symbol- error-corrected 8 bits u7 to uθ.

[103] The P2S 270 converts the 8 bits u7 to u0 outputted from the error bit correction unit 260 and the 1 bit u8 outputted from the correlation value determination unit 230 to a 1-bit output having a transmission rate of 9Mbps of the frequency selective demodulation apparatus 200.

[104] Now, a human-body communication system, that is, a digital communication system employing the symbol-error-correctable frequency selective modulation and demodulation apparatuses using a frequency selective baseband will be described in detail.

[105] FIG. 8 is a view illustrating a configuration of a symbol-error-correctable human- body communication system using a frequency selective baseband according to an embodiment of the present invention.

[106] Referring to FIG. 8, the human-body communication system may include a MAC processing unit 10, a physical layer modem unit 20, an analog processing unit 30, a signal electrode 40, and a ground electrode 50.

[107] In the human-body communication system, the human-body communication MAC processing unit 10 includes a MAC transmitting processor 11 and a MAC receiving processor 12. The human-body communication MAC processing unit 10 transfers to- be-transmitted data and data information (transmission rate, modulation scheme, user ID, data length, etc) received from an upper layer to a transmitting unit of a physical layer modem unit 20. In addition, the human-body communication MAC processing unit 10 transfers data and data information received from the physical layer modem unit 20 to the upper layer.

[108] The physical layer modem unit 20 includes the transmitting unit 21 and a receiving unit 22. The transmitting unit 21 mainly includes a preamble/ header transmitting processing unit (2110, 2111, 2112, 2113), a data transmitting processing unit (2114, 2115, 100), and a multiplexer 2116.

[109] The preamble/ header transmitting processing unit (2110, 2111, 2112, 2113) has functions of spreading a frame-synchronization preamble and header information. The preamble/ header transmitting processing unit (2110, 2111, 2112, 2113) includes a preamble generator 2110, a header generator 2111, an HCS generator 2112, and spreader 2113. The data transmitting processing unit (2114, 2115, 100) has functions of spreading data (that is to be transmitted through human-body communication) into spread codes having the best frequency characteristics in a user's desired frequency band, that is, the frequency selective spread codes. The data transmitting processing unit (2114, 2115, 100) includes a data generator 2114, a scrambler 2115, and a symbol- error-correctable frequency selective modulator 100.

[110] In particular, the symbol-error-correctable frequency selective modulator 100 of the data transmitting processing unit (2114, 2115, 100) modulates 8Mbps or 9Mbps serial data (scrambled by the data generator 2114 and the scrambler 2115) to transmitting data using the serial-to-parallel conversion, the frequency selective baseband transmission scheme, and the limited number of spread codes according to the configuration and operations shown in FIG. 3 or 4 of the aforementioned embodiments. Herein, the symbol-error-correctable frequency selective modulator 100 may perform modulation of the transmitting data so as to add 4 parity bits for error detection and correction into a portion of a spread code group.

[I l l] The multiplexer 2116 multiplexes the preamble and the header generated through the spreading of the preamble/ header transmitting processing unit (2110, 2111, 2112, 2113) and the frequency-selective-modulated data outputted from the data transmitting processing unit (2114, 2115, 100) to transmit a digital signal.

[112] Accordingly, the digital signal transmitted from the multiplexer 2116 of the transmitting unit 21 can be adapted to the baseband transmission of the frequency selective modulator 100, so that the digital signal can be transmitted through a transmitting/receiving switch 31 and the signal electrode 40 into a human body without separate configurations for analog transmitting processes. The ground electrode 50 is disposed to provide a reference voltage.

[113] The analog processing unit 30 is divided to a portion for transmitting the digital signal of the transmitting unit into the human body, that is, the transmitting/receiving switch 31 and the signal electrode 40 and a portion for receiving the digital signal from the human body and transferring the receiving unit 22 of the physical layer modem unit, that is, the signal electrode 40, the transmitting/receiving switch 31, a noise filter 32, an amplifier 33, and a clock recovering/data retiming unit (CDR) 34.

[114] In the analog processing unit 30 having the aforementioned configuration, noise of the receiving signal (inputted through the signal electrode 40) that is originated from the internal-human-body transmission is removed through the transmitting/receiving switch 31 and the noise filter 32, the receiving signal is amplified to have a desired signal amplitude by the amplifier 33, and timing synchronization and frequency offset of the receiving signal are compensated based on a clock of a receiving stage by the clock recovering/data retiming unit 34.

[115] The receiving signal of which timing synchronization and frequency offset are compensated is output to the receiving unit 22 of the physical layer modem unit 20.

[116] The receiving unit 22 of the physical layer modem unit 20 mainly includes a demultiplexer 2210, a header receiving processing unit (2211, 2212, 2213), and a data receiving processing unit (200, 2214, 2215). The receiving unit 22 further includes a frame synchronization unit 2216 and common control signal generation unit 2217 to acquire frame synchronization of the receiving signal and generate common control signals used for the transmitting unit and the receiving unit 22 of the physical layer modem unit.

[117] In the physical layer modem unit 20, the demultiplexer 2210 has functions of extracting a preamble, headers, and data from the digital signal transmitted through the human-body channel. The header receiving processing unit (2211, 2212, 2213) has functions of despreading the extracted header to recover original data information. The header receiving processing unit (2211, 2212, 2213) includes a despreader 2211, an HCS tester 2212, and a header processor 2213.

[118] The data receiving processing unit (200, 2214, 2215) has functions of despreading the extracted date into spread codes having the best frequency characteristics in a user's desired frequency band. The data receiving processing unit (200, 2214, 2215) includes a symbol-error-correctable frequency selective demodulator 200, a descrambler 2214, and a data processor 2215.

[119] In particular, when data are input through the demultiplexer 2210, the frequency selective demodulator 200 of the data receiving processing unit (200, 2214, 2215) acquires correlation values using a frequency selective baseband and spread codes used for transmission, corrects errors included in the input data symbol by using the finally- selected index values, and demodulates the error-corrected data into 8Mbps or 9Mbps serial data according to the configurations and operations shown in FIG. 6 or 7 of the aforementioned embodiment.

[120] As described above, a human-body communication system according to the embodiment of the present invention is provided with a frequency selective modulator and a frequency selective demodulator to efficiently combine serial-to-parallel conversion of data, a frequency selective baseband, and the limited number of spread codes, so that it is possible to increase a processing gain of the entire system and to increase a data transmission rate. In addition, in a transmitting stage, parity bits for symbol error correction are added into a portion of a spread code group, and in a receiving stage, errors included in the symbol is corrected by using the parity bits, so that it is possible to implement more stable human-body communication even in a poor human-body communication channel environment.

[121] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.

[122] Particularly, the present invention is described through embodiments using spread codes for frequency selection, but not limited thereto. As alternative embodiments, orthogonal codes may be used for the frequency selection.

Claims

[1] A symbol-error-correctable frequency modulation method using a frequency selective baseband, comprising: generating a plurality of subgroups by dividing 2^N (N is a real number) spread codes or orthogonal codes used for frequency spreading into 2^M (M<N, M is a real number) spread codes or orthogonal codes; selecting (P+L) (P and L is a real number) subgroups selected among the generated subgroups; acquiring P spread codes by inputting M data bits to each of the selected P subgroups so as for one spread code to be selected among the 2^M spread codes of each subgroup; generating L*M parity bits for symbol error correction by using P*M data bits input to the selected P subgroups; selecting one spread code among the 2^M spread codes of the L subgroups by inputting the L*M parity bits to the L subgroups; and selecting the dominant values among the (P+L) spread codes acquired from the (P+L) subgroups to generate transmitting data including the dominant values.

[2] The symbol-error-correctable frequency modulation method of claim 1, further comprising converting serial data provided from an upper layer to P*M-bit parallel data, wherein the M parallel data bits are inputted to the selected P subgroups.

[3] The symbol-error-correctable frequency modulation method of claim 1, further comprising: converting serial data provided from an upper layer to (P*M+l)-bit parallel data; and generating transmitting data by performing an XOR operation on the dominant values selected from the (P+L) spread codes acquired from the (P+L) subgroups and one bit of the (P*M+1) bits.

[4] The symbol-error-correctable frequency modulation method of claim 1, wherein in the selecting of the dominant values among the (P+L) spread codes acquired from the (P+L) subgroups, an AND operation is performed on groups of two spread codes among the acquired (P+L) spread codes, an OR operation is performed on the resulting values of the AND operation, and only the most significant bit is selected from the resulting values of the OR operation for the (P+L) spread codes.

[5] A symbol-error-correctable frequency demodulation method using a frequency selective baseband, comprising: generating a plurality of subgroups by dividing 2^N (N is a real number) spread codes used for frequency spreading into 2^M (M<N, M is a real number) spread codes; when modulated data are transmitted from a transmitting stage, acquiring frame synchronization and timing synchronization from the transmitting data; selecting (P+L) subgroups determined to be used for modulation of the transmitting data among the plurality of subgroups and synchronizing the spread codes of the selected subgroups with the frame synchronization and the timing synchronization ; calculating correlation values between the spread codes of the (P+L) subgroups and the transmitting data and detecting one spread code determined to be selected for the modulation of the transmitting data from each of the (P+L) subgroups; generating an M-bit index value of the detected spread code of each of the (P+L) subgroups and generating L*M syndrome bits from the generated (P+L)*M index values by using a parity check matrix; generating M*P error pattern bits from the L*M syndrome bits and performing an XOR operation on the generated error pattern bits and the M*P index values generated from the P subgroups to correct symbol error; and converting the M*P index values of the symbol-error-corrected parallel data to serial data.

[6] The symbol-error-correctable frequency demodulation method of claim 5, further comprising: acquiring 1-bit data according to the correlation values of the index values generated the individual P subgroups; and obtaining parallel data by adding the acquired 1-bit data and the symbol- error-corrected M*P-bit parallel data and converting the parallel data to the serial data.

[7] A symbol-error-correctable frequency modulation apparatus using a frequency selective baseband, comprising: a plurality of sub-frequency selective spreaders each including one subgroup among a plurality of subgroups generated by dividing 2^N (N is a real number) spread codes used for frequency spreading into 2^M (M<N, M is a real number) spread codes, each of the sub-frequency selective spreaders selecting and outputting one spread code among the 2^M spread code of the corresponding subgroup when M data bits are inputted; a serial-to-parallel conversion unit converting serial data provided from an upper layer to P*M-bit parallel data, outputting the M data bits to each of the P sub- frequency selective spreaders selected among the plurality of sub-frequency selective spreaders; and a parity bit generation unit acquiring P*M data bits outputted from the serial- to-parallel conversion unit to the P sub-frequency selective spreaders and generating L*M parity bits for symbol error correction from the acquired P*M data bits to the L*M parity bits to the L sub-frequency selective spreaders; and a dominant-value selection unit selecting dominant values from (P+L) spread codes outputted from the (P+L) sub-frequency selective spreaders.

[8] The symbol-error-correctable frequency modulation apparatus of claim 7, wherein the serial-to-parallel conversion unit converts the serial data provided the upper layer to (P*M+l)-bit parallel data, outputs M data bits to each of the selected p sub-frequency selective spreaders, and outputs one bit in separation from the P*M bits.

[9] The symbol-error-correctable frequency modulation apparatus of claim 8, further comprising an XOR logic circuit performing an XOR operation on the dominant values selected by the dominant- value selection unit and the 1 bit separately outputted from the serial-to-parallel conversion unit so as to increase a transmission data rate.

[10] The symbol-error-correctable frequency modulation apparatus of claim 7, wherein the dominant- value selection unit performs an AND operation on groups of two spread codes among the selected (P+L) spread codes, performs an OR operation on the resulting values of the AND operations, and selects only the most significant bit from the resulting values of the OR operation for the (P+L) spread codes.

[11] A symbol-error-correctable frequency demodulation apparatus using a frequency selective baseband, comprising: a orthogonal code generator generating a plurality of subgroups by dividing 2^N (N is a real number) spread codes used for frequency spreading into 2^M (M<N, M is a real number) spread codes, acquiring frame synchronization and timing synchronization from transmitting data which is modulated data transmitted from a transmitting stage, selecting P+L subgroups determined to be used for modulation of the transmitting data among the plurality of subgroups, and synchronizing and outputting the spread codes of the P+L subgroups with the acquired frame synchronization and timing synchronization; a plurality of sub-frequency selective despreaders each receiving, in a case where the modulated transmitting data is received from the transmitting stage, 2^M spread codes from the orthogonal code generator, calculating correlation values between the provided spread codes and the transmitting data, detecting one spread code determined to be selected for the modulation of the transmitting data, and outputting an M-bit index value of the detected spread code; a syndrome generation unit inputted with (P+L)*M index values from the(P+L) sub-frequency selective despreaders provided with the spread codes of each of the (P+L) subgroups from the orthogonal code generator and generating L*M syndrome bits from the input index values by using a parity check matrix; an error pattern generation unit generating M*P error pattern bits from the L*M syndrome bits; an error bit correction unit performing an XOR operation on the M*P index values outputted from the P sub-frequency selective despreaders and the M*P error pattern bits generated by the error pattern generation unit to correct symbol error of the M*P index values; and a parallel-to-serial conversion unit converting the M*P index values of the symbol-error-corrected parallel data to serial data.

[12] The symbol-error-correctable frequency demodulation apparatus of claim 11, further comprising a correlation value determination unit receiving with the correlation values of the index values outputted from the (P+L) sub-frequency selective despreaders and outputting different 1-bit data according to the provided correlation values.

[13] The symbol-error-correctable frequency demodulation apparatus of claim 12, wherein, in a case where 1-bit data outputted from the correlation value determination unit together with the P*M index values outputted from the error bit correction unit are inputted, the parallel-to-serial conversion unit converts parallel data obtained by adding the P*M index values and the 1-bit data to the serial data.