KR100291076B1 - Quadrature Walsh Modulator with High Speed Detection - Google Patents

Abstract

TECHNICAL FIELD The present invention relates to the field of mobile communications, and more particularly, to a bi-orthogonal walsh modulator capable of high-speed detection, and to providing a quadrature Walsh modulator capable of reducing the calculation amount of a receiver without degrading a system. Its purpose is to. For example, in the 64-bit CDMA cellular system (IS-95) currently commercially available, the Walsh-Hadamard converter takes each correlation value for the 64 bits received, so that the highest correlation coefficient value among the 64 Walsh indexes is obtained. It is for extracting a 6-bit pattern from where it is detected. Thus, the complexity of the receiver hardware is determined by the calculation of the Walsh-Hadamard converter, which is proportional to the length of the Walsh sequence. To achieve the same performance while reducing the complexity of the receiver, it is necessary to reduce the computation of the Walsh-Hadamard converter while transmitting 6 bits, as in the IS-95. Bi-orthogonal Walsh sequences have 64 types of sequence like 64 binary orthogonal Walsh modulators, and the sequence length is 32 bits, which allows 6 bits to be transmitted in the same way as IS-95. By using a reduced sequence, the computation of the Walsh-Hadamard converter can be reduced by more than half. The present invention can be applied not only to the 64-ary quadrature Walsh modulator, but also to extending it to a 2M-ary quadrature Walsh modulator.

Description

Quadrature Walsh Modulator with High Speed Detection

TECHNICAL FIELD The present invention relates to the field of mobile communications, and more particularly to a bi-orthogonal Walsh modulator capable of high speed detection.

Code divisional multiple access (CDMA) digital cellular systems (IS-95), which are currently commercially available, perform modulation asynchronously, resulting in performance degradation compared to synchronous forward links. In order to compensate for this, a method of modulating and transmitting a 64-bit orthogonal Walsh modulator has been used. A 64-bit orthogonal Walsh modulator transmits a 6-bit convolutional coded bit to a 64-bit Walsh sequence according to a bit pattern. We tried to guarantee the orthogonality between 6 bits by modulating with. That is, the 64-bit orthogonal Walsh modulator attempts to compensate for the loss due to the link in a manner that guarantees orthogonality between convolutional coded 6-bit sequences.

1 is a block diagram of a general 64-bit quadrature Walsh modulator. The most significant bit b5 of convolutional coded bit sequences [b0, b1, b2, b3, b4, b5] is multiplied by a clock (01010101...) The Walsh sequence is divided into two and the lower bits are sequentially multiplied by a modulo-2 adder to add a Walsh sequence with a sequence length of 64 in a 6-bit pattern. W ₆₄ ).

On the other hand, the base station receiver detects a correlation coefficient for every 64 bit sequences using a Walsh-Hadamard Transform (WHT) technique to detect an orthogonal Walsh code sequence modulated and transmitted by a mobile station. It demodulates the 6-bit sequence transmitted by the mobile station through the Walsh code index in which the coefficient value is located. To implement this, the receiver must have a Walsh-Hadamard converter, which increases the complexity of the receiver hardware. That is, since the 6-bit sequence is mapped to the 64-bit orthogonal Walsh sequence and modulated, the structure of the orthogonal Walsh modulator must be more complicated to increase the information bit sequence to be mapped.

In the reverse link receiver of the IS-95 system, the Walsh-Hadamard converter performs the calculation in six stages. In the first stage, the correlation coefficient between the upper 32 bits and the lower 32 bits of the received 64 bit sequence is calculated. In the next step, 16 bits of each of the 16-bit groups are obtained by classifying each of 16 bits among the 64 correlation coefficients calculated. The next step is 8 bits, 4 bits, 2 bits, and 1 Classify bit by bit and calculate correlation coefficient by 8 bit, 4 bit, 2 bit, 1 bit within the group to find the location where the correlation coefficient value is maximum among 64 Walsh index and finally demodulate 6 bit bit pattern do.

Thus, the amount of Walsh-Hadamard calculation depends on the number of steps (or the number of iterations) of calculating the correlation coefficient values. In the case of the IS-95 system described above, in order to demodulate a 64-bit Walsh sequence into 6-bit coded bits, A total of 64 × 6 = 364 calculations are needed because 64 calculations are required for each iteration.

It is an object of the present invention to provide a quadrature Walsh modulator capable of reducing the amount of computation of a receiver without degrading the performance of the system.

It is also an object of the present invention to provide a 64-binary quadrature Walsh modulator capable of reducing the amount of computation of a receiver without degrading the performance of the system.

1 is a block diagram of a typical 64-bit quadrature Walsh modulator.

2 is a conceptual diagram of a 64 binary quadrature Walsh modulator of the present invention.

3 is a block diagram of a 64 binary quadrature Walsh modulator according to an embodiment of the present invention;

Figure 4 is a block diagram of a 64 binary quadrature Walsh demodulator in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: serial / parallel converter

21: 64 Binary Orthogonal Walsh Modulator

40: Walsh-Hadamard Converter

41: maximum value minimum value detector

42a, 42b: Binary Converter

For example, in the 64-bit CDMA cellular system (IS-95) currently commercially available, the Walsh-Hadamard converter takes each correlation value for the 64 bits received, so that the highest correlation coefficient value among the 64 Walsh indexes is obtained. It is for extracting a 6-bit pattern from where it is detected. Thus, the complexity of the receiver hardware is determined by the calculation of the Walsh-Hadamard converter, which is proportional to the length of the Walsh sequence. To achieve the same performance while reducing the complexity of the receiver, it is necessary to reduce the computation of the Walsh-Hadamard converter while transmitting 6 bits, as in the IS-95. Bi-orthogonal Walsh sequences have 64 types of sequence like 64 binary orthogonal Walsh modulators, and the sequence length is 32 bits, which allows 6 bits to be transmitted in the same way as IS-95. By using a reduced sequence, the computation of the Walsh-Hadamard converter can be reduced by more than half. The present invention can be applied not only to the 64-ary quadrature Walsh modulator, but also to extending it to a 2M-ary quadrature Walsh modulator.

In order to achieve the above technical problem, a characteristic quadrature Walsh modulator provided from the present invention modulates the remaining lower bits except the most significant bit of the convolutional coded bit sequence into a quadrature Walsh sequence, and converts the most significant data bit into the doublet Walsh modulator. And a parity bit for determining an inverted portion of the orthogonal Walsh sequence.

Further, in order to achieve the above technical problem, the characteristic 64-binary quadrature Walsh modulator provided from the present invention modulates the lower five bits of the convolutional coded bit sequence into a quadrature Walsh sequence having a sequence length of 32, and The most significant data bit of the sequence is used as a parity bit to determine the inverted portion of the orthogonal Walsh sequence.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2 is a conceptual diagram of a 64 binary quadrature Walsh modulator, in which a convolutionally coded bit sequence [b0, b1, b2, b3, b4, b5 is coded through a serial-to-parallel converter 20 having data bits as inputs; The lower five bits b0, b1, b2, b3, and b4 generate a Walsh-Hadamard sequence with a sequence length of 32 in a 5-bit pattern, similar to the conventional 64-bit quadrature Walsh modulator. Inverted part of an orthogonal Walsh sequence ) Is used as a parity bit to determine). Reference numeral 21 denotes a 64 binary quadrature Walsh modulator. In this case, the 64 binary quadrature Walsh-Hadamard matrix is a matrix of 64 × 32, as shown in Equation 1 below.

FIG. 3 is a block diagram illustrating a 64-bit quadrature Walsh modulator according to an embodiment of the present invention, wherein the lower five bits b0, b1, b5, b2, b3, b4, b5 of convolutional coded bits are illustrated. b2, b3, b4 are 5-bit patterns with a Walsh sequence of 32 sequence length W ₃₂ And if the most significant bit b5 is '0' according to the pattern of the bit, it is modulated according to the previous 5-bit pattern, and if '1' is determined by the previous 5-bit pattern W ₃₂ Is a reversed sequence Is modulated by That is, the most significant bit b4 among the lower five bits b0, b1, b2, b3, and b4 among the convolutional coded bits [b0, b1, b2, b3, b4, b5] is clocked like a conventional 64-bit quadrature Walsh modulator. Multiplying the clock by two, and then sequentially subtracting the clock bits by two and the lower bits thereof, summed together in a modulo-2 adder to form a Walsh sequence with a sequence length of 32. W ₃₂ ). And, the most significant bit of the convolutionally coded bits [b0, b1, b2, b3, b4, b5] is the orthogonal Walsh sequence. W ₃₂ Or its inversion sequence Used as a parity bit to determine. In this way, 6-bit encoded bits can be modulated and transmitted into a Walsh sequence having a length of 32.

4 is a block diagram of a 64 binary quadrature Walsh demodulator according to an embodiment of the present invention. After converting a received signal into a 32-bit sequence through the Walsh-Hadamard converter 40, The maximum value minimum detector 41 finds the maximum value among the correlation coefficients, and detects the 5-bit pattern [b0, b1, b2, b3, b4] according to the Walsh index of the position where the maximum correlation coefficient value (+32) has occurred and correlates it. When the coefficient value has the minimum value (−32), it means that the most significant transmission bit b5 is '1', so that the pattern of the bit b5 may be determined. At this time, the binary converter 42a receives the maximum correlation coefficient value and adds a '0' bit to the most significant bit b5 to output a demodulated signal in a 6-bit bit pattern, and the binary converter 42b inputs a minimum correlation coefficient value. Receiving the most significant bit b5 and adding a '1' bit to output a demodulated signal in a 6-bit bit pattern.

As described above, in the reverse link receiver of the IS-95 system, the Walsh-Hadamard converter requires a total of 364 calculations over a total of six stages, whereas in the case of the orthogonal Walsh modulator proposed by the present invention, the sequence length is 32 times. Since the orthogonal Walsh modulator is used, the number of iteration calculations in the receiver's Walsh-Hadamard converter will be five times, thus reducing the computation by more than half since the total computation is 32 × 5 = 160 times.

The 64 binary quadrature Walsh modulator described above is not more complicated than the structure of the 64 binary quadrature Walsh modulator of the currently commercialized IS-95 system, but it has the advantage of reducing the calculation amount of the demodulator by more than half, and also 2M Since it can be extended with a -ary quadrature Walsh modulator, it can be extended with a quadrature Walsh modulator that can be applied to various data rates in the future. Therefore, it can be extended to a quadrature Walsh modulator that can be applied to various data rates in the future. .

Unlike the orthogonal Walsh demodulator of IS-95, the orthogonal Walsh demodulator has to detect maximum and minimum values, so it can be applied only to the system using the synchronous demodulation method, but the third generation such as IMT-2000, which is being developed in the future Since most of the mobile communication systems adopt a synchronous demodulation method, the application is not a big limitation.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

For example, in the above-described embodiment, a 64-ary quadrature Walsh modulator has been described as an example for comparison with a current CDMA system, but the present invention may be applied to the case of extending it to a 2M-ary quadrature Walsh modulator. Can be.

The above-described present invention improves the structure of an orthogonal Walsh modulator used in the reverse link of a conventional CDMA system, thereby increasing the number of available information bits that can be transmitted at high speed, and thereby increasing the amount of transmitted information. When applied to a mobile communication system can have a great effect. In addition, the present invention has the effect of reducing the complexity of the receiver hardware of the CDMA mobile communication system and increase the detection speed.

Claims (2)

A low-order bit other than the most significant bit of the convolutional coded bit sequence, modulating the low-order bit into a quadrature Walsh sequence, and using the most-significant data bit as a parity bit for determining an inverted portion of the quadrature Walsh sequence. . Modulating the lower five bits of the convolutional coded bit sequence into a quadrature Walsh sequence having a sequence length of 32 and using the most significant data bit of the bit sequence as a parity bit for determining the inverted portion of the quadrature Walsh sequence. 64-bin orthogonal Walsh modulator.