WO2009026171A3 - Stacked die vertical interconnect formed by transfer of interconnect material - Google Patents

Stacked die vertical interconnect formed by transfer of interconnect material Download PDF

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Publication number
WO2009026171A3
WO2009026171A3 PCT/US2008/073365 US2008073365W WO2009026171A3 WO 2009026171 A3 WO2009026171 A3 WO 2009026171A3 US 2008073365 W US2008073365 W US 2008073365W WO 2009026171 A3 WO2009026171 A3 WO 2009026171A3
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WO
WIPO (PCT)
Prior art keywords
transfer
die
interconnect
carrier
edge
Prior art date
Application number
PCT/US2008/073365
Other languages
French (fr)
Other versions
WO2009026171A2 (en
Inventor
Terrence Caskey
Lawrence Douglas Andrews
Simon J S Mcelrea
Scott Mcgrath
Marc Robinson
Mark Scott
Yong Du
Roydn Jones
Thanh Van Tran
Original Assignee
Vertical Circuits Inc
Terrence Caskey
Lawrence Douglas Andrews
Simon J S Mcelrea
Scott Mcgrath
Marc Robinson
Mark Scott
Yong Du
Roydn Jones
Thanh Van Tran
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vertical Circuits Inc, Terrence Caskey, Lawrence Douglas Andrews, Simon J S Mcelrea, Scott Mcgrath, Marc Robinson, Mark Scott, Yong Du, Roydn Jones, Thanh Van Tran filed Critical Vertical Circuits Inc
Publication of WO2009026171A2 publication Critical patent/WO2009026171A2/en
Publication of WO2009026171A3 publication Critical patent/WO2009026171A3/en

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    • H—ELECTRICITY
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L2224/05599—Material
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    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Apparatus for making electrical interconnection of semiconductor die includes a transfer carrier having an electrically conductive material arranged in a pattern on a transfer surface. A transfer process for electrical interconnect includes steps of aligning the transfer apparatus with an edge of a die to be interconnected; and moving the transfer apparatus toward the die edge (or moving the die edge toward the transfer apparatus, or moving both the transfer carrier and the die edge in relation to one another) to bring the patterned conductive material on the transfer surface and interconnect terminals on the die into contact. In some embodiments the carrier is left in place in a functioning interconnected device; in other embodiments the transfer carrier and the die edge are separated to leave at least a portion of the conductive material in contact with the interconnect terminals.
PCT/US2008/073365 2007-08-17 2008-08-15 Stacked die vertical interconnect formed by transfer of interconnect material WO2009026171A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US96518407P 2007-08-17 2007-08-17
US60/965,184 2007-08-17

Publications (2)

Publication Number Publication Date
WO2009026171A2 WO2009026171A2 (en) 2009-02-26
WO2009026171A3 true WO2009026171A3 (en) 2009-05-07

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PCT/US2008/073365 WO2009026171A2 (en) 2007-08-17 2008-08-15 Stacked die vertical interconnect formed by transfer of interconnect material

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
US20050230802A1 (en) * 2004-04-13 2005-10-20 Al Vindasius Stacked die BGA or LGA component assembly
US7245021B2 (en) * 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
US20050230802A1 (en) * 2004-04-13 2005-10-20 Al Vindasius Stacked die BGA or LGA component assembly
US7245021B2 (en) * 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly

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