WO2009024886A3 - System and method for error protection of a memory - Google Patents

System and method for error protection of a memory Download PDF

Info

Publication number
WO2009024886A3
WO2009024886A3 PCT/IB2008/053185 IB2008053185W WO2009024886A3 WO 2009024886 A3 WO2009024886 A3 WO 2009024886A3 IB 2008053185 W IB2008053185 W IB 2008053185W WO 2009024886 A3 WO2009024886 A3 WO 2009024886A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
dma
controller
error protection
address information
Prior art date
Application number
PCT/IB2008/053185
Other languages
French (fr)
Other versions
WO2009024886A2 (en
Inventor
Manfred Zinke
Markus Baumeister
Wageningen Andries Van
Original Assignee
Nxp Bv
Manfred Zinke
Markus Baumeister
Wageningen Andries Van
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv, Manfred Zinke, Markus Baumeister, Wageningen Andries Van filed Critical Nxp Bv
Publication of WO2009024886A2 publication Critical patent/WO2009024886A2/en
Publication of WO2009024886A3 publication Critical patent/WO2009024886A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error

Abstract

The present invention proposes a system for error protection for a memory during accessing the memory. The system comprises a memory (200) and a DMA-controller (110). The memory (200) comprises a first portion (210) and a second portion (220), wherein the first portion (210) provides address information about the second portion (220) and the second portion (220) is to store data to be accessed. The DMA-controller (110) is adapted to access the second portion (220), or the first portion (210) of the memory (200) by using information stored in the first portion (210) of the memory (200). The DMA-controller (110) includes a checking unit (140) receiving address information from the first portion (210) and determining an address of the memory location in the second portion (220) or in the first portion (210). The checking unit (140) verifies the consistency of the determined address based on the address information.
PCT/IB2008/053185 2007-08-21 2008-08-08 System and method for error protection of a memory WO2009024886A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07114645 2007-08-21
EP07114645.0 2007-08-21

Publications (2)

Publication Number Publication Date
WO2009024886A2 WO2009024886A2 (en) 2009-02-26
WO2009024886A3 true WO2009024886A3 (en) 2009-04-30

Family

ID=40361728

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/053185 WO2009024886A2 (en) 2007-08-21 2008-08-08 System and method for error protection of a memory

Country Status (1)

Country Link
WO (1) WO2009024886A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5689432B2 (en) * 2012-03-13 2015-03-25 富士通テレコムネットワークス株式会社 Automatic voice report device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6134699A (en) * 1998-01-30 2000-10-17 International Business Machines Corporation Method and apparatus for detecting virtual address parity error for a translation lookaside buffer
US6718494B1 (en) * 2000-12-22 2004-04-06 Intel Corporation Method and apparatus for preventing and recovering from TLB corruption by soft error
US6901540B1 (en) * 1999-11-08 2005-05-31 International Business Machines Corporation TLB parity error recovery

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6134699A (en) * 1998-01-30 2000-10-17 International Business Machines Corporation Method and apparatus for detecting virtual address parity error for a translation lookaside buffer
US6901540B1 (en) * 1999-11-08 2005-05-31 International Business Machines Corporation TLB parity error recovery
US6718494B1 (en) * 2000-12-22 2004-04-06 Intel Corporation Method and apparatus for preventing and recovering from TLB corruption by soft error

Also Published As

Publication number Publication date
WO2009024886A2 (en) 2009-02-26

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