WO2009009566A3 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
WO2009009566A3
WO2009009566A3 PCT/US2008/069479 US2008069479W WO2009009566A3 WO 2009009566 A3 WO2009009566 A3 WO 2009009566A3 US 2008069479 W US2008069479 W US 2008069479W WO 2009009566 A3 WO2009009566 A3 WO 2009009566A3
Authority
WO
WIPO (PCT)
Prior art keywords
under
semiconductor chip
filling resin
semiconductor device
substrate
Prior art date
Application number
PCT/US2008/069479
Other languages
French (fr)
Other versions
WO2009009566A2 (en
WO2009009566A9 (en
Inventor
Mutsumi Masumoto
Original Assignee
Texas Instruments Inc
Mutsumi Masumoto
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2007179461A external-priority patent/JP4569605B2/en
Application filed by Texas Instruments Inc, Mutsumi Masumoto filed Critical Texas Instruments Inc
Publication of WO2009009566A2 publication Critical patent/WO2009009566A2/en
Publication of WO2009009566A3 publication Critical patent/WO2009009566A3/en
Publication of WO2009009566A9 publication Critical patent/WO2009009566A9/en

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

This invention includes a method for manufacturing a semiconductor device by which implementation of a finer pitch for a semiconductor chip (10) can be handled, and the creation of voids inside an under-filling resin can be reduced in order to realize highly reliable flip-chip mounting. It involves a step in which multiple electrodes arranged two-dimensionally on one side of a semiconductor chip are connected to corresponding conductive regions on a substrate (16); a step in which an under-filling resin (20) is injected between the one surface of the semiconductor chip and the substrate; and a step in which the under-filling resin is melted at a temperature higher than its glass transition temperature while under a prescribed pressure and cured.
PCT/US2008/069479 2007-07-09 2008-07-09 Method for manufacturing semiconductor device WO2009009566A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007179461A JP4569605B2 (en) 2007-07-09 2007-07-09 Filling method of underfill of semiconductor device
JP2007-179461 2007-07-09
US12/168,637 US20090017582A1 (en) 2007-07-09 2008-07-07 Method for manufacturing semiconductor device
US12/168,637 2008-07-07

Publications (3)

Publication Number Publication Date
WO2009009566A2 WO2009009566A2 (en) 2009-01-15
WO2009009566A3 true WO2009009566A3 (en) 2009-03-26
WO2009009566A9 WO2009009566A9 (en) 2009-05-14

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PCT/US2008/069479 WO2009009566A2 (en) 2007-07-09 2008-07-09 Method for manufacturing semiconductor device

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000019514A1 (en) * 1998-09-28 2000-04-06 Hitachi, Ltd. Semiconductor package and flip-chip bonding method therefor
US20030080437A1 (en) * 2001-10-26 2003-05-01 Intel Corporation Electronic assembly with filled no-flow underfill and methods of manufacture
US6798072B2 (en) * 2000-11-10 2004-09-28 Hitachi, Ltd. Flip chip assembly structure for semiconductor device and method of assembling therefor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000019514A1 (en) * 1998-09-28 2000-04-06 Hitachi, Ltd. Semiconductor package and flip-chip bonding method therefor
US6798072B2 (en) * 2000-11-10 2004-09-28 Hitachi, Ltd. Flip chip assembly structure for semiconductor device and method of assembling therefor
US20030080437A1 (en) * 2001-10-26 2003-05-01 Intel Corporation Electronic assembly with filled no-flow underfill and methods of manufacture

Also Published As

Publication number Publication date
WO2009009566A2 (en) 2009-01-15
WO2009009566A9 (en) 2009-05-14

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