WO2009007906A1

WO2009007906A1 - Circuitry for synchronous testing of an asynchronous logic module

Info

Publication number: WO2009007906A1
Application number: PCT/IB2008/052722
Authority: WO
Inventors: Frank J. Te Beest
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2007-07-10
Filing date: 2008-07-07
Publication date: 2009-01-15

Abstract

The present invention relates to a circuitry (100', 100') adapted for allowing synchronous testing of an asynchronous logic module (110), the circuitry (100', 100') comprising a first multiplexing circuitry (102) which has two data inputs (I1, I2) and a first select input (I3) for selecting one of the data inputs as a data output, wherein one data input is connected to a synchronous test clock and the other data input is connected to a request input signal for the asynchronous logic module, and a second multiplexing circuitry (104) which has two data inputs and a second select input (I4) for selecting one of the data inputs as a data output, wherein one data input is connected to the synchronous test clock, the other data input is connected to the data output of the first multiplexing circuitry (102) and provided as an acknowledgement output signal (O2) from the circuitry (100', 100'), and the data output (O1) of the second multiplexing circuitry (104) is connected to a clock input of the asynchronous logic module (110), thereby allowing for decoupling of the request input signal for the asynchronous logic module (110) such that the asynchronous logic module (110) becomes synchronously testable. Advantages that follow with the circuitry according to the present invention include the possibility to optimize the clock multiplexers using conventional logic optimizers, thereby obtaining faster and/or smaller circuits. Furthermore, the present invention allows for less netlist restrictions that eventually result in less layout restrictions and thus a higher layout density and thus a smaller circuit. The present invention also relates to method for testing an asynchronous logic module using such a circuitry.

Description

Circuitry for synchronous testing of an asynchronous logic module

FIELD OF THE INVENTION

The present invention relates to circuitry adapted for allowing synchronous testing of an asynchronous logic module, and a method for testing such an asynchronous logic module.

DESCRIPTION OF THE RELATED ART

In large scale circuitry, for example comprising both combinational and sequential logic, a global clock signal is used for progressing a functional process provided by the circuitry. This global clock signal is generally provided as a single input to the circuitry, thereafter divided and/or multiplied and provided to the different blocks/modules of the circuitry. Such a circuitry is said to be clocked in a synchronous manner, i.e. every logic transition of the clock controlling the circuitry potentially leads to a change of the logic state of the circuitry.

Even though synchronous clocking of a circuitry in many ways is advantageous, especially in relation to the development and testing of the circuitry, synchronous circuitries use a large amount of electrical power as all of the blocks/modules of the circuitry continuously are affected by the global clock signal. One way of solving the power consumption problem is by adapting the logical blocks/modules of the circuitry to communicate with each other in an asynchronous manner. An asynchronous circuitry is not governed by a clock circuit or global clock signal, but instead need only wait for signals that indicate completion of instructions and operations, and thus only the blocks/modules really needing to advance forward are affected when that block/module receives an activation signal. These activation signals are specified by simple data transfer protocols, sometimes referred to as handshake signals, for example comprising a request signal and an acknowledgement signal.

To simplify circuitry testing, a circuitry is preferably designed for testing by including a special scan enable signal. When this scan signal is enabled, all flip-flops and/or latches of the circuitry are connected into a long shift register, thereby forming a long scan chain linking each of the flip-flops and/or latches with each other. By providing an arbitrary bit string to the first flip-flop/latch, and thereafter clock the circuitry, the arbitrary bit string can be read out of the last flip-flop/latch of the scan chain, thereby enabling the possibility to test the circuitry. However, when dealing with asynchronously clocked circuits there is a problem as all of the different blocks/modules of the circuitry communicate with each other using handshake signals and not using a global clock.

A solution to this problem is disclosed in WO2006/013524, wherein an external clock signal is multiplexed as a clock signal on the clock inputs of all flip- flops/latches in the data path of the circuitry. However, the multiplexer that is used as a clock-multiplexer in WO2006/013524 is also part of a functional control path, and thus introduces complex timing constraints on the use of the multiplexer and on the overall test strategy.

OBJECT OF THE INVENTION

There is therefore a need for a novel circuitry adapted for allowing synchronous testing of an asynchronous logic module, and more specifically that handles the prior art problems with complex timing constraints due to the introduction of a multiplexer on the data path of the circuitry.

SUMMARY OF THE INVENTION According to an aspect of the invention, the above object is met by a circuitry adapted for allowing synchronous testing of an asynchronous logic module, the circuitry comprising a first multiplexing circuitry which has two data inputs and a first select input for selecting one of the data inputs as a data output, wherein one data input is connected to a synchronous test clock and the other data input is connected to a request input signal for the asynchronous logic module, and a second multiplexing circuitry which has two data inputs and a second select input for selecting one of the data inputs as a data output, wherein one data input is connected to the synchronous test clock, the other data input is connected to the data output of the first multiplexing circuitry and provided as an acknowledgement output signal from the circuitry, and the data output of the second multiplexing circuitry is connected to a clock input of the asynchronous logic module, thereby allowing for decoupling of the request input signal for the asynchronous logic module such that the asynchronous logic module becomes synchronously testable.

The function of the first and the second multiplexers (multiplexing circuitries) are that of multiple-input, single-output switches, having a selector, or select input, that connects one of the data inputs to the single data output. By arranging two such multiplexers on the functional clock path between the received request input signal (i.e. the asynchronous clock for the asynchronous logic module), the transmitted acknowledgement output signal (i.e. the output from the circuitry), and the clock input of the asynchronous logic module, it is possible to test the path between the received request signal and the transmitted acknowledgement signal, as well as the clock path between the first multiplexer and the clock input of the asynchronous logic module. The settings of the different multiplexers are controlled by setting the selection signals of the two different multiplexers.

For example, in a first mode, the first multiplexer is controlled, using the first select signal, to only "forward" the externally provided synchronous test clock, and the second multiplexer is controlled to only forward the output from the first multiplexer to the input of the asynchronous logic module, thereby allowing for testing of the clock path between the first multiplexer and the clock input of the asynchronous logic module. Conversely, in a second mode, the first multiplexer is controlled to only forward the externally provided request signal, and the second multiplexer is controlled to only forward the externally provided synchronous test clock, such that the functional path from request to acknowledge can be tested independently of the clock path to the asynchronous logic module. Also, in a third mode the multiplexers are controlled such that the asynchronous module works in normal mode, i.e. the request signal is used as a clock signal for the asynchronous module.

One fundamental difference with prior art is the fact that the acknowledge signal is connected between the two multiplexers and no longer directly to the clock of the register. However, the acknowledge signal is activated earlier, and this timing difference has to be taken into account during timing verification. Advantages that follow with the circuitry according to the present invention include the possibility to optimize the clock multiplexers using conventional logic optimizers, thereby obtaining faster and/or smaller circuits. Furthermore, the arrangement according to the present invention allows for less netlist restrictions that eventually result in less layout restrictions and a higher layout density, and thus a smaller circuit. Preferably, the asynchronous logic module comprises at least one of a latch and a flip-flop, however, other similar components are possible within the scope of the present invention. When using such components, the output of the second multiplexer can be directly provided as a clock signal to the latch or flip-flop, thereby allowing for the advantageous gating of the clock in accordance with the present invention. In one embodiment, it is possible to adapt the circuitry according to the present invention to also include a third multiplexing circuitry which has two data inputs and a third select input for selecting one of the data inputs as a data, wherein the third multiplexing circuitry is inserted on a synchronous test clock path between the synchronous test clock and the first multiplexing circuitry. This extended arrangement allows for the possibility to use the multiplexing-based test method as disclosed in above referenced WO2006/013524. The test multiplexer function can be added to the circuit without changing the functional delay from request to latch or flip-flop clock. Also, the use of a combined test/clock multiplexer breaks the request to acknowledge paths from a test perspective, resulting in that fewer test multiplexers are needed elsewhere in the circuit, thereby providing an overall performance improvement of the complete circuit.

In another embodiment, it is possible to connect a first asynchronous logic module, which is controlled by the circuitry according to the invention, to other asynchronous logic modules, thereby allowing for scan chain testing of the asynchronous logic modules. As mentioned above, by designing the complete circuit for testing, and including a scan signal for controlling all flip-flops and/or latches such that they are connected with each other in a scan chain, it is possible to perform scan chain testing of the complete circuit. This is again due to the fact that the present invention allows for gating of the functional path between the different request signals and the different clock inputs of the respective flip-flops and/or latches, thereby allowing for testing to be performed in a synchronous manner which considerably simplifies the design and testing procedures.

Preferably, the request signal (i.e. the asynchronous clock) for the asynchronous logic module (e.g. comprising a latch or a flip-flop) and the acknowledgement signal (i.e. the output) from the circuitry are provided and received by a handshake controller. When dealing with large scale circuits, it can be advantageous to include a centralized controller that administrates the communication between the different blocks/modules of the complete circuitry. Furthermore, the select signals provided to the first and the second multiplexers are preferably provided by a test control circuit. This test control circuit can also provide the arbitrary bit pattern used to scan chain test the interconnected/linked asynchronous logic modules.

According to a further aspect of the invention, there is provided a method for testing an asynchronous logic module using a circuitry according to any one of the above embodiments, comprising the steps of receiving control signals intended for the select signals for controlling the respective multiplexing-circuitries such that the circuitry is arranged in a test mode, providing test scan data to an input of the asynchronous logic module, capturing an output of the asynchronous logic module, and outputting the scan data from the asynchronous logic module, whereby the outputted data is usable for analyzing the performance of the asynchronous logic module. By arranging the multiplexers comprised in the circuitry, it will be possible to in a test mode adapt the circuit according to the invention such that the asynchronous logic module can be tested in a synchronous manner. Preferably, the test scan data is provided by the test control circuit or a similar control module, and the capturing, reception of the outputted test data, and the analysis of the test data can be either performed using the test control circuit or an analysis module arranged either internally in the complete circuitry comprising the test circuitry according to the invention and the asynchronous logic module, or externally connected to the complete circuitry. The different types of performance related issues that can be tested include for example checking the functional correctness (e.g. logic- errors) of the asynchronous module, controlling timing issues, and/or performance degradation. It is understood by the skilled addressee that the test mode is not the only mode for using the complete circuit. The circuit according to the present invention can of course be controlled (i.e. by controlling the multiplexers comprised in the circuitry) such that the circuitry have a minimal impact during normal usage mode.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing currently preferred embodiments of the invention, in which:

Fig. Ia is a block diagram illustrating a prior art test circuit; Fig. Ib is a block diagram illustrating a test circuit according to an embodiment of the present invention;

Fig. Ic is a block diagram illustrating a test circuit according to another embodiment of the present invention; and

Fig. 2 is a block diagram illustrating an alternative layout of a test circuit.

DETAILED DESCRIPTION OF CURRENTLY PREFERRED EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which currently preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided for thoroughness and completeness, and fully convey the scope of the invention to the skilled addressee. Like reference characters refer to like elements throughout. Referring now to the drawings and to Fig. Ia in particular, there is depicted a prior art circuit used for testing of an asynchronous module. In Fig. Ia, the test circuit 100 comprises solely a multiplexing circuit 102, the test circuit 100 having three inputs, I₁, 1₂, 13, and two outputs, Oi , O₂, both replicating the same resulting output. The multiplexing circuit 102 provides a gating functionality, i.e. one of the inputs, I3, controls which of the other input signals, I₁, 1₂, that should be connected to the output of the multiplexing circuit 102. One of the outputs, Oi , from the test circuit 100 is connected to the clock input of an asynchronous module, in this case a (d-q) flip-flop 110. However, it could also be possible to use a latch element as the asynchronous module.

The test circuit uses different input signals, directly connected to the multiplexing circuit 102, which comprises a request signal, I₁, used during normal functional mode for providing asynchronous clocking of the flip-flip 110, a test clock signal, I₂, used for providing a synchronous testing possibility for the flip-flop 110 during test mode, and a select signal, I₃, for controlling which of the two input signals Ii , I₂ that should be used (i.e. if the flip-flop should be clocked asynchronous (during normal mode) or synchronous (during test mode)). The second output, O₂, from the test circuit 100 is provided as a acknowledge signal that during normal mode is used for acknowledging that the request signal has reached the flip-flop 110 and that the function provide by an overall circuitry, comprising among other things the flip-flop 110, can be advanced forward.

The reason for including the circuitry 100 is for being able to test the path between the request signal and the acknowledge signal, and this path is tested by setting the select signal I₃ such that the request signal is routed directly out to the outputs of the circuit, i.e. both Oi and O₂. However, during this test, the flip-flop 110 cannot be used since its clock input signal is driven by the test and does not have a known fixed state. For this reason care must be taken not to use the flip-flop 110 during the test of the request-acknowledge path. The effects are a number of constraints that both complicate testing and lead to a higher test cost.

Turning now to Fig. Ib which illustrates a test circuit according to an embodiment of the present invention. In Fig. Ib the test circuit 100' has been extended to include two multiplexing circuits 102, 104. The connectional layout of the test circuit 100' is similar to the test circuit 100 from Fig. Ia, however, the test circuit 100' comprises an additional input signal I₄. The additional input signal I₄ is used for controlling the gating functionality of the second multiplexing circuit 104.

One fundamental difference with the test circuit 100' in regards to the prior art test circuit 100 shown in Fig. Ia is the fact that the acknowledge signal is connected between the two multiplexers and no longer directly to the clock of the flip-flop 110. The result is that the acknowledge signal is activated earlier, resulting in a timing difference that has to be taken into account during timing verification. The resulting functionality of the novel test circuitry 100' gives two paths from the clock input to the register, thus providing for the possibility to test the path from request to acknowledge as well as the clock path to the flip- flop 110. The implementation according to the present embodiment provides for the possibility to optimize the clock multiplexers using conventional logic optimizers to obtain faster and/or smaller circuits.

Fig. Ic illustrates an alternative embodiment of the present invention. In this embodiment, the test circuit 100" has been further extended to also function as a test circuit for the multiplexing based test method described in the above cited WO2006/013524. The test circuit 100" is similar to the test circuit 100' in Fig. Ib, but comprises additionally a third multiplexing circuit 106. The output from the third multiplexing circuit 106 is connected to one of the two inputs of the first multiplexing circuitry 102, i.e. the one not connected to the external request signal. One of the inputs to the third multiplexing circuit 106 is connected to the external synchronous test clock signal, thereby separating the clock path between the provided external synchronous test clock signal and the first multiplexing circuit 102. The test multiplexer functionality can be added to the test circuit according to the present embodiment without changing the functional delay from request to the flip-flop 110 clock. In the present embodiment, two additional inputs, I₅, 1₆, and one additional output, O₃, are included. One of the additional inputs, I5, is used for controlling the additional multiplexing circuit 106, and the other input, I₆, is used for shifting in test data during test mode. Similarly, the additional output, O₃, is provided for outputting the in-shifted test data. The test circuit 106 can work in a couple of different test modes, additional to the normal asynchronous functional mode. The different test modes are described in the above cited WO2006/013524, and comprises for example functional, shift, control, and data test mode.

The use of the combined test/clock multiplexer circuit according to the present embodiment breaks the request to acknowledge paths from a test perspective, meaning that fewer test multiplexers are needed elsewhere in the circuit, thus resulting in an overall performance improvement of the circuits.

In Fig. 2 an alternative test circuit layout 200 is illustrated, providing similar functionality as the test circuit shown in Fig. Ib. However, instead of using the multiplexing circuits 104 and 106, the test circuit 200 solely comprises an AND-gate 202 and an OR-gate 204. The AND-gate 202 and the OR-gate 204 are connected such that the output from the AND-gate 202 is used as a first input for the OR-gate 204, having the externally provided synchronous test clock signal as a second input. The above discussed request signal is provided as a first input to the AND-gate 202, and is also directly connected to the acknowledge output signal providing an output from the test circuit 200. The second input to the AND-gate 202 is a select signal used for controlling the functionality of the test circuit, i.e. for controlling the gating of the clock signal (i.e. the request signal or the externally provided synchronous test clock) for clocking the asynchronous module 210. This embodiment results in a smaller test circuit implementation, but depends on clock gating support in Automatic Test Pattern Generation tools (ATPG tools). Furthermore, since the output of the flip-flop 210 can be different when clocked (vs. when not clocked), this establishes a link between the value of the request and the output of the flip-flop 210. Any fault on the path will break this link and can thus be tested. However, as can be seen from Fig. 2, again a flip-flop 210 is used as the asynchronous module, as it in this embodiment is not possible to use a latch element as the asynchronous module, thus providing less flexibility that the test circuit 100' illustrated in Fig. Ib.

The skilled addressee realizes that the present invention by no means is limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example, from analyzing the test circuit layouts of Fig. Ib and 2 it is possible to find some similarities. Firstly, by visualizing the first multiplexing circuit 102 in Fig. Ib as a gate with two AND-gates gates feeding into an OR-gate, and secondly using one of the inputs of both AND-gates connected to the select signal (one inverted), and then thirdly removing one AND-gate, a structure similar to that in Fig. 2 is achieved. However, once again, the resulting test circuit can only be used for clocking flip-flops and not for clocking latch elements.

In conclusion, it is according to the present invention possible to provide a new clock multiplexer that is completely stuck-at testable, and that also provides independent test modes for control and data path testing, thus preventing complicated timing and test constraints.

Claims

CLAIMS:

1. Circuitry ( 100 ' , 100") adapted for allowing synchronous testing of an asynchronous logic module (110), the circuitry (100', 100") comprising: a first multiplexing circuitry (102) which has two data inputs (Ii , I₂) and a first select input (I₃) for selecting one of the data inputs as a data output, wherein one data input is connected to a synchronous test clock and the other data input is connected to a request input signal for the asynchronous logic module; and a second multiplexing circuitry (104) which has two data inputs and a second select input (I₄) for selecting one of the data inputs as a data output, wherein one data input is connected to the synchronous test clock, the other data input is connected to the data output of the first multiplexing circuitry (102) and provided as an acknowledgement output signal (O₂) from the circuitry (100', 100"), and the data output (Oi) of the second multiplexing circuitry (104) is connected to a clock input of the asynchronous logic module (110), thereby allowing for decoupling of the request input signal for the asynchronous logic module (110) such that the asynchronous logic module (110) becomes synchronously testable.

2. Circuitry (100', 100") according to claim 1, wherein the asynchronous logic module (110) comprising at least one of a latch or a flip-flop.

3. Circuitry (100") according to claim 1 or 2, further comprising a third multiplexing circuitry (106) which has two data inputs and a third select input for selecting one of the data inputs as a data, wherein the third multiplexing circuitry (106) is inserted on a synchronous test clock path between the synchronous test clock and the first multiplexing circuitry (102).

4. Circuitry (100', 100") according to any one of the preceding claims, wherein the asynchronous logic module (110) is connected to other asynchronous logic modules, thereby allowing for scan chain testing of the asynchronous logic modules.

5. Circuitry (100', 100") according to any one of the preceding claims, wherein the request input signal for the asynchronous logic module (110) and the acknowledgement output signal from the circuitry (100', 100") are provided and received by a handshake controller.

6. Circuitry (100', 100") according to any one of the preceding claims, wherein the select signals are provided by a test control circuit.

7. Method for testing an asynchronous logic module (110) using a circuitry (100', 100") according to any one of the above claims, comprising the steps of: receiving control signals intended for the select signals for controlling the respective multiplexing circuitries, such that the circuitry (100', 100") is arranged in a test mode; providing test scan data to an input of the asynchronous logic module (110); capturing an output of the asynchronous logic module (101); and outputting the scan data from the asynchronous logic module (110), whereby the outputted data is usable for analyzing the performance of the asynchronous logic module (110).