WO2009004583A1 - Trench gate field-effect transistor and method of making the same - Google Patents

Trench gate field-effect transistor and method of making the same Download PDF

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Publication number
WO2009004583A1
WO2009004583A1 PCT/IB2008/052655 IB2008052655W WO2009004583A1 WO 2009004583 A1 WO2009004583 A1 WO 2009004583A1 IB 2008052655 W IB2008052655 W IB 2008052655W WO 2009004583 A1 WO2009004583 A1 WO 2009004583A1
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Prior art keywords
trenches
major surface
regions
protrusions
source
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PCT/IB2008/052655
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French (fr)
Inventor
Steven T. Peake
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Nxp B.V.
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Publication of WO2009004583A1 publication Critical patent/WO2009004583A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • This invention relates to the field of Insulated Gate Field Effect transistors, and in particular to transistors having a vertical channel defined adjacent to an insulated gate disposed in a trench in the device (TrenchFETs).
  • TrenchFETs have a wide field of application, and in particular are used as power semiconductors.
  • a typical example of a TrenchFET design is shown in schematic cross-section (not to scale) in Figure 2.
  • a heavily doped n+ substrate 1 is provided with a more lightly doped epitaxial "drift" n- layer 3.
  • a p-doped body, or base, region 5 is interposed between the n- drift layer, and n+ doped source regions 7.
  • a conductive channel is formed between the source and drift regions, adjacent to trenches 1 1 through the p- body.
  • the trenches are filled with conductive material 15, conveniently polycrystalline silicon (poly), to form the gate of the transistor.
  • TrenchFET is a type of Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET), whose switching characteristics are determined by, amongst other things, the gate geometry.
  • MOS Metal Oxide Semiconductor
  • FET Field Effect Transistor
  • the channel width per unit area when a specified field is applied to the gate to open a conductive channel to a "depth” or distance determined by the size of the field, the amount of current which can flow is dependant on the "width" of the channel.
  • the channel forms a current pipe whose capacity is determined by its area ("depth” multiplied by “width”), and whose length ("gate length") is the distance across the body region.
  • the gate "length” actually relates to the vertical depth of the body region, and the gate “width” is determined by the longitudinal length of the trench.
  • conventional MOS transistor terminology is retained, when considering the figures of merit and operational characteristics of the device.
  • the specific on-resistance (Rds on) of a TrenchFET is defined as the drain-source resistance per unit area of device, when the device is in the "on" state.
  • the specific on-resistance is related to, and in part determined by, the area of the pipe or conduction channel: the greater the area of the conduction channel, the lower the specific on-resistance of the device.
  • Cao discloses a power semiconductor device of the trench variety in which the trenches follow a serpentine path. That is, unlike a stripe trench which advances along a single direction, a trench according to Cao changes direction, thereby creating a serpentine path.
  • Cao discloses a low on-resistance power MOSFET with variably spaced trenches and offset contacts. Summary of the invention
  • an insulated gate semiconductor device having a first major surface and a second major surface, the device comprising a plurality of trenches across the first major surface and extending towards the second major surface, gate insulator on the sidewalls of each of the trenches, a conductive gate in each of the trenches, source regions of a first conductivity type adjacent each of the trenches at the first major surface, body regions of a second conductivity type opposite to the first conductivity type adjacent the sidewalls of each of the trenches closer to the second major surface than the source regions, and conductive source contacts in contact with each of the source regions, wherein the conductive source contacts contact the source regions in stripes along a longitudinal direction across the first major surface, and the trenches comprise first regions extending generally in the longitudinal direction across the first major surface and protrusions extending laterally towards the conductive source contacts.
  • the protrusions are rectangular and extend from both sides of the first region. This provides for effective use of the available area, along with design simplicity.
  • the stripes are continuous, which provides for desirably low source resistance.
  • the protrusions take the form of a series of equispaced bars and the first region defines a central spine between the bars.
  • the length of the bars is greater than the width of the first region, and still more preferably, the ratio is between 1 and 5.
  • a method of making an insulated gate semiconductor device comprising the steps, not necessarily in the following order, of: defining a plurality of trenches across a first major surface and extending towards a second major surface, forming gate insulator on the sidewalls of each of the trenches, forming a conductive gate in each of the trenches, defining body regions of a first conductivity type adjacent the sidewalls of each of the trenches, defining source regions of a second conductivity type opposite to the first conductivity type adjacent each of the trenches at the first major surface, defining conductive source contacts in contact with at least each of the source regions, wherein said step of defining the conductive source contacts comprises defining the conductive source contacts to contact the source regions in stripes along a longitudinal direction across the first major surface, and said step of defining a plurality of trenches comprises patterning each of the trenches to comprise first regions extending generally in the longitudinal direction across the first major surface and protrusions extending laterally
  • Figure 1 shows the plan view of a part of a TrenchFET according to an embodiment of the invention
  • Figure 2 shows a section along AA' of Figure 1
  • Figure 3 shows a section along BB' of Figure 1
  • Figure 4 shows a section along CC of Figure 1 in a different plane from
  • Figures 2 and 3 Figure 5 plots the results of a calculation of the variation of channel width per unit area, with the pitch of the protrusion, and compared with a conventional stripe structure;
  • Figure 6 plots the respective trench area for the calculation depicted in figure 5;
  • Figure 7 similarly plots the results of a calculation of the variation in channel width per unit area for various protrusion lengths, with the pitch of the protrusion, and compared with that of a conventional stripe structure, and
  • Figure 8 similarly plots the respective trench area for the calculation depicted in figure 7.
  • FIG. 1 shows, in schematic form only, a plan view of one embodiment of the invention.
  • a trench 1 1 defines a gate region of the TrenchFET.
  • the trench comprises a central spine region 21 which forms a first region extending from the top to the bottom of the figure, and from which extend protrusions, or bars 31 .
  • the bars are rectangular, and the central spine joins the centre of the bars; however, it will be immediately apparent to the person skilled in the art that the protrusions could take alternative shapes, such as trapezoids or truncated triangles. Further it is not essential for the purposes of the invention that the protrusions all have the same shape or dimensions.
  • the first region or spine need not be straight nor lie down the centre of the bars.
  • the source region 7 Adjacent the trenches, lies the source region 7. As will become apparent from the remaining figures, the source region lies adjacent the trenches only near the top of the trenches: deeper in the trenches, the body region, which is not visible in this plan view, is adjacent the trenches. Of particular relevance is the fact that the source region is adjacent the trench along the whole of the perimeter of the trench - both the spine region and the protrusions.
  • contact areas 17 Extending generally parallel to the spine first region and spaced apart from the trench, are contact areas 17.
  • the contact areas are formed by etching through the source region and into the body region, at selected areas of the device to provide a moated stripe or moat.
  • Figure 2 shows a cross section along AA' of Figure 1 . That is, Figure 2 shows a cross-section through the central spine of the trench, but not through a protrusion.
  • figure 2 is schematically representative of a conventional TrenchFET according to the related art, as discussed above.
  • the pitch 22 of the device is the distance between neighbouring trenches are between neighbouring contact stripes.
  • a small pitch is generally desirable, in order to increase the number of trenches per unit width of device, and thus increase the channel width per unit area.
  • one constraint on the pitch is the requirement to have a contact area, or contact stripe, adjacent to each trench.
  • the contacts are typically metal, to provide a very low resistance, although they could be of other conductive material, such as polysilicon.
  • the contacts which extend up the sidewalls of the moat, also serve to electrically short the p body region to the n source region.
  • the body and source regions have to be shorted together, to prevent having a floating region, or even (if the source is floating or un-shorted) an open bipolar junction transistor (BJT). If the p body is left floating with only the source shorted then an open base BJT results. So shorting them both together stops any BJT action from occurring.
  • BJT bipolar junction transistor
  • Oxide layer 19 This oxide is conveniently TEOS Oxide (so called, since it is formed by the
  • Figure 4 shows a partial section CC through Figure 1 .
  • this section is in a different plan to those of Figures 2 and 3. It shows a further series of trench regions separated by source and body regions. In this case, though, there are no contact regions between each trench regions. By comparison with Figure 1 , it is clear that these trench regions are the protrusions visible in the plan view.
  • Xp is the X-Pitch 22
  • CO is the width 23, of the contact moat 17
  • OV is the minimum separation 24, between trench and contact regions
  • Yp is the Y-pitch 25;
  • TB is the length 26 of each protrusion
  • TR is the width 27 of the trench central spine.
  • the channel width, Gw per unit area is the same as the perimeter of the trench (end effects being negligible).
  • the channel width is increased without the need to adjust the contact moat.
  • some of the trench lies further from the source contact region (and thus further from the source metallisation), so resulting in a slightly higher source resistance, this effect is not significant when the device is taken as a whole.
  • the invention is advantageous in terms of the sensitivity of the device to reverse breakdown. Since on average, taken over the whole width of the gate, the source is further from the gate, there is a reduced sensitivity to reverse breakdown. (Although the tips of the protrusions are proximate to the source contact, the remainder of the trench, and in particular the central spine region, are well-spaced therefrom.)
  • a further advantage of the preferred embodiment is that the contact may be modified, for example by implanting, to achieve enhanced RESURF effects, with little determent to reverse breakdown sensitivity or loss of channel width. (By RESURF is meant reduced surface field effect). This results since most of the trench is distant from the source contact.
  • the doping level of the p-body region 5, in TrenchFETs is typically higher near to the contact region (away from the trench and the channel region), in order to reduce the sensitivity of the device to reverse breakdown. This is normally achieved by a second p-type implant - with an implant dose typically 100 times higher than that used to define the main body region, to locally increase the doping level near the contact area.
  • the region defined by such an implant (which is sometimes referred to as a ruggedness implant, or ADP/AP implant), should be physically spaced apart from the channel, since the doping (resulting from the p-body implant) at the channel defines the threshold voltage of the device. Incursion of the higher doping level of the ruggedness implant close to the active region or channel of the device would result in increased and potentially uncontrollable threshold voltage.
  • dashed line 33 delineates an area (the "contact well") near the contact moat, in which the further p-type implant may be used.
  • Such an implant would provide a low resistance current path during reverse blocking and would cover the end of each trench protrusion.
  • the increase in channel width of the preferred embodiment has been achieved by, in part, allowing portions or parts of the channel to be separated further from the source contact regions, than other parts.
  • the embodiment described includes a continuous (linear) moated source contact region, and the central spine of the trench lies further from the moat, than do the tips of the protrusions, by a distance equal to the length of the protrusions.
  • the trench regions may meander, or follow a serpentine path, in order to maintain at least approximately constant distance from the moat.
  • some of the related art does not provide a linear moat, but separated contact regions.
  • the moat does not need to be either linear, or continuous.
  • the designer has a wide freedom over the geometry of the moat.
  • a series of rectangular contact regions may be used, similar to those described by Cao.
  • Figures 5 and 6 show the results of the analysis of an example arrangement according to the preferred embodiment:
  • Figure 5 plots the channel width per unit area for a conventional arrangement (51 ), and trenches according to the embodiment for protrusion lengths of 1 .0 ⁇ m (52) and 1 .2 ⁇ m
  • the new layout does not require any self-alignment or orthogonal implants, for deep sub-micron cell pitches.
  • the gap between the tips of the protrusions and the contact moat was fixed at 0.25 ⁇ m, the trench width at 0.4 ⁇ m, and the moat width at 0.8 ⁇ m.
  • the embodiment appears to be beneficial, in terms of channel width, for Y-pitch less then about 1 .7 ⁇ m, with no penalty to pay in terms of increased gate area.
  • the figures show that for a horizontal stripe length of 2.0um, the channel width is approximately 2.1 e6 ⁇ m (2.1 m) for a Y-cell pitch of 0.8um [achievable with I-Line].
  • the channel width is approximately 2.1 e6 ⁇ m (2.1 m) for a Y-cell pitch of 0.8um [achievable with I-Line].
  • a cell pitch of 0.9 ⁇ m, which is possible with l-line but would require to utilize a 1 in N perpendicular source implant (that is, perpendicular to the trench network) with a significant loss of channel. For the preferred embodiment this is not required as the source is shorted away from the active trench network.

Abstract

A stripe TrenchFET is disclosed in which the gate trench (11) takes the form of a spine (21) with protrusions (31) extending laterally towards a body- contact moat (17). The contact moat runs generally parallel to the spine. This arrangement provides increased gate width.

Description

DESCRIPTION
AN IMPROVED TRENCHFET
Field of the Invention
This invention relates to the field of Insulated Gate Field Effect transistors, and in particular to transistors having a vertical channel defined adjacent to an insulated gate disposed in a trench in the device (TrenchFETs).
Background of the Invention
TrenchFETs have a wide field of application, and in particular are used as power semiconductors. A typical example of a TrenchFET design is shown in schematic cross-section (not to scale) in Figure 2. A heavily doped n+ substrate 1 is provided with a more lightly doped epitaxial "drift" n- layer 3. A p-doped body, or base, region 5 is interposed between the n- drift layer, and n+ doped source regions 7. In operation, a conductive channel is formed between the source and drift regions, adjacent to trenches 1 1 through the p- body. The trenches are filled with conductive material 15, conveniently polycrystalline silicon (poly), to form the gate of the transistor. The walls of the trenches are lined with an insulating material 13, which conveniently is silicon oxide, to form a gate oxide, and thus insulate the gate from the rest of the active part of the device. Metal contacts (not shown) are made to various regions including the gate 15, the source 7, and the drain (i.e. the semiconductor substrate 1 ). Thus a TrenchFET is a type of Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET), whose switching characteristics are determined by, amongst other things, the gate geometry.
For power semiconductors, one important design parameter is the channel width per unit area: when a specified field is applied to the gate to open a conductive channel to a "depth" or distance determined by the size of the field, the amount of current which can flow is dependant on the "width" of the channel. To a first approximation, the channel forms a current pipe whose capacity is determined by its area ("depth" multiplied by "width"), and whose length ("gate length") is the distance across the body region. Of course, in the case of a TrenchFET, the gate "length" actually relates to the vertical depth of the body region, and the gate "width" is determined by the longitudinal length of the trench. However, conventional MOS transistor terminology is retained, when considering the figures of merit and operational characteristics of the device.
The specific on-resistance (Rds on) of a TrenchFET, is defined as the drain-source resistance per unit area of device, when the device is in the "on" state. The specific on-resistance is related to, and in part determined by, the area of the pipe or conduction channel: the greater the area of the conduction channel, the lower the specific on-resistance of the device.
From the above, it will be clear, that there is an interest in improving, or increasing, the channel width per unit area of TrenchFETs.
To improve the channel width per unit area, and thus reduce the specific on-resistance, it is usual to use thin trench widths to achieve a small cell pitch, and thereby increase the number of channels per unit width of device.
Another approach to increasing the channel width per unit area of TrenchFETS is disclosed in United States Patent Application US -2005-
006700, to Cao. Cao discloses a power semiconductor device of the trench variety in which the trenches follow a serpentine path. That is, unlike a stripe trench which advances along a single direction, a trench according to Cao changes direction, thereby creating a serpentine path. Thus Cao discloses a low on-resistance power MOSFET with variably spaced trenches and offset contacts. Summary of the invention
It is an object of the present invention to provide a TrenchFET with an improved performance.
According to the present invention, there is provided an insulated gate semiconductor device having a first major surface and a second major surface, the device comprising a plurality of trenches across the first major surface and extending towards the second major surface, gate insulator on the sidewalls of each of the trenches, a conductive gate in each of the trenches, source regions of a first conductivity type adjacent each of the trenches at the first major surface, body regions of a second conductivity type opposite to the first conductivity type adjacent the sidewalls of each of the trenches closer to the second major surface than the source regions, and conductive source contacts in contact with each of the source regions, wherein the conductive source contacts contact the source regions in stripes along a longitudinal direction across the first major surface, and the trenches comprise first regions extending generally in the longitudinal direction across the first major surface and protrusions extending laterally towards the conductive source contacts.
Advantageously, the protrusions are rectangular and extend from both sides of the first region. This provides for effective use of the available area, along with design simplicity.
Preferably the stripes are continuous, which provides for desirably low source resistance.
Advantageously, in order to make particularly effective use of the available area, the protrusions take the form of a series of equispaced bars and the first region defines a central spine between the bars. Preferably, the length of the bars is greater than the width of the first region, and still more preferably, the ratio is between 1 and 5.
According to another aspect of the invention, there is provided a method of making an insulated gate semiconductor device, comprising the steps, not necessarily in the following order, of: defining a plurality of trenches across a first major surface and extending towards a second major surface, forming gate insulator on the sidewalls of each of the trenches, forming a conductive gate in each of the trenches, defining body regions of a first conductivity type adjacent the sidewalls of each of the trenches, defining source regions of a second conductivity type opposite to the first conductivity type adjacent each of the trenches at the first major surface, defining conductive source contacts in contact with at least each of the source regions, wherein said step of defining the conductive source contacts comprises defining the conductive source contacts to contact the source regions in stripes along a longitudinal direction across the first major surface, and said step of defining a plurality of trenches comprises patterning each of the trenches to comprise first regions extending generally in the longitudinal direction across the first major surface and protrusions extending laterally towards the conductive source contacts.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
Brief description of Drawings
Figure 1 shows the plan view of a part of a TrenchFET according to an embodiment of the invention;
Figure 2 shows a section along AA' of Figure 1 Figure 3 shows a section along BB' of Figure 1 ; Figure 4 shows a section along CC of Figure 1 in a different plane from
Figures 2 and 3; Figure 5 plots the results of a calculation of the variation of channel width per unit area, with the pitch of the protrusion, and compared with a conventional stripe structure;
Figure 6 plots the respective trench area for the calculation depicted in figure 5;
Figure 7 similarly plots the results of a calculation of the variation in channel width per unit area for various protrusion lengths, with the pitch of the protrusion, and compared with that of a conventional stripe structure, and
Figure 8 similarly plots the respective trench area for the calculation depicted in figure 7.
Detailed description of embodiments
Figure 1 shows, in schematic form only, a plan view of one embodiment of the invention. A trench 1 1 defines a gate region of the TrenchFET. The trench comprises a central spine region 21 which forms a first region extending from the top to the bottom of the figure, and from which extend protrusions, or bars 31 . As shown, the bars are rectangular, and the central spine joins the centre of the bars; however, it will be immediately apparent to the person skilled in the art that the protrusions could take alternative shapes, such as trapezoids or truncated triangles. Further it is not essential for the purposes of the invention that the protrusions all have the same shape or dimensions. Moreover, the first region or spine need not be straight nor lie down the centre of the bars.
Adjacent the trenches, lies the source region 7. As will become apparent from the remaining figures, the source region lies adjacent the trenches only near the top of the trenches: deeper in the trenches, the body region, which is not visible in this plan view, is adjacent the trenches. Of particular relevance is the fact that the source region is adjacent the trench along the whole of the perimeter of the trench - both the spine region and the protrusions.
Extending generally parallel to the spine first region and spaced apart from the trench, are contact areas 17. In this embodiment, the contact areas are formed by etching through the source region and into the body region, at selected areas of the device to provide a moated stripe or moat.
Turning now to Figure 2, this shows a cross section along AA' of Figure 1 . That is, Figure 2 shows a cross-section through the central spine of the trench, but not through a protrusion.
Since it does not depict any of the protrusions, figure 2 is schematically representative of a conventional TrenchFET according to the related art, as discussed above. The pitch 22 of the device (X-pitch) is the distance between neighbouring trenches are between neighbouring contact stripes. A small pitch is generally desirable, in order to increase the number of trenches per unit width of device, and thus increase the channel width per unit area. However, one constraint on the pitch is the requirement to have a contact area, or contact stripe, adjacent to each trench.
In the embodiment of the invention shown in the Figures, the distance between the trench in Figure 2, and the contact regions, appears larger than necessary. However, turning now to Figure 3, which shows a section through part of the TrenchFET including the protrusion, it becomes apparent that the pitch of the device is constrained by the length of the protrusions, and the need to space them apart from the contact regions.
Electrical contacts (not shown) are deposited in the contact areas 17 of the moat. The contacts are typically metal, to provide a very low resistance, although they could be of other conductive material, such as polysilicon. As will be apparent from Figure 2, the contacts, which extend up the sidewalls of the moat, also serve to electrically short the p body region to the n source region. The body and source regions have to be shorted together, to prevent having a floating region, or even (if the source is floating or un-shorted) an open bipolar junction transistor (BJT). If the p body is left floating with only the source shorted then an open base BJT results. So shorting them both together stops any BJT action from occurring.
The component parts of the device visible in Figure 3 generally correspond to those in Figure 2, and so bear the same reference numerals; however, whilst the section through the trench shown in Figure 2 is only through the central spine 21 , that shown in Figure 3 is through the length of one of the protrusions 31 (including, though not separately indicated), though the central spine 21 ).
In both Figures 2 and 3, there is shown part of the Oxide layer 19. This oxide is conveniently TEOS Oxide (so called, since it is formed by the
Chemical Vapour Deposition of Oxide from the gaseous compound Tetraethyl
Orthosilicate, Si(OC2Hs)4 ) and overlies most of the device. Holes are etched into the TEOS Oxide, to reveal the contact regions in order to make electrical contact, for example, to the source at contact areas 17. For the purposes of clarity, this oxide is not shown in the plan view of Figure 1 .
Figure 4 shows a partial section CC through Figure 1 . Of particular significance is that this section is in a different plan to those of Figures 2 and 3. It shows a further series of trench regions separated by source and body regions. In this case, though, there are no contact regions between each trench regions. By comparison with Figure 1 , it is clear that these trench regions are the protrusions visible in the plan view.
Inclusion of the protrusions significantly increases the channel width per unit area, as will be demonstrated by the following analysis, in which Xp is the X-Pitch 22; CO is the width 23, of the contact moat 17; OV is the minimum separation 24, between trench and contact regions; Yp is the Y-pitch 25;
TB is the length 26 of each protrusion, and TR is the width 27 of the trench central spine.
For a conventional TrenchFET, the channel width, Gw per unit area, is the same as the perimeter of the trench (end effects being negligible). Thus:
Gw = 2 / (Xp) i.e. Gw = 2 / (TR + 2* OV +CO),
However, for the improved TrenchFET shown in this embodiment, there is a further contribution to the channel width, arising from the protrusions or side-bars. Since each side-bar adds a contribution of 2x TB, the total channel width is now: Gw' = {2 + (4* TB / Yp) / (Xp)J i.e. Gw' = 2*{1 +2*TB/Yp} / (TR +2OV + 2*TB+ CO), i.e. Gw' = 2*{Yp +2*TB} / Yp*(TR +2OV + 2*TB+ CO).
From the above, it is possible to compare the channel width of a device according to this embodiment of the invention with a conventional structure. Results and conclusions from such an analysis will be presented herebelow.
Of particular significance for this embodiment is the fact that, by using a structure with protrusions as described, the channel width is increased without the need to adjust the contact moat. Although it is the case that some of the trench lies further from the source contact region (and thus further from the source metallisation), so resulting in a slightly higher source resistance, this effect is not significant when the device is taken as a whole. Further, the invention is advantageous in terms of the sensitivity of the device to reverse breakdown. Since on average, taken over the whole width of the gate, the source is further from the gate, there is a reduced sensitivity to reverse breakdown. (Although the tips of the protrusions are proximate to the source contact, the remainder of the trench, and in particular the central spine region, are well-spaced therefrom.)
A further advantage of the preferred embodiment is that the contact may be modified, for example by implanting, to achieve enhanced RESURF effects, with little determent to reverse breakdown sensitivity or loss of channel width. (By RESURF is meant reduced surface field effect). This results since most of the trench is distant from the source contact.
The doping level of the p-body region 5, in TrenchFETs is typically higher near to the contact region (away from the trench and the channel region), in order to reduce the sensitivity of the device to reverse breakdown. This is normally achieved by a second p-type implant - with an implant dose typically 100 times higher than that used to define the main body region, to locally increase the doping level near the contact area. The region defined by such an implant (which is sometimes referred to as a ruggedness implant, or ADP/AP implant), should be physically spaced apart from the channel, since the doping (resulting from the p-body implant) at the channel defines the threshold voltage of the device. Incursion of the higher doping level of the ruggedness implant close to the active region or channel of the device would result in increased and potentially uncontrollable threshold voltage.
As cell pitches decrease, it becomes increasingly difficult to maintain separation between the p-body implant region and the ruggedness region.
However, it will be apparent that the present invention allows one to maintain this separation since most of the channel is distant from the ruggedness implant.
An alternative approach to overcome the limitations of decreasing cell pitch, which has been proposed, is to carry out a 1 in N perpendicular implant. In this technique, the implant used to define the n source region is spatially masked, to that it does not cover the whole of the trench network. Thus only a percentage of the channel has a source region coverage. However, in that case, because a percentage of the channel has no source region, channel width has been sacrificed, and hence the device will have a higher Rds on Further, that approach suffers from an increase in sensitivity to reverse breakdown (ruggedness). The preferred embodiment does not suffer from this sacrifice of channel width or ruggedness in the same way.
In some instances, it may be beneficial to extend the ruggedness implant further into the contact moat area. For instance, in Figure 3, dashed line 33 delineates an area (the "contact well") near the contact moat, in which the further p-type implant may be used. Such an implant would provide a low resistance current path during reverse blocking and would cover the end of each trench protrusion.
It will be apparent from the above, that since the increase in channel width is achieve generally remote from the contact moat regions the increase has been achieved with entirely conventional processes, which are readily transferable, and no resort is required to process "tricks" such as self- alignment, or the orthogonal implants discussed earlier.
Further, it will be apparent that the increase in channel width of the preferred embodiment has been achieved by, in part, allowing portions or parts of the channel to be separated further from the source contact regions, than other parts. The embodiment described includes a continuous (linear) moated source contact region, and the central spine of the trench lies further from the moat, than do the tips of the protrusions, by a distance equal to the length of the protrusions. This is in contrast to the prior art discussed, in which the trench regions may meander, or follow a serpentine path, in order to maintain at least approximately constant distance from the moat. As a result, some of the related art does not provide a linear moat, but separated contact regions. In accordance with the present invention, the moat does not need to be either linear, or continuous. However, in contrast with the related art, the designer has a wide freedom over the geometry of the moat. For instance, a series of rectangular contact regions may be used, similar to those described by Cao. In this instance, it may be preferable for the protrusions to have varying lengths, for instance those adjacent to a contact moat region extending less far, that those between the moat regions.
Figures 5 and 6 show the results of the analysis of an example arrangement according to the preferred embodiment: Figure 5 plots the channel width per unit area for a conventional arrangement (51 ), and trenches according to the embodiment for protrusion lengths of 1 .0 μm (52) and 1 .2 μm
(53). Also shown (54) is the ratio between the 1 .Oμm stripe and conventional case (right hand scale). Figure 6 shows the equivalent trench areas per unit area (61 , 62, 63 and 64 respectively). In this analysis, the X-pitch was fixed at
3.2 μm, and the trench width at 0.4 μm. The figures show that the arrangement may be expected to be beneficial, in this example case, for y- pitches below around 1 .6 μm. Also, there is only an apparent penalty (of increased trench area and thus potentially higher or worse gate-drain capacitance Cgd) at Y-pitches greater than around 1 .6 μm. However, significantly, the new layout does not require any self-alignment or orthogonal implants, for deep sub-micron cell pitches.
Figures 7 and 8 show the results of a similar analysis, comparing conventional geometry (protrusion length = 0) 71 , 81 , with a range of protrusion lengths ("stripe") ranging from 0.4 μm (73, 83) to 2 μm (72, 82). In this instance, the gap between the tips of the protrusions and the contact moat was fixed at 0.25 μm, the trench width at 0.4 μm, and the moat width at 0.8 μm. Again it is evident that the embodiment appears to be beneficial, in terms of channel width, for Y-pitch less then about 1 .7 μm, with no penalty to pay in terms of increased gate area. As a worked example the figures show that for a horizontal stripe length of 2.0um, the channel width is approximately 2.1 e6μm (2.1 m) for a Y-cell pitch of 0.8um [achievable with I-Line]. To achieve this with a conventional structure would require a cell pitch of 0.9μm, which is possible with l-line but would require to utilize a 1 in N perpendicular source implant (that is, perpendicular to the trench network) with a significant loss of channel. For the preferred embodiment this is not required as the source is shorted away from the active trench network.
From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of TrenchFETs and which may be used instead of, or in addition to, features already described herein.
Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination. The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
For the sake of completeness it is also stated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, and reference signs in the claims shall not be construed as limiting the scope of the claims.

Claims

1 . An insulated gate semiconductor device having a first major surface and a second major surface, the device comprising a plurality of trenches (1 1 ) across the first major surface and extending towards the second major surface, gate insulator (13) on the sidewalls of each of the trenches, a conductive gate (15) in each of the trenches, source regions (7) of a first conductivity type adjacent each of the trenches at the first major surface, body regions (5) of a second conductivity type opposite to the first conductivity type adjacent the sidewalls of each of the trenches closer to the second major surface than the source regions, and conductive source contacts (17) in contact with each of the source regions, wherein the conductive source contacts (17) contact the source regions in stripes along a longitudinal direction across the first major surface, and the trenches comprise first regions (21 ) extending generally in the longitudinal direction across the first major surface and protrusions (31 ) extending laterally towards the conductive source contacts.
2. A device according to claim 1 wherein the protrusions are generally rectangular.
3. A device according to claim 1 or 2 wherein the stripes are continuous.
4. A device according to any preceding claim, wherein the protrusions extend from both sides of the first region.
5. A device according to claim 4 wherein the protrusions take the form of a series of equispaced bars (31 ) and the first region defines a central spine between the bars.
6. A device according to claim 5, wherein the length (TB) of the bars is greater than the width (TR) of the first region.
7. A device according to claim 5, wherein the ratio between the length (TB) of the bars and the width (TR) of the first region is between 1 and 5.
8. A method of making an insulated gate semiconductor device, comprising the steps, not necessarily in the following order, of: defining a plurality of trenches (1 1 ) across a first major surface and extending towards a second major surface, forming gate insulator (13) on the sidewalls of each of the trenches, forming a conductive gate (15) in each of the trenches, defining body regions (5) of a first conductivity type adjacent the sidewalls of each of the trenches, defining source regions (7) of a second conductivity type opposite to the first conductivity type adjacent each of the trenches at the first major surface, defining conductive source contacts (17) in contact with at least each of the source regions, wherein said step of defining the conductive source contacts (17) comprises defining the conductive source contacts to contact the source regions in stripes along a longitudinal direction across the first major surface, and said step of defining a plurality of trenches comprises patterning each of the trenches to comprise first regions (21 ) extending generally in the longitudinal direction across the first major surface and protrusions (31 ) extending laterally towards the conductive source contacts.
A method according to claim 8, wherein the trenches are patterned such that the protrusions take the form of a series of equispaced bars and the first region defines a central spine between the bars.
PCT/IB2008/052655 2007-07-05 2008-07-02 Trench gate field-effect transistor and method of making the same WO2009004583A1 (en)

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WO2005048352A1 (en) * 2003-11-12 2005-05-26 Toyota Jidosha Kabushiki Kaisha Trench gate field effect devices
WO2008010148A1 (en) * 2006-07-14 2008-01-24 Nxp B.V. Trench field effect transistors

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US20050006700A1 (en) * 2003-06-11 2005-01-13 International Rectifier Corporation Low on resistance power MOSFET with variably spaced trenches and offset contacts
WO2005048352A1 (en) * 2003-11-12 2005-05-26 Toyota Jidosha Kabushiki Kaisha Trench gate field effect devices
WO2008010148A1 (en) * 2006-07-14 2008-01-24 Nxp B.V. Trench field effect transistors

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KR20200069924A (en) * 2018-12-07 2020-06-17 현대자동차주식회사 Semiconductor device
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