WO2009003129A3 - Methods and circuits for adaptive equalization and channel characterization using live data - Google Patents

Methods and circuits for adaptive equalization and channel characterization using live data Download PDF

Info

Publication number
WO2009003129A3
WO2009003129A3 PCT/US2008/068409 US2008068409W WO2009003129A3 WO 2009003129 A3 WO2009003129 A3 WO 2009003129A3 US 2008068409 W US2008068409 W US 2008068409W WO 2009003129 A3 WO2009003129 A3 WO 2009003129A3
Authority
WO
WIPO (PCT)
Prior art keywords
lane
signal
performance
bit errors
isi
Prior art date
Application number
PCT/US2008/068409
Other languages
French (fr)
Other versions
WO2009003129A2 (en
Inventor
Hae-Chang Lee
Jihong Ren
Brian S Leibowitz
Christopher J Madden
Qi Lin
Jared L Zerbe
Original Assignee
Rambus Inc
Hae-Chang Lee
Jihong Ren
Brian S Leibowitz
Christopher J Madden
Qi Lin
Jared L Zerbe
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc, Hae-Chang Lee, Jihong Ren, Brian S Leibowitz, Christopher J Madden, Qi Lin, Jared L Zerbe filed Critical Rambus Inc
Publication of WO2009003129A2 publication Critical patent/WO2009003129A2/en
Publication of WO2009003129A3 publication Critical patent/WO2009003129A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/203—Details of error rate determination, e.g. BER, FER or WER
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/205—Arrangements for detecting or preventing errors in the information received using signal quality detector jitter monitoring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0224—Channel estimation using sounding signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/024—Channel estimation channel estimation algorithms
    • H04L25/0242—Channel estimation channel estimation algorithms using matrix methods
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.
PCT/US2008/068409 2007-06-27 2008-06-26 Methods and circuits for adaptive equalization and channel characterization using live data WO2009003129A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US93761507P 2007-06-27 2007-06-27
US60/937,615 2007-06-27
US93780907P 2007-06-29 2007-06-29
US60/937,809 2007-06-29
US297907P 2007-11-13 2007-11-13
US61/002,979 2007-11-13

Publications (2)

Publication Number Publication Date
WO2009003129A2 WO2009003129A2 (en) 2008-12-31
WO2009003129A3 true WO2009003129A3 (en) 2009-04-16

Family

ID=40019360

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/068409 WO2009003129A2 (en) 2007-06-27 2008-06-26 Methods and circuits for adaptive equalization and channel characterization using live data

Country Status (1)

Country Link
WO (1) WO2009003129A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9222972B1 (en) 2010-09-17 2015-12-29 Altera Corporation On-die jitter generator
US8433958B2 (en) * 2010-09-17 2013-04-30 Altera Corporation Bit error rate checker receiving serial data signal from an eye viewer
US9882748B2 (en) * 2014-03-10 2018-01-30 Intel Corporation Technologies for configuring transmitter equalization in a communication system
US9264187B1 (en) * 2014-10-09 2016-02-16 Intel Corporation Measuring bit error rate during runtime of a receiver circuit
US11126585B1 (en) 2020-03-09 2021-09-21 Western Digital Technologies, Inc. Data storage device with improved interface transmitter training
US11288225B2 (en) 2020-04-14 2022-03-29 Western Digital Technologies, Inc. Adapting transmitter training behavior based upon assumed identity of training partner
TWI733488B (en) * 2020-06-10 2021-07-11 瑞昱半導體股份有限公司 Signal processing circuit in digital domain and method thereof

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1193931A2 (en) * 2000-10-02 2002-04-03 Lsi Logic Corporation Adaptive equalization in a receiver of serial data
US20020060820A1 (en) * 2000-10-20 2002-05-23 Alcatel Receiver with feedback filter, and eye monitor for the feedback filter
EP1147624B1 (en) * 1998-11-18 2002-08-28 Nokia Corporation A method for improved channel impulse response estimation in tdma systems
US6512802B1 (en) * 1999-09-28 2003-01-28 Nortel Networks Limited Method and apparatus for equalization and data symbol detection for MPSK modulation
WO2003019810A2 (en) * 2001-08-28 2003-03-06 Igor Anatolievich Abrosimov Adaptive equaliser for reducing distortion in a communication channel
US20040008764A1 (en) * 2002-07-09 2004-01-15 Jae-Hyun Seo Pre-equalizer, VSB transmission system using the same, and transmission method thereof
WO2005091582A1 (en) * 2004-03-12 2005-09-29 Intel Corporation System and method for automatically calibrating two-tap and multi-tap equalization for a communications link
US20060034358A1 (en) * 2004-08-16 2006-02-16 Hitoshi Okamura Methods and transmitters for loop-back adaptive pre-emphasis data transmission
US20060067440A1 (en) * 2004-09-30 2006-03-30 International Business Machines Corporation High Speed Multi-Mode Receiver
US20060067688A1 (en) * 2004-09-24 2006-03-30 Inman Brad L Optical transceiver tester
US20060280272A1 (en) * 2003-04-09 2006-12-14 Stojanovic Vladimir M Data-level clock recovery
EP1758287A2 (en) * 2005-08-24 2007-02-28 Samsung Electronics Co., Ltd. Circuit and method of measuring eye diagram size of a serial bit stream

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1147624B1 (en) * 1998-11-18 2002-08-28 Nokia Corporation A method for improved channel impulse response estimation in tdma systems
US6512802B1 (en) * 1999-09-28 2003-01-28 Nortel Networks Limited Method and apparatus for equalization and data symbol detection for MPSK modulation
EP1193931A2 (en) * 2000-10-02 2002-04-03 Lsi Logic Corporation Adaptive equalization in a receiver of serial data
US20020060820A1 (en) * 2000-10-20 2002-05-23 Alcatel Receiver with feedback filter, and eye monitor for the feedback filter
WO2003019810A2 (en) * 2001-08-28 2003-03-06 Igor Anatolievich Abrosimov Adaptive equaliser for reducing distortion in a communication channel
US20040008764A1 (en) * 2002-07-09 2004-01-15 Jae-Hyun Seo Pre-equalizer, VSB transmission system using the same, and transmission method thereof
US20060280272A1 (en) * 2003-04-09 2006-12-14 Stojanovic Vladimir M Data-level clock recovery
WO2005091582A1 (en) * 2004-03-12 2005-09-29 Intel Corporation System and method for automatically calibrating two-tap and multi-tap equalization for a communications link
US20060034358A1 (en) * 2004-08-16 2006-02-16 Hitoshi Okamura Methods and transmitters for loop-back adaptive pre-emphasis data transmission
US20060067688A1 (en) * 2004-09-24 2006-03-30 Inman Brad L Optical transceiver tester
US20060067440A1 (en) * 2004-09-30 2006-03-30 International Business Machines Corporation High Speed Multi-Mode Receiver
EP1758287A2 (en) * 2005-08-24 2007-02-28 Samsung Electronics Co., Ltd. Circuit and method of measuring eye diagram size of a serial bit stream

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"SET OF STRESS TESTS FOR EVALUATING SERIALIZED OPTICAL DATA LINKS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 32, no. 3A, 1 August 1989 (1989-08-01), pages 396 - 398, XP000049421, ISSN: 0018-8689 *
KARABULUT G Z ET AL: "Sparse channel estimation using orthogonal matching pursuit algorithm", VEHICULAR TECHNOLOGY CONFERENCE, 2004. VTC2004-FALL. 2004 IEEE 60TH LOS ANGELES, CA, USA 26-29 SEPT. 2004, PISCATAWAY, NJ, USA,IEEE, vol. 6, 26 September 2004 (2004-09-26), pages 3880 - 3884, XP010790147, ISBN: 978-0-7803-8521-4 *
PALACHARLA P ET AL: "Techniques for accelerated measurement of low bit error rates in computer data links", COMPUTERS AND COMMUNICATIONS, 1995., CONFERENCE PROCEEDINGS OF THE 199 5 IEEE FOURTEENTH ANNUAL INTERNATIONAL PHOENIX CONFERENCE ON SCOTTSDALE, AZ, USA 28-31 MARCH 1995, NEW YORK, NY, USA,IEEE, US, 28 March 1995 (1995-03-28), pages 184 - 190, XP010149389, ISBN: 978-0-7803-2492-3 *

Also Published As

Publication number Publication date
WO2009003129A2 (en) 2008-12-31

Similar Documents

Publication Publication Date Title
WO2009003129A3 (en) Methods and circuits for adaptive equalization and channel characterization using live data
US7516029B2 (en) Communication channel calibration using feedback
Stojanovic et al. Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery
KR20060131883A (en) System and method for automatically calibrating two-tap and multi-tap equalization for a communications link
WO2008070138A9 (en) Methods and circuits for asymmetric distribution of channel equalization between transceiver devices
Lee et al. A 95fJ/b current-mode transceiver for 10mm on-chip interconnect
US20100289544A1 (en) Receiver With Enhanced Clock And Data Recovery
US8429439B2 (en) Inter-pair skew adjustment
WO2011062823A3 (en) Receiver with time-varying threshold voltage
EP1752882B1 (en) Circuitry and methods for programmably adjusting the duty cycles of serial data signals
KR20080100843A (en) Asymmetric control of high-speed bidirectional signaling
US9973356B1 (en) Slicer and decision feedback equalization circuitry
US8842745B2 (en) Transmission unit adopting a differential voltage driving system, transmission unit and receiving unit selectively adopting a differential current driving system, differential voltage driving system, and interface system
US7358771B1 (en) System including a single ended switching topology for high-speed bidirectional signaling
Kim et al. A 5.2-Gb/s low-swing voltage-mode transmitter with an AC-/DC-coupled equalizer and a voltage offset generator
US9491011B2 (en) Methods and systems for transmitting data by modulating transmitter filter coefficients
US8324936B2 (en) Transmitter and receiver of differential current driving mode, and interface system of differential current driving mode including the same
Tomita et al. A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-$\mu {\hbox {m}} $ CMOS
KR100897282B1 (en) Receiver Circuit
US10778478B2 (en) Fast-settling voltage reference generator for SERDES applications
Lee et al. A single-ended parallel transceiver with four-bit four-wire four-level balanced coding for the point-to-point dram interface
US7505332B1 (en) Input offset correction for asymmetric control of high-speed bidirectional signaling
KR20080017973A (en) Data transmitter and method thereof
US9484916B1 (en) Adaptive on-chip termination circuitry
Fan et al. A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08772076

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08772076

Country of ref document: EP

Kind code of ref document: A2