WO2008155839A1 - 命令処理装置 - Google Patents
命令処理装置 Download PDFInfo
- Publication number
- WO2008155839A1 WO2008155839A1 PCT/JP2007/062425 JP2007062425W WO2008155839A1 WO 2008155839 A1 WO2008155839 A1 WO 2008155839A1 JP 2007062425 W JP2007062425 W JP 2007062425W WO 2008155839 A1 WO2008155839 A1 WO 2008155839A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- instruction
- instructions
- decoding part
- execution pipeline
- decoded
- Prior art date
Links
- 238000012545 processing Methods 0.000 abstract 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
Abstract
本発明は、一時には1つのスレッドについて複数の命令を同時に保持してその保持している命令を解読するデコード部109と、デコード部109で解読された命令の処理を実行する、互いに異なるスレッドに属する複数の命令それぞれが表す処理を同時に実行可能な実行パイプライン220と、デコード部109によって解読済の命令を受け取り実行パイプライン220に渡す、その解読済の命令が、シンク属性の命令である場合には、その命令が実行可能な条件が整うまで保持した後で実行パイプライン220に渡すリザベーションステーション210と、デコード部109よりも前に簡易な解読によってその命令がシンク属性の命令であるか否かを確認するプリデコード部108と、シンク属性の命令よりも後続の命令についてはデコード部109への投入を中断して保持する命令バッファ104とを備えた。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/062425 WO2008155839A1 (ja) | 2007-06-20 | 2007-06-20 | 命令処理装置 |
EP07767263A EP2169538A4 (en) | 2007-06-20 | 2007-06-20 | INSTRUCTION PROCESSOR |
JP2009520193A JP5093237B2 (ja) | 2007-06-20 | 2007-06-20 | 命令処理装置 |
US12/654,311 US20100106945A1 (en) | 2007-06-20 | 2009-12-16 | Instruction processing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/062425 WO2008155839A1 (ja) | 2007-06-20 | 2007-06-20 | 命令処理装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/654,311 Continuation US20100106945A1 (en) | 2007-06-20 | 2009-12-16 | Instruction processing apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008155839A1 true WO2008155839A1 (ja) | 2008-12-24 |
Family
ID=40156005
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/062425 WO2008155839A1 (ja) | 2007-06-20 | 2007-06-20 | 命令処理装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20100106945A1 (ja) |
EP (1) | EP2169538A4 (ja) |
JP (1) | JP5093237B2 (ja) |
WO (1) | WO2008155839A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020027616A (ja) * | 2018-08-10 | 2020-02-20 | 北京百度网▲訊▼科技有限公司Beijing Baidu Netcom Science And Technology Co.,Ltd. | コマンド実行方法及び装置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8984511B2 (en) * | 2012-03-29 | 2015-03-17 | Advanced Micro Devices, Inc. | Visibility ordering in a memory model for a unified computing system |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07175649A (ja) * | 1993-12-16 | 1995-07-14 | Nippon Steel Corp | プロセッサ |
US20050273583A1 (en) * | 2004-06-02 | 2005-12-08 | Paul Caprioli | Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2908598B2 (ja) * | 1991-06-06 | 1999-06-21 | 松下電器産業株式会社 | 情報処理装置 |
US5337415A (en) * | 1992-12-04 | 1994-08-09 | Hewlett-Packard Company | Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency |
TW260765B (ja) * | 1994-03-31 | 1995-10-21 | Ibm | |
TW353732B (en) * | 1994-03-31 | 1999-03-01 | Ibm | Processing system and method of operation |
US6694425B1 (en) * | 2000-05-04 | 2004-02-17 | International Business Machines Corporation | Selective flush of shared and other pipeline stages in a multithread processor |
US7310722B2 (en) * | 2003-12-18 | 2007-12-18 | Nvidia Corporation | Across-thread out of order instruction dispatch in a multithreaded graphics processor |
US7237094B2 (en) * | 2004-10-14 | 2007-06-26 | International Business Machines Corporation | Instruction group formation and mechanism for SMT dispatch |
US7664936B2 (en) * | 2005-02-04 | 2010-02-16 | Mips Technologies, Inc. | Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages |
US7254697B2 (en) * | 2005-02-11 | 2007-08-07 | International Business Machines Corporation | Method and apparatus for dynamic modification of microprocessor instruction group at dispatch |
US7266674B2 (en) * | 2005-02-24 | 2007-09-04 | Microsoft Corporation | Programmable delayed dispatch in a multi-threaded pipeline |
US7953959B2 (en) * | 2005-06-15 | 2011-05-31 | Panasonic Corporation | Processor |
-
2007
- 2007-06-20 EP EP07767263A patent/EP2169538A4/en not_active Withdrawn
- 2007-06-20 JP JP2009520193A patent/JP5093237B2/ja not_active Expired - Fee Related
- 2007-06-20 WO PCT/JP2007/062425 patent/WO2008155839A1/ja active Application Filing
-
2009
- 2009-12-16 US US12/654,311 patent/US20100106945A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07175649A (ja) * | 1993-12-16 | 1995-07-14 | Nippon Steel Corp | プロセッサ |
US20050273583A1 (en) * | 2004-06-02 | 2005-12-08 | Paul Caprioli | Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor |
Non-Patent Citations (1)
Title |
---|
"SPARC JPS1 Implementation Supp lement: Fujitsu SPARC64 V, edition 1.0", FUJITSU LTD., 1 July 2002 (2002-07-01), pages 55 - 56, XP003023940 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020027616A (ja) * | 2018-08-10 | 2020-02-20 | 北京百度网▲訊▼科技有限公司Beijing Baidu Netcom Science And Technology Co.,Ltd. | コマンド実行方法及び装置 |
JP7012689B2 (ja) | 2018-08-10 | 2022-01-28 | 北京百度网▲訊▼科技有限公司 | コマンド実行方法及び装置 |
US11422817B2 (en) | 2018-08-10 | 2022-08-23 | Kunlunxin Technology (Beijing) Company Limited | Method and apparatus for executing instructions including a blocking instruction generated in response to determining that there is data dependence between instructions |
Also Published As
Publication number | Publication date |
---|---|
US20100106945A1 (en) | 2010-04-29 |
JPWO2008155839A1 (ja) | 2010-08-26 |
EP2169538A4 (en) | 2010-12-01 |
EP2169538A1 (en) | 2010-03-31 |
JP5093237B2 (ja) | 2012-12-12 |
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