WO2008145915A2

WO2008145915A2 - Compound for processing a digital signal, and corresponding modulation and/or demodulation device, modulation and/or demodulation method and computer software

Info

Publication number: WO2008145915A2
Application number: PCT/FR2008/050703
Authority: WO
Inventors: Chawki Sahnine; Denis Callonnec; Nacer-Eddine Zergainoh; Frédéric PETROT
Original assignee: France Telecom
Priority date: 2007-04-24
Filing date: 2008-04-18
Publication date: 2008-12-04
Also published as: WO2008145915A3

Abstract

The invention relates to a component (81) for processing a digital signal, that comprises: an assembly (101, 111) of elementary calculation modules including a connection means; and a control unit (83) capable of configuring the connection means of at least a portion of the elementary modules in order to achieve two connection structures with said elementary modules respectively ensuring a mathematical conversion function of the digital signal between the time domain and the frequency domain, and a multiple-phase filtration function by a prototype signal function.

Description

Component for processing a digital signal, modulation and / or demodulation device, modulation and / or demodulation method and corresponding computer program.

FIELD OF THE DISCLOSURE The field of the invention is that of telecommunications, by wired or wireless means.

More specifically, the invention relates to communications based on multicarrier modulations, for example OFDM type (Orthogonal Frequency Division Multiplexing, in English "Orthogonal frequency division multiplexing").

In particular, the technique according to the invention is well suited to the modulation and demodulation of OFDM / Quadrature Amplitude Modulation (OFDM / OFDM) or OFDM / OQAM signals (in English OFDM / Offset Quadrature Amplitude Modulation). For which the carriers are shaped by a prototype function, for example the IOTA function ("Isotropic Orthogonal Transform Algorithm").

The invention relates more particularly to a component of the physical layer of a communication system, performing signal processing operations, including modulation and / or demodulation operations. 2. Prior Art

2.1 OFDM / OQAM Modulations and Demodulations The following is a description of the prior art relating to the OFDM / OQAM ("Offset Quadrature Amplitude Modulation") type of modulation, associated with an IOTA waveform. The modulation or demodulation operations in a multicarrier transmission system of this type are conventionally carried out using two separate components, one performing a Fast Fourier Transform (FFT) and the other one. other a polyphase filtering by the prototype function IOTA, for the synthesis of the OFDM / OQAM signal. FIGS. 1 and 2 respectively illustrate the architecture of a modulator and an OFDM / OQAM demodulator with shaping filtering, according to the prior art.

As illustrated in connection with FIG. 1, a modulator conventionally implements the following steps: decomposition 11 of the complex data of an incoming bit stream x {t)

(with x (t) - a (t) + jb (t)) into two real data a (t) and b (t); quadrature modulation 12, implementing a multiplication of j) (-1), where L is the truncation length of the prototype function, i.e., the number of symbols of the OFDM / OQAM signal that the function filters prototype. This quadrature modulation step ensures a phase shift of π / 2 in time and in frequency of each carrier, which makes it possible to guarantee a complete orthogonality of the sub-carriers; - serial / parallel conversion 13; Fourier inverse transformation (IFFT) 14; put on hold in a buffer; filtering 16 by the prototype function; parallel / serial conversion 17, delivering an OFDM / OQAM / IOTA signal s (t).

A corresponding demodulator, as illustrated in relation to FIG. 2, conventionally implements the following steps: serial / parallel conversion 21 of the received signal y (t); filtering 22 by the prototype function; - Hold 23 in a buffer memory; direct Fourier transformation (FFT) 24; parallel / serial conversion 25; phase and amplitude correction 26, implementing a multiplication

_{! e} -J ^θ > n, ι (- _j y ^{+ m} uγ ^{(n +} v _e - ^jβ _m , ι of the signal by ^ - ^ ^ - ^, where

PmJ ^W Pm, l correct the phase and amplitude of the signal altered by the channel, and W the band allocated to the signal, such that W = ^ y, with M the number of samples

a symbol and τ _Q the duration of a symbol; extraction (27) of the real part and recombination (28) of the real data by two, to form a complex piece of data, and to reconstruct the bit stream jc (f).

2.2 The Fourier transform

Here are some reminders about the Fourier transform. The equation of the discrete Fourier transform is written:

NI X (k) = Σ x (n) W ^ ^k ,

TTzfcn. . (2πnk λ where Wjj = e - j sml 1 (called factors of

rotations), with: n the indices of temporal samples; k the indices of the frequency samples; - N the number of points of the FFT, which also corresponds to the number of subcarriers in the OFDM modulation. The algorithm for calculating the FFT, or fast Fourier transform, is based on the implementation of basic operations, known as "butterfly", or "Butterfly" (BF) in English. More precisely, each "Butterfly" module is composed of a set of complex adders. Some "Butterfly" modules also include a set of complex multipliers.

We recall that by definition, a complex addition makes it possible to add two complex numbers (of the form a + jb, where a represents the real part and b the imaginary part). A complex adder is therefore composed of two real adders. A complex multiplication makes it possible to multiply two complex numbers. A complex multiplier is composed of four real multipliers and two real adders / subtractors. More precisely, the realization of an N-point FFT requires log ₂ N

NN stages each comprising - butterflies, for a total of - log ₂ iV butterflies.

2. 2 _*

Thus, FIG. 3 illustrates an example of calculation of an 8-point FFT, using the radix-2 algorithm (which means that each butterfly has two inputs) in time interleaving.

As indicated above, the realization of an 8-point FFT requires

N Iog ₂ 8 = 3 stages 31, 32, 33, each comprising - = 4 butterflies (corresponding

N at the crossroads in Figure 3), for a total of - log ₂ iV = 12 butterflies. The

Figure 4 illustrates computational operations performed at a butterfly in the case of a radix-2 algorithm.

Materially, the calculation algorithm of the FFT can be implemented in an architecture as illustrated in FIG. 5, comprising a "butterfly" calculation module 51 (also denoted by BF), an N-point memory 52 containing the samples in question. FFT input, and a control unit 53. Thus, the FFT algorithm consists of taking the samples two by two in the memory 52, performing the operation butterfly 51, and writing the results in the same memory.

These operations are performed butterfly butterfly, and floor by floor, until the last butterfly of the last floor. For example, by resuming the algorithm illustrated in FIG. 3, the samples x [o] and x [4] are read from the memory, processed at the butterfly 311, and the results of the butterfly operation are stored in the same memory. memory ; then it's the turn of the samples

and JC [O], jc [l] and * [5], and * [3] and

of the first stage 31. The butterflies of the following stages are then considered. More precisely, once the first stage 31 has been traversed, the algorithm is repeated for the second stage 32, but this time in a different order, taking the samples

c [θ] and

and * [3], and * [5] and JC [7]. Then we resume the algorithm for the third stage 33, with the samples

and * [l], and x [_5 ^~ ],

and j: [3], and

In order to increase the processing flow rate, type architectures

"Pipeline" have been proposed, for example in the document "New radix-2 to the 4th power pipeline FFT processor" J.-Y. Oh and M. -S. Lim (The institute of

Electronics, Information and Communication Engineer, Volume E88, No. 8,

2005). These architectures make it possible to simultaneously process several stages.

According to this approach, illustrated for example in FIG. 6 for a 256-point FFT using a radix-2 algorithm, log ₂ iV butterflies are used at the same time (ie 8 butterflies), and one butterfly per stage (thus eight stages).

The architecture receives the data (samples) one by one, according to the rhythm of the clock CLK. The butterfly operation is performed every two samples received, and its result sent to the next stage.

In this example, the symbol O corresponds to an optimized complex multiplier, and the symbol ® to a complex multiplier. It is recalled that the optimized complex multipliers correspond to multiplications by rotational factors equal to ± - V2 ± J V2. Multiplications by these factors

2. 2 _* can be realized by using multipliers with constants, which can be implemented by shift registers and adders. Optimized complex multipliers therefore have a lower complexity than complex multipliers.

2.3 Polyphase filtering

The filtering consists in weighting (that is to say, multiplying) the samples at the output of the inverse Fourier transform (IFFT) by the coefficients of the prototype function (for example the IOTA function), and to add the results to the results of the filtering of the previous LI outputs of the inverse FFT.

More precisely, the OFDM / OQAM / IOTA signal obtained at the output of the filtering step is of the following form: + oo 2M-1

^S V> OFDM / OQAM I IOTA ^~ Lu Lu ^a n, _m J ° ^ nτ _Q ⁾ in = -∞ m = 0 with a _nm the real samples at the input of the filtering step.

In the discrete domain, the signal OFDM / OQAM / IOTA at the output of the modulator can be expressed in the following form:

\>

with:

O ≤ k ≤ M - 1; I e9? ;

O ≤ q ≤ L - 1; O if a odd. ; Sk + qM ^Sl 1 P ^Mr i ^m P ^air

o ^u _{k +} 8 ^ ^es _qM ^are samples of the function calculated Iota all y.

FIGS. 7A to 7C thus illustrate the implementation of the polyphase filtering algorithm, according to a prototype function of the IOTA type of truncation length L = 2, represented by a triangular function 71, and processing M = A samples.

C _{nk is} the samples at the output of the transformation step of

Fourier inverse, at each time / symbol OFDM / OQAM, and S _{k + M} the samples at the output of the filtering step, at each time / symbol OFDM / OQAM.

More precisely, at the exit of the inverse FFT, the expression of the samples can take the following form:

where C _nk and C _{n k + M} represent respectively the first M and the last M samples of the inverse Fourier transform.

As illustrated in connection with FIG. 7A, the IOTA function is sampled at a frequency γ, and 2ML values of the IOTA function are

obtained (the symmetry of the IOTA function makes it possible to store in ROM, in English "read-only memory", in French "read-only memory", only ML + 1 values). In other words, sixteen values (2ML = 16) of the IOTA function 71, denoted go to gi5, are sampled, all y.

As illustrated in connection with FIG. 7B for the first symbol

OFDM / OQAM (K - O), eight (2M = 8) new complex samples of the inverse FFT (C _{0 0} , C _{0 1} , C _{0 2} , C _{0 3} , C _{0 4} , C _{0 5} , C _{0 6} , C _{0 7} ) are multiplied by the IOTA function at each symbol time OFDM / OQAM, and deliver M = A complex samples (C _Qfi g _Q , C ₀ ^ g ₁ , C _Qa g ₂ , C ₀ ^ g ₃ ). At subsequent iterations, the result array is shifted and M zeros are introduced at the end of the array.

Thus, as illustrated in connection with FIG. 7C for the second OFDM / OQAM symbol (K = I), four "zeros" are introduced at the end of the results table. The eight (2M = 8) new samples C _{1 Q 5} C _{1 p} C _{1 2} , C _{1 3} , C _{1 4} , C _{1 5} , C _{1 6} , C _{1 7} are then weighted by the coefficients

IOTA, and added to the previous results and so on.

At the 2L iteration, the calculation of the samples at the output of the filtering step reaches a steady state 72, and the output samples correspond to the sum of 2L samples of the weighted inverse FFT. An example of architecture optimized for this filtering algorithm, using 2L real multipliers and 2L real adders, is described in the European patent EP 1 005 748 filed on 30/06/1998 in the names of FRANCE TELECOM and TELEDIFFUSION DE FRANCE. In particular, to take into account the part In the real world and the imaginary part of the complex samples at the output of the FFT, it is necessary to use twice as many real multipliers and adders, ie 2 • 2 real multipliers and 2 • 2L real adders.

2.4 Disadvantages of the Techniques of the Prior Art These prior art techniques have several disadvantages.

First of all, it should be noted that these techniques require a large amount of computing power, as well as a large storage capacity.

For example, filtering requires the use of additional memories, of size \ 2L - IJM. Thus, for a truncation length of the IOTA L-4 function, the optimized architecture of the filtering algorithm requires 2L - 2 = 16 real multipliers, and 2L - 2 = 16 real adders as well as a sample memory complexes of size \ 1L - Y \ M - 3,5N. It should be noted that other values of L, not exceeding the value 8, can be used. In addition, it is necessary to use an interface between the inverse Fourier transform unit and the filtering unit on the modulator side, or between the filtering unit and the direct Fourier transforming unit on the demodulator side. This interface makes it possible to store samples in a buffer memory until the arrival of a desired sample. Indeed, the filter unit can work only when it has the first sample output of the inverse Fourier transform unit, and the sample located M = N 12 samples after.

Furthermore, conventional techniques do not achieve a high flow rate, while limiting consumption. In particular, these techniques do not make it possible to achieve very high data rates, for example a bit rate of 480 Mb / s over a bandwidth of 528 MHz and 128 carriers, for the case of ultra-wideband (UWB, in English "Ultra Wide Band").

For such applications, it is possible to parallelize and "pipeliner" the data processing, to increase the flow of treatment. "Parallelism" is understood to mean the concurrent treatment of several butterflies of the same floor, and by "pipeline" the concurrent treatment of several butterflies of different floors.

However, this solution also has disadvantages, since the use of a FFT "pipeline" algorithm requires an architecture comprising as many butterflies as stages (log ₂ N), multiplied by the degree of parallelism. For example, if we consider a FFT of 4096 points pipelined on 12 floors (Iog ₂ 4096 = 12), and a parallelism of 4, the corresponding architecture requires the use of 24 complex multipliers and 48 butterflies for the implementation. implementation of the Fourier transform algorithm. A large number of arithmetic resources and memories are therefore necessary, to which the resources for filtering must be added taking into account the additional resources due to parallelism. Considering again a parallelism of 4 for the filtering (ie 4 parallel filtering units), the corresponding architecture requires the use of 64 real multipliers and 64 real adders for the implementation of the filtering algorithm.

Thus, according to this example, the modulator delivering an OFDM / OQAM / IOTA signal is based on the implementation of 160 real multipliers and 304 real adders, which requires a large calculation power and a large storage capacity. 3. Presentation of the invention

The invention proposes a new component for processing a digital signal, that is to say a discrete signal comprising a series of discrete digital values, requiring fewer arithmetic resources and memories than the components of the prior art for performing both a mathematical transformation operation of the signal between the time and frequency domains (for example a direct or inverse Fourier transform) and a filtering operation.

According to the invention, such a component comprises: a set of elementary calculation modules having connection means, and a control unit able to configure the connections of the connection means of at least a part of the elementary modules to produce at least two connection structures with said elementary modules respectively providing a mathematical transformation function of the signal between the time domain and the domain frequency, and a polyphase filtering function by a prototype function of the signal.

Thus, the invention is based on a new and inventive approach to the implementation of mathematical transformation functions between the time domain and the frequency domain and filtering in a signal processing component.

It is noted that "mathematical transformation between the time domain and the frequency domain" is understood to mean both a transformation of a digital signal from the time domain to the frequency domain, and a transformation of a digital signal from the frequency domain to the frequency domain. time domain.

The proposed technique is based on the use of a generic component, including all or part of the internal connections, which include external connections, ie inputs and / or outputs, elementary modules but also internal connections. to the elementary modules, can be modified to perform various functions including entering the modulation or demodulation of a multi-carrier signal, such as filtering or mathematical transformation functions, from the time domain to the frequency domain or vice versa.

The invention therefore makes it possible to reuse elementary modules for calculating the component to perform either filtering operations or mathematical transformation operations between the time and frequency domains.

According to a particular embodiment, the control unit is adapted to configure the connection means so as to make the two connection structures alternately. In other words, the control unit makes it possible to produce a first structure connection by configuring the external connections (inputs / outputs) and / or internal of at least some elementary modules of the set, then to achieve at least a second connection structure by reconfiguring these connections.

In a particular embodiment, the set of elementary modules forms a matrix comprising P × Q elementary modules, P and

Q respectively representing a degree of parallelism and a number of stages, the elementary modules forming the matrix being interconnected in the connection structure providing the mathematical transformation function of the signal between the time domain and the frequency domain, so as to form Q stages , each comprising P elementary modules able to perform parallel processing, and P parallel channels, each comprising Q elementary modules able to perform sequential processing.

The choice of such a structure to perform the mathematical transformation of the signal between the time domain and the frequency domain offers easy reconfiguration to achieve the filtering structure.

It is recalled that the degree of parallelism P allows simultaneous processing of several elementary modules of the same stage, and the number of stages or "pipeline depth" Q allows simultaneous processing of several elementary modules of different stages. In particular, it is possible to choose the number of stages Q and channels

P depending on the speed of treatment allowed to reach a desired flow rate. Advantageously, the structure providing the mathematical transformation function is adapted to implement a radix-2 algorithm, where i corresponds to the number Q of stages of the matrix, and the degree of parallelism P and the number of stages Q are such that that Q - log ₂ (2P).

According to an advantageous aspect of the invention, each stage of the matrix comprises at least four elementary modules.

Such a structure having several stages each comprising at least four elementary modules makes it possible to reach bit rates of the order of several hundred megahertz. In particular, such a treatment component a digital signal is well suited to provide modulation and / or demodulation of an OFDM / OQAM / IOTA type signal.

The elementary modules comprise calculation means capable of performing arithmetic operations of complex addition and / or complex multiplication. In other words, they include complex adders and / or complex multipliers.

In a particular embodiment, at least a portion of the elementary modules comprising a plurality of external connection means of the elementary module and a plurality of calculation means provided with internal connection means, the control unit is adapted to configure the connections. internal of said elementary modules, between the calculation means and the external connection means and between the calculation means themselves, to achieve the two connection structures.

Advantageously, the matrix comprises a first set of at least one stage of elementary modules comprising calculation means able to carry out only arithmetic operations of addition and a second set of at least one stage of elementary modules comprising means of calculation capable of performing arithmetic operations of multiplication and arithmetic operations of addition. In addition, the control unit is adapted to short-circuit the elementary modules of the first set and to modify the external connections and the internal connections of the modules of the second set, in order to achieve the connection structure providing the filtering function. To perform the filtering function, only modules capable of performing complex addition operations and complex multiplication operations are used by modifying the internal connections of these modules.

According to a particular characteristic of the invention, the mathematical transformation is a direct or inverse Fourier transform.

Thus, the component makes it possible to produce a structure providing a mathematical transformation function from the time domain to the frequency domain by means of a direct Fourier transformation structure providing a mathematical transformation function from the frequency domain to the time domain by means of an inverse Fourier transformation.

One could however consider using any other function of mathematical transformation of the signal between the frequency domain and the time domain, for example the direct cosine transform function, or "DCT".

According to a particular characteristic of the invention, memory means being provided for storing intermediate samples calculated by the mathematical transformation function of the signal between the time domain and the frequency domain, said memory means are also intended to feed the calculations of the function. filtering. With this, the memory means serve both memory means for storing the intermediate samples during the mathematical transformation of the signal and buffering means for feeding the filtering operation. This saves a buffer memory.

For example, the filtering function is performed from the samples resulting from the mathematical transformation of the signal between the time and frequency domains, which are stored in said memory means. These samples are then multiplied by filter coefficients corresponding, for example, to the coefficients of the prototype function IOTA, then added to the samples resulting from the mathematical transformation and the filtering determined previously, for example for a preceding symbol in the context of an OFDM modulation. .

According to a particular aspect of the invention, the control unit takes into account at least one parameter belonging to the group comprising: a type of modulation; a number of points associated with said mathematical transformation; a type of prototype function; a recovery number "L" of the prototype function. Thus, the connections of the connection means of the elementary modules depend on various parameters, which can be programmed. For example, the number of elementary calculation modules used in the structure providing the mathematical transformation function is chosen according to the number of points associated with said mathematical transformation and the signal bandwidth. Another aspect of the invention also relates to a modulation and / or demodulation device comprising a component for processing a signal as described above.

In other words, a processing component of a signal as described above makes it possible to ensure both the mathematical transformation functions of the frequency domain to the time domain and of filtering in a modulation device, and / or the inverse filtering and mathematical transformation functions from the time domain to the frequency domain in a demodulation device.

Thus, such a modulation device is adapted to produce a connection structure providing a mathematical transformation function of the signal from the frequency domain to the time domain, and a connection structure providing a filtering function.

A demodulation device is adapted for producing a connection structure providing a mathematical transformation function of the signal from the time domain to the frequency domain, and a connection structure providing a filtering function.

Yet another aspect of the invention relates to equipment for transmitting and / or receiving a signal comprising a modulation and / or demodulation device as above. Such transmission equipment is particularly suitable for implementing a modulation of a digital signal. This is for example a base station, or a terminal type radiotelephone, laptop, personal assistant type PDA (in English "Personal Digital Assistant"), etc..

Reception equipment is adapted to implement a demodulation of a digital signal. This is for example a radiotelephone type terminal, laptop, personal assistant PDA (in English "Personal Digital Assistant"), etc..

In another embodiment, the invention relates to a method of modulating or demodulating a digital signal.

Such a method comprises: a step of configuring the connections of the connecting means of at least a part of a set of elementary calculation modules, able to define at least two connection structures with said elementary modules respectively providing a transformation function mathematical signal between the time domain and the frequency domain, and a signal filtering function; a step of mathematical transformation of the signal between the time domain and the frequency domain, according to a first connection structure of said set; a polyphase filtering step by a prototype function of the signal according to a second connection structure of said set.

Such a method is for example implemented in the modulation and / or demodulation device described above. Another aspect of the invention also relates to a computer program comprising program code instructions for implementing the steps of the modulation or demodulation method described above, when the program is executed by the computer.

Such a program can be stored in or transmitted by a data carrier.

Yet another aspect of the invention thus relates to a computer-readable recording medium on which the computer program is recorded.

This may be a hardware storage medium, for example a CD-ROM, a magnetic diskette or a hard disk, or a medium transmissible, such as an electrical, optical or radio signal.

For example, the computer program can be downloaded from a communication network.

4. List of Figures Other features and advantages of the invention will appear more clearly on reading the following description of a particular embodiment, given as a simple illustrative and non-limiting example, and the accompanying drawings, among which: Figures 1 and 2 respectively illustrate a modulation chain and a demodulation chain according to the prior art; Figure 3 shows the radix-2 algorithm for an eight point FFT; FIG. 4 illustrates a butterfly operation according to the radix-2 algorithm; FIG. 5 proposes an architecture for producing an FFT; Figure 6 shows a pipelined architecture for a 256-point FFT

3 using the radix-2 algorithm; FIGS. 7A to 7C illustrate the filtering algorithm according to the prior art; FIG. 8 illustrates a processing component of a signal according to the invention; FIG. 9 presents the main steps of the modulation and / or demodulation method according to the invention; FIGS. 10A and 10B illustrate a first example of connection structures to ensure a mathematical transformation function

(Figure 10A) and filtering (Figure 10B); and Figures HA and HB illustrate a second example of connection structures to provide a mathematical transformation function

(FIG. 1A) and filtering (FIG. 1B), FIGS. 12A and 12B illustrate the internal structure of an elementary module used in the component of FIGS. 1OA and 1OB as well as that of FIGS. HA and HB, configured for a connection structure providing a mathematical transformation function (FIG. 12A) and for a connection structure providing a filtering function (FIG. 12B).

5. DESCRIPTION OF AN EMBODIMENT OF THE INVENTION 5.1 GENERAL PRINCIPLE The general principle of the invention is based on the use of a single component making it possible to ensure both the mathematical transformation functions of the frequency domain towards the time domain and filtering on the modulation side, and / or the inverse filter functions and the mathematical transformation of the time domain to the frequency domain on the demodulation side.

In other words, by repeating FIGS. 1 and 2, the invention proposes a component grouping the steps of mathematical transformation 14, standby 15 and filtering 16, or filtering stages 22, holding 23 , and mathematical transformation 24. Considering, for example, advanced modulation of

OFDM / OQAM associated with an IOTA waveform, the invention proposes a generic component carrying out the two main operations for the synthesis of the OFDM / OQAM signal, namely the fast Fourier transform and the multiphase filtering by the IOTA prototype function, instead of two separate components respectively performing each of the two functions as proposed in conventional architectures.

From the outset, it will be noted that by the expression "fast Fourier transform", also denoted FFT, is meant either a direct fast Fourier transform (used for the demodulation), or an inverse fast Fourier transform (used for the modulation).

Thus, the proposed solution defines a new architecture: for performing a modulation or demodulation with multiple carriers comprising any number of sub-carriers (multiple of 2), - to achieve a very high speed, of the order of many hundreds of megahertz for an OFDM / OQAM / IOTA signal, and operating at low power, using a minimum of hardware resources (ie arithmetic operators, memories, etc.). To do this and as illustrated in FIG. 8, a component 81 for processing a digital signal according to the invention comprises a set 82 of elementary calculation modules, denoted by BF, and a control unit 83 able to configure the connections of the means. connecting at least a portion of the elementary modules to realize at least two connection structures with the elementary modules, so as to respectively provide a mathematical transformation function of the signal between the time domain and the frequency domain, and a filtering function of the signal.

More precisely, the mathematical transformation operation between the time and frequency domains is based on a semi-pipelined structure, which makes it possible to stop the dependence on the number of stages required according to the value of the number of points of the mathematical transformation. In addition, this structure is always compatible with a certain degree of parallelism, for example of at least 4.

The filtering operation reuses for its part at least some of the elementary calculation modules used for the mathematical transformation operation.

The structures respectively providing the functions of mathematical transformation and filtering are therefore performed alternately, in other words in turn.

Elementary modules are thus used to perform the multiplication operations during the mathematical transformation and during the filtering.

Such a signal processing component may in particular be integrated in a modulation device, or a demodulation device.

A modulation device is particularly adapted to modulate a data signal to deliver a multicarrier signal, alternately realizing a connection structure providing a mathematical transformation function. signal from the frequency domain to the time domain, and a connection structure providing a filtering function.

A demodulation device is in turn adapted to demodulate a multicarrier signal for recovering a data signal, alternately realizing a connection structure providing a filtering function, and a connection structure providing a mathematical transformation function of the signal of the signal. time domain to the frequency domain.

The invention also relates to a method for modulating or demodulating a signal as illustrated in FIG. 9, comprising: a configuration step 91 of the connections of the connection means of at least a part of a set of modules elementary calculating elements, able to define at least two connection structures with said elementary modules respectively providing a mathematical transformation function of the signal between the time domain and the frequency domain, and a signal filtering function; a step of mathematical transformation of the signal between the time domain and the frequency domain 92, according to a first connection structure of the set of elementary modules; a step of filtering the signal 93 according to a second connection structure of the set of elementary modules.

A modulation and / or demodulation device as presented above may comprise a processing unit, equipped for example with a microprocessor and driven by a computer program comprising program code instructions for implementing the steps of the program. method of modulation and / or demodulation described above when executed by the device. This program can be stored in or transmitted by a data carrier. This may be a hardware storage medium, for example a CD-ROM, a magnetic diskette or a hard disk, or a transmissible medium such as an electrical, optical or radio signal. A processing component of a signal according to the invention therefore allows to provide at least two distinct functions with the elementary modules, among which at least one mathematical transformation function between the time and frequency domains and at least one filtering function, while retaining both the advantages of the pipeline and the parallelism. It will be recalled that "parallelism" means the concurrent processing of several elementary modules of the same stage of the set of elementary modules, and "pipeline" the concurrent processing of several elementary modules of different stages. In particular, it is considered that all the elementary calculation modules form a matrix. 5.2 Examples of realization

Two embodiments of the invention are described below, in the context of advanced OFDM modulation of the OQAM type, implementing the IOTA prototype function.

It is understood that the invention is not limited to this type of modulation, and can also be applied to other multicarrier modulations, and in particular to conventional modulations, for example of the OFDM / QAM type, which do not filtering.

In addition, other prototype functions can be used, such as the Nyquist function, the Hermite function or any new waveform based on the OFDM / OQAM modulation.

A) First example: degree of parallelism equal to 4

Depending on the speed of processing allowed to reach the desired rate, the signal processing component includes different degrees of parallelism and "pipeline" (ie, serialization). For example, to reach a bit rate of several hundred megahertz for an OFDM / OQAM / IOTA signal and a mathematical transform size between 2 and 4096 points (and thus 12 stages), the component can be realized with a parallelism of at least 4.

FIGS. 10A and 10B illustrate two connection structures with the elementary modules of a set 101 of elementary calculation modules forming a matrix, denoted BF1, BF2,... BF12, for a parallelism of 4, and a degree of pipeline (that is to say a number of stages in series) of 3, modulation side. More precisely, FIG. 10A illustrates a connection structure making it possible to provide a mathematical transformation function from the frequency domain to the time domain if it is placed on the modulation side, for example an inverse Fourier transform. FIG. 1B illustrates a connection structure making it possible to provide a filtering function, for example by the IOTA prototype function.

Thus, the signal processing component comprises a matrix 101 of elementary calculation modules, comprising P × Q elementary modules for carrying out the mathematical transformation and filtering operations, with P the degree of parallelism and Q the number of modules. stages of the matrix (also called depth or degree of the pipeline), such as g = log ₂ (2P), and manipulating 2P data at once at the input of the component. In other words, the connection structure is composed of Q stages each comprising P elementary modules able to perform parallel processing, and P parallel channels, each comprising Q elementary modules able to perform sequential processing.

For example, for FIGS. 10A and 10B, there is a parallelism P = 4 and a pipeline of Q-3, defining an array of 12 elementary calculation modules, and eight data are manipulated at a time at the input of the component ( eight inputs on the first stage of the matrix comprising the elementary modules BF1, BF2, BF3 and BF4, eight inputs on the second stage of the matrix comprising the elementary modules BF5, BF6, BF7 and BF8, and eight inputs on the third stage of the matrix comprising the elementary modules BF9, BF10, BFI 1 and BF12).

The elementary modules BF1 to BF4 of the first stage comprise simple complex adders, while the elementary modules BF5 to BF 12 of the last two stages comprise multipliers, or "multipliers", complex and complex adders. The control unit includes short-circuit means (102) of at least one stage of the matrix, hopefully the first stage comprising the adders of the modules BF1 to BF4. In addition, it is arranged to modify the external connections and the internal connections of the modules BF5 to BF12 of the two last stages, comprising multipliers and adders, to realize either the connection structure ensuring the mathematical transformation function of the signal between the domains. time and frequency, ie the connection structure providing the filtering function. Thus, the architecture is modular and the matrix can be used in whole or in part by shorting here a stage of the matrix during the FFT, which allows to obtain several degrees of parallelism or pipeline depth.

Such an architecture is particularly effective with the radix-2 * type algorithms, for i ranging from 1 to 4. The case i-1 corresponds to the radix-2 algorithm. With regard to these radix-2 algorithms, it is recalled that according to the value of i, the matrix of the elementary modules must comprise i stages, that is to say a degree of pipeline equal to i.

The inverse Fourier transform operation of FIG. 10A illustrates the case of the radix-2 frequency interleaving algorithm. However, it is understood that time interleaving (dual operation of the frequency interleaving), as illustrated for example in relation to FIG. 3, can also be used. To do this, it suffices to invert the inputs and outputs of the elementary modules, by correspondingly modifying the rotation factors.

The matrix 101 of elementary modules is interconnected, according to this exemplary embodiment, while respecting the data flow of a radix-2 FFT. Each elementary module BFi, l ≤ i ≤ 12, therefore implements a butterfly, as illustrated in FIG.

The Fourier transformation operation also implements two memories of size N, that is to say the size of the FFT, denoted 103 and 104. These memories are of RAM type, in English "random access memory" , in French "Mémoire vive". They serve both as memories to store the intermediate samples calculated by the Fourier transformation and buffer operation to feed the filtering operation with the samples from the Fourier transform. A memory of filtering coefficients, not shown in the figure, (for example a ROM or a FIFO, in English "first in, first out", in French "first in, first out") of size {2L - ÙM dependent the value of the truncation length L, with M = NI l, is also used, in particular to store the weighting coefficients of the prototype function. If a different prototype function of the IOTA function is used, for example a Nyquist function, or the Hermite function, it is necessary to store the coefficients of this prototype function in this ROM.

More precisely, the two memories 103 and 104 operate alternately. The use of two memories according to the invention allows a direct write of the results in the right order, not requiring a replay and a reorganization of the results as in the prior art.

Before the calculation algorithm of the FFT begins, it is expected that the N points of the FFT are stored in one of the two memories, for example the memory 103.

Therefore, this memory 103 is used to calculate the FFT, while the other memory 104 is used to store the N points of the next FFT. Thus, the two memories become active for the processing of the FFT in turn.

Once the N points ready to be processed stored in the memory 103, the points are read in the memory 103 in a very precise sequence that corresponds to the data flow (in English "dataflow") of the FFT radix-2 algorithm, as described in the "Designing pipeline FFT processor for OFDM (demodulation) of S. He and M. Torkelson (International Symposium on Signals, Systems, and Electronics, pp. 257-262, Sept. 29 - Oct. 2, 1998) The points are processed by the elementary calculating modules of the matrix 101 and rewritten in the memory 103, at the same addresses as during the reading, This procedure is implemented continuously, until the complete realization of the FFT.

Once the set of FFT samples has been calculated, the control unit bypasses the first stage (and thus modifies the configuration of the external connections of the modules BF1 to BF4) and modifies the configuration of the external connections and that of the connections. internal connections of the elementary modules BF5 to BF12 of the matrix 101, defining a second connection structure with the same elementary modules BFi, l ≤ j ≤ 12, to provide a filtering function. Such a structure is illustrated in particular in FIG.

The filtering consists in multiplying the samples at the output of the inverse Fourier transform memorized in one of the two memories of the FFT, for example the memory 103, by the IOTA coefficients stored in the filter coefficient memory (not shown), and adding up the results at the results of the filtering of the preceding symbol stored in a filter memory 105. Thus, multiplexers make it possible to select the IOTA coefficients, the samples of the result of the FFT stored in the memories 103 or 104, and the results of the previous filtering in filter memories 105.

More precisely, during filtering, each elementary module used for filtering becomes an independent calculation unit, performing basic operations for filtering. In other words, we use the arithmetic operations offered by at least some elementary modules, here those comprising adders and complex multipliers, for the implementation of the filtering function.

For example, the filtering architecture is based on the architecture proposed in the aforementioned European patent EP 1 005 748. Thus, there are connections between the filter memories 105 and each of the elementary modules, for example BFi, 5 ≤ i ≤ 12, used for filtering. For example, the filter memories 105 comprise three memories 1051, 1052 and 1053 of size N, and a memory 1054 of size N 12.

The elementary modules of the component implemented for the mathematical transformation are therefore reused for filtering. In particular, we can note only the elementary modules necessary for real-time modulation processing are used.

The modules BF1 to BF4, used only in the structure ensuring the mathematical transformation of the signal, include inputs / outputs, so the connections are configurable.

The modules BF5 to BF12, used both in the structure ensuring the mathematical transformation of the signal and in the structure providing the filtering, comprise inputs / outputs whose connections are configurable and also configurable internal connections. Finally, each of these elementary modules BF5 to BF12 comprises a plurality of external connection means of the elementary module, in this case input ports and output ports, and a plurality of calculation means corresponding to different mathematical operators. (multipliers, adders) having internal connection means for connecting the mathematical operators to each other as well as to the input ports and the output ports. The control unit of a basic module BFi (with 5 <; <12) is adapted to configure, in other words to modify, the internal connections of this basic module BFi in order to realize either the connection structure ensuring the mathematical transformation, either the connection structure providing the filtering. By "internal connections" of an elementary module, we mean

the connections between, on the one hand, the calculation means and, on the other hand, the input ports and the output ports,

- as well as the interconnections between the calculation means themselves.

By way of illustrative example, FIGS. 12A and 12B show the internal architecture of a BFi module comprising complex multipliers and complex adders, in accordance with an elementary module BF ₁ with

<<<12 used in the component shown in FIGS. 10A and 10B. In FIG. 12A, the BF module ₁ is configured for the connection structure providing the Fourier transform function. In FIG. 12B, the same BF module ₁ is configured for the connection structure providing the filtering function. This BF module ₁ comprises, a plurality of input ports (left in the figures), a plurality of output ports (right in the figures), adders, multipliers, subtracters and multiplexers. Note that the internal connections of the BF module ₁ shown in Fig. 12A differ from those shown in Fig. 12B.

In FIG. 12A, the internal connections of the BFi module form a butterfly in order to carry out complex addition and complex subtraction operations between two complex samples supplied as input, and denoted by Xi (n) _ree i, Xi (n) _ima ginary X2 (n) _ree i and X2 (n) _ima g _inary, as well as complex multiplication operations by the rotation factors (that is to say, the coefficients of the Fourier transform) rated w ^ _ml, w ^ _{mig ^} , w ^ _ml , w ^ _mugmim . The output samples are denoted y ^y , ^L U \ /) real, y ^y , ^L U \) / imaginary, y ^, ^z U \) / real, y ^, ^z U \) / imaginary

In FIG. 12B, the internal connections of the BFi module are adapted to perform multiplications of the samples of the Fourier transform, stored in the memories 103 and 104 and denoted C _{k + ιM} real, C _{k + ιM} imag, by the coefficients of the function of IOTA, denoted iOTA _{k + ιM} , and to add the results to the results of the preceding filtering operation, denoted F _in _{k + ιM} real, F _in _{k + ιM} imag, with 0 ≤ / ≤ 3. filtering output results are noted

_{F_out k + ιM} real, F _{_out k + ιM} imag, with 0 <i <3. Thus, it can be seen that a modulation and / or demodulation device comprising a signal processing component according to this exemplary embodiment of the invention requires only 64 real multipliers and 80 real adders for a parallelism of 4, whereas according to the techniques of the prior art, a modulator delivering an OFDM / OQAM / IOTA signal is based on the implementation of 160 real multipliers and 304 real adders.

B) Second Example: Degree of Parallelism Equal to 8 Hereinafter, with reference to FIGS. HA and HB, two connection structures are described with the elementary modules of a set 111 of elementary calculation modules forming a matrix, denoted BF1, BF2. , ... BF32, for a parallelism of 8, and a degree of pipeline (i.e., number of stages) of 4, modulation side.

In other words, the matrix 111 of elementary calculation modules comprises P χ <2 = 8 χ 4 = 32 elementary modules making it possible to carry out the mathematical transformation and filtering operations, with P the degree of parallelism and Q the number of stages of the matrix.

More precisely, FIG. 6A illustrates a connection structure making it possible to provide a mathematical transformation function from the frequency domain to the time domain, for example an inverse Fourier transform. Figure HB illustrates a connection structure for providing a filter function, for example by the prototype function IOTA.

Consider for example a 128-point FFT, that is to say requiring log ₂ 128 = 7 stages, and using a degree of parallelism of 8 manipulating sixteen data at a time at the input of the component (for example sixteen inputs on the first stage of the matrix comprising the elementary modules BF1 to BF8, sixteen inputs on the second stage of the matrix comprising the elementary modules BF9 to BF 16, sixteen inputs on the third stage of the matrix comprising the elementary modules BF17 to BF24, sixteen inputs on the fourth stage of the matrix comprising the elementary modules BF25 to BF32). In the particular example described here, the elementary modules of the first two stages, referenced BF1 to BF16, comprise only complex adders, whereas the elementary modules of the last two stages, referenced BF17 to BF32, comprise complex multipliers and complex adders. . We therefore consider eight successive sequences of sixteen data to cover the 128 points of the FFT (128 / 16-8).

To achieve the seven stages of the FFT at 128 points with a pipeline degree of 4, it is possible to consider three stages of the matrix on

3 which uses the algorithm radix-2, and four stages of the matrix on which

4 we use the radix-2 algorithm. Thus, it is possible to short-circuit (112) the first stage of the matrix comprising the elementary modules BF1 to BF8, by entering directly at the second stage of the matrix comprising the elementary modules.

3 BF9 to BF 16, and use the radix-2 algorithm to perform the first three stages of the FFT. The last four floors of the FFT are made using

4 the radix-2 algorithm by entering this time directly at the first stage of the matrix.

As described above with reference to FIG. 10A, 128 points of the FFT are first stored in a first memory 113, of size N-128.

The eight sequences of sixteen points are then read one after another at each clock stroke.

As indicated above, one enters directly on the second stage of the matrix thanks to the short-circuit 112, and one uses the algorithm radix-2. Once the first sequence Seq. 1 has reached the last stage of the matrix (fourth stage), we receive the results of the other seven sequences, one after another at each clock stroke. The sequences are then stored in the memory 113, at the same address as during the reading.

Thus, the addresses read in the memory 113, for addresses ranging from 0 to 127 points, are for the eight sequences:

Seq. 1) 0, 8, 16, 24, 32, ..., 104, 112, 120 Seq. 2) 1, 9, 17, 25, 33, ..., 105, 113, 121 Seq. 3) 2, 10, 18, 26, 34, ..., 106, 114, 122 Seq. 4) 3, 11, 19, 27, 35, ..., 107, 115, 123 Seq. 5) 4, 12, 20, 28, 36, ..., 108, 116, 124

Seq. 6) 5, 13, 21, 29, 37, ..., 109, 117, 125 Seq. 7) 6, 14, 22, 30, 38, ..., 110, 118, 126 Seq. 8) 7, 15, 23, 31, 39, ..., 111, 119, 127

The first three floors of the FFT are then realized, and it remains only to calculate the last four floors of the FFT. These last four floors of the FFT correspond to eight FFTs of sixteen points. We read the eight sequences of sixteen points one after the other, each clock stroke.

As indicated above, we enter at the level of the first floor of the

4 matrix, and we use the radix-2 algorithm. So we take sixteen points at a time, one sequence after another at each clock stroke, and we go through the four stages of the matrix.

Thus, the addresses read in the memory 113, for addresses ranging from 0 to 127 points, are for the eight sequences: Seq. 1) 0 to 15

Seq. 2) 16 to 31

Seq. 3) 32 to 47

Seq. 4) 48 to 63

Seq. 5) 64 to 79 Seq. 6) 80 to 95

Seq. 7) 96 to 111

Seq. 8) 112 to 127

The results are then stored in the memory 113, at the same address as during the reading. The memory 113 then includes the result of the 128-point FFT. A second memory 114, also of size N = 128, makes it possible to memorize the N points of the following FFT.

It is recalled that although FIG. 6A illustrates a radix-2 algorithm according to a frequency interleaving, the invention is not limited to this type of interleaving, and also applies to time interleaving.

Once all the samples of the FFT have been calculated and stored in the FFT memories 113, 114, the control unit modifies the connection configuration of the connection means of at least a portion of the elementary modules of the matrix 111, defining a second connection structure with the same elementary modules BFi, l ≤ i <32, to ensure a filter function. Such a structure is illustrated in FIG. As can be seen in this figure HB, in the filtering structure, the modules BF1 to BF16 are short-circuited whereas the external connections and the internal connections of the modules BF17 to BF32 are modified, reconfigured, in a similar way to what has been described with reference to Figure 1OB, to provide the filtering function.

The modules BF1 to BF16, used only in the FFT structure, include input ports and output ports whose external connections are configurable.

Modules BF17 to BF32, used in both the FFT structure and the filtering structure, include input and output ports with configurable external connections as well as configurable internal connections. Each of these elementary modules BFi with 17 ≤ i ≤ 32 conforms to the elementary module shown in FIGS. 12A and 12B in the FFT structure and in the filter structure respectively. As indicated above, the filtering consists of multiplying the samples at the output of the inverse Fourier transform stored in the storage means 115, by the IOTA coefficients stored in a not represented memory, and adding the results to the results of the filtering of the symbol. Previously stored in a filter memory 115. Thus, multiplexers allow to select the IOTA coefficients, the samples of the result of the FFT stored in the memories 113 or 114, and the results of the previous filtering in filter memories 115.

It will be noted that, as before, the memories 113 and 114 are used to store intermediate samples of the FFT and to act as buffers in order to feed the calculations of the filtering function. There are in particular connections between the filter memories 115 and each of the elementary modules, for example BFi for 17 ≤ i ≤ 32, used for filtering. For example, the filter memories 115 comprise three memories 1151, 1152 and 1153 of size N, and a memory 1154 of size N 12. The filtering procedure is as follows: 1. reading the samples at the output of the IFFT in one of the two memories of the FFT, for example the memory 113;

2. multiplication of these samples by the IOTA coefficients, stored in a ROM not shown; 3. reading the samples of the preceding symbol in the filter memory 115 and addition with the results of step 2; 4. writing the summation result in the filter memory to the same addresses as when reading the samples of the previous symbol in step 3. The elementary modules of the component implemented for the mathematical transformation are therefore reused for filtering; between the time and frequency domains. In particular, it can be noted that only the elementary modules necessary for real-time modulation processing are used.

It can be seen that a modulation and / or demodulation device comprising a signal processing component according to the invention only requires 128 real multipliers and 192 real adders for a parallelism of 8, whereas according to the techniques of FIG. In the prior art, a modulator delivering an OFDM / OQAM / IOTA signal is based on the implementation of 160 real multipliers and 304 real adders for a parallelism of 4. Thus, the processing component of a signal according to the invention makes it possible to achieve a very high processing rate (of the order of a few hundred megahertz), while remaining low consumption, because of the decrease in the number of arithmetic operators used.

The proposed component thus allows a great flexibility and a great power of computations, thanks to a architecture resting on the parallelism and the pipeline, and the reuse of the same elementary modules to realize different functions as a mathematical transformation between the time and frequency domains or a filtering.

The size of the Fourier transform can of course be greater than 4096 points. In the embodiment described, it is limited by the size (N) memories (103 and 104, 113 and 114). 5.3 Demodulator

A component according to the invention can also be used in a demodulation device, replacing the inverse Fourier transform and filter functions by inverse filtering and direct Fourier transform functions.

Such a component comprises the same elements as previously described, namely a set of elementary calculation modules, and a control unit able to configure the connections of the ports of at least a portion of the elementary modules to achieve at least two connection structures with said elementary modules respectively providing a function of mathematical transformation of the signal between the time and frequency domains (for example a direct FFT), and a signal filtering function (for example inverse polyphase filtering). It is therefore possible to use the same component to carry out the direct and inverse Fourier transformation operations for example.

For example, as for the filtering algorithm and the mode of operation of the architecture during transmission filtering, the filtering algorithm and the mode of operation of the architecture at the reception may be based on the structure presented in FIG. European patent EP 1 005 748 cited above.

It may also be noted that, unlike the broadcast, reception filtering requires only 2 • 2 (L-1) real adders (for the real and imaginary part) instead of the 2 • 2 L real adders on transmission.

In the foregoing description, the mathematical transformation function of the signal between the time domain and the frequency domain is the Fourier transform. Alternatively, another function of mathematical transformation of the signal between the time domain and the frequency domain, for example a direct cosine transform, could be used.

Claims

1. Component (81) for processing a digital signal, characterized in that it comprises: a set (101; 111) of elementary calculation modules having connection means, and a control unit (83) adapted to configuring the connections of the connecting means of at least a portion of the elementary modules to achieve at least two connection structures with said elementary modules respectively providing a mathematical transformation function of the signal between the time domain and the frequency domain, and a function of polyphase filtering by a prototype function of the signal.

2. Component (81) according to claim 1, characterized in that the control unit is adapted to configure the connection means so as to make said connection structures alternately.

3. Component (81) according to any one of claims 1 and 2, characterized in that the set of elementary modules form a matrix comprising P x Q elementary modules, P and Q respectively representing a degree of parallelism and a number of modules. stages, the elementary modules forming the matrix being interconnected in the connection structure providing the function of mathematical transformation of the signal between the time domain and the frequency domain so as to form Q stages, each comprising P elementary modules able to operate parallel treatments, and P parallel channels, each comprising Q elementary modules capable of operating sequential treatments.

The component (81) according to claim 3, wherein the structure providing the mathematical transformation function is adapted to implement a radix-2 algorithm, where i corresponds to the number Q of stages of the matrix, and the degree of parallelism P and the number of stages Q are such that Q - log ₂ (2P).

5. Component (81) according to any one of claims 1 to 4, characterized in that, at least a portion of the elementary modules comprising external connection means, and

a plurality of calculation means provided with internal connection means, the control unit is adapted to configure the internal connections of said elementary modules, between the calculation means and the external connection means and between the calculation means themselves. to realize the two connection structures.

6. Component (81) according to one of claims 3 to 5, wherein the matrix comprises a first set of at least one stage of elementary modules comprising calculation means capable of performing only arithmetic operations of addition and a second set of at least one stage of elementary modules comprising calculation means able to perform arithmetic multiplication operations and arithmetic addition operations, and the control unit is adapted to short-circuit the elementary modules of the first together and to modify the external connections and internal connections of the modules of the second set to achieve the connection structure providing the filtering function.

7. Component according to any one of claims 1 to 6, characterized in that said mathematical transformation is a direct or inverse Fourier transform.

8. Component (81) according to any one of claims 1 to 7, wherein storage means (103, 104) being provided for storing intermediate samples calculated by the mathematical transformation function of the signal between the time domain and the frequency domain, said storage means (103, 104) are also adapted to act as buffer memory means for feeding the calculations of the filtering function.

9. Component (81) according to any one of claims 1 to 8, characterized in that said control unit (83) takes into account at least one parameter belonging to the group comprising: - a type of modulation; a number of points associated with said mathematical transformation; a type of prototype function; a recovery number of the prototype function.

Modulation device comprising a component (81) for processing a digital signal according to claim 1, adapted to produce: a connection structure providing a mathematical transformation function of the signal from the frequency domain to the time domain, and a structure connection providing a polyphase filtering function by a prototype function.

11. Demodulation device comprising a component (81) for processing a digital signal according to claim 1, adapted to provide: a connection structure providing a mathematical transformation function of the signal from the time domain to the frequency domain, and a structure connection providing a polyphase filtering function by a prototype function.

Equipment for transmitting a signal comprising a modulation device according to claim 10.

13. Equipment for receiving a signal comprising a demodulation device according to claim 11.

14. Process for processing a digital signal, characterized in that it comprises: a step of configuring (91) connection means connections of at least part of an assembly (101; 111) of elementary modules computer, capable of defining at least two connection structures with said elementary modules respectively providing a mathematical transformation function of the signal between the time domain and the frequency domain, and a filtering function of the signal; a step of mathematical transformation of the signal between the domain temporal and frequency domain (92), according to a first connection structure of said set (101; 111); a polyphase filtering step by a prototype function of the signal (93) according to a second connection structure of said set (101; 111).

15. Computer program, characterized in that it comprises program code instructions for implementing the steps of the method according to claim 14 when the program is executed by the computer.

Computer-readable recording medium on which the computer program according to claim 15 is recorded.