WO2008143622A1 - Système et procédé pour concevoir et mettre en œuvre des produits de traitement de paquet - Google Patents

Système et procédé pour concevoir et mettre en œuvre des produits de traitement de paquet Download PDF

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Publication number
WO2008143622A1
WO2008143622A1 PCT/US2007/012583 US2007012583W WO2008143622A1 WO 2008143622 A1 WO2008143622 A1 WO 2008143622A1 US 2007012583 W US2007012583 W US 2007012583W WO 2008143622 A1 WO2008143622 A1 WO 2008143622A1
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Prior art keywords
packet
output
header
packet processing
input
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PCT/US2007/012583
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English (en)
Inventor
Vispi Cassod
Anthony Dalleggio
Amine Kandalaft
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Modelware, Inc.
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Priority to PCT/US2007/012583 priority Critical patent/WO2008143622A1/fr
Publication of WO2008143622A1 publication Critical patent/WO2008143622A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Definitions

  • the present invention relates to digital component design and implementation systems and, more particularly, to a system and method for designing and implementing packet processing products.
  • Computer-based communications are dominated by the transmission of packets of data.
  • a packet contains a payload, i.e., a portion of an overall data message, surrounded by a number of header bits or bytes, that are used to insure that the payload is transmitted and received without error.
  • the header bits or bytes can be divided into a number of fields designating commands, responses, packet characteristics, etc.
  • the fields can take on one or more values depending on the particular protocol used. Some protocols are custom-designed, while others, such as asynchronous transfer mode (ATM) or Transmission Control Protocol/Internet Protocol (TCP/IP), are standardized.
  • ATM asynchronous transfer mode
  • TCP/IP Transmission Control Protocol/Internet Protocol
  • NPU network processing unit
  • the present invention relates to a system and method for designing and implementing packet processing products, wherein a user can create instructions for building a packet processing integrated circuit.
  • the system includes a user interface for allowing a user to define a desired packet processing algorithm by defining a plurality of discrete, packet processing blocks, each of the blocks corresponding to a portion of the desired packet processing algorithm, as well as connections between the plurality of packet processing blocks.
  • the system processes the plurality of packet processing blocks and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm.
  • the list of instructions can be delivered to a customer, or the customer can be provided with an integrated circuit constructed using the list of instructions.
  • the customer can also be provided with a NETLIST generated using said list of instructions.
  • the packet processing blocks of the present invention include a Packet Processing Unit (PPU) 1 a Packet Modification Unit (PMU), and a Decision and Forwarding Unit (DFU).
  • the PPU includes functionality for extracting a header of a packet; for pointing to a portion of the header of a predetermined width using a predetermined index of a bit location in the header; for comparing the data represented by the portion of the header with at least one predetermined value; and for declaring a match when the result of the comparison is true.
  • a variation of a PPU, called a PPUX includes functionality for accessing an external Content- Addressable Memory (CAM) or Random-Access Memory (RAM).
  • CAM Content- Addressable Memory
  • RAM Random-Access Memory
  • the PMU includes functionality for extracting a packet; pointing to a portion of the packet of a predetermined width using a predetermined index of a bit location in the packet; and modifying the portion of the packet.
  • a packet can be modified in one of three ways: deletion, insertion, or overwriting a portion of the packet.
  • the DFU can perform one of drop, queue, and forwarding operations on packets coming from at least one PPU, PPUX, or PMU.
  • the PPU, PPUX, PMU, and DFU can be programmed by an external microprocessor.
  • FIG. 1 is a flowchart showing a process according to the present invention for designing a packet processing product
  • FIG. 2A is a screen shot of a window in a graphical user interface (GUI) according to the present invention for choosing a type of packet processing block to be configured;
  • GUI graphical user interface
  • FIG. 2B is a screen shot of a window in a graphical user interface (GUI) for selecting configuration parameters for generating a Packet Processing Unit (PPU) of the present invention
  • GUI graphical user interface
  • FIG. 2C is a screen shot of a window in a graphical user interface (GUI) for selecting configuration parameters for generating a Packet Modification Unit (PMU) of the present invention
  • FIG. 2D is a screen shot of a window in a graphical user interface (GUI) according to the present invention for selecting configuration parameters for generating a Decision and Forwarding Unit (DFU) of the present invention;
  • GUI graphical user interface
  • FIG. 3 is a block diagram of a plurality of packet processing blocks according to the present invention for designing a packet processing product
  • FIG. 4 is a block diagram showing, in greater detail, a Packet Parsing Unit (PPU) of the present invention
  • FIG. 5 is a block diagram showing, in greater detail, a Packet Parsing Unit with an external interface to a CAM/RAM (PPUX) of the present invention
  • FIG. 6 is a block diagram showing, in greater detail, a Packet Modification Unit (PMU) of the present invention.
  • PMU Packet Modification Unit
  • FIG. 7 is a block diagram showing, in greater detail, the Decision and Forwarding Unit (DFU) of the present invention.
  • FIG. 8 is a block diagram showing a sample packet processor design for determining the queuing precedence of a VLAN/non-VLAN frame.
  • the present invention allows a user to design packet processing products using a high-level programming language which generates a NETLIST for generating a hardware design specification of a digital circuit.
  • a NETLIST describes the connectivity of an electronic design.
  • the design process begins at step 1 , wherein a set of user requirements and specifications are received, which may be in the form of a packet parsing architecture or a packet parsing and classification algorithm. Typically, these requirements are in the form of a text description of the system to be generated.
  • the description is translated by the user or provider into a textual or graphical design using packet processing blocks which include Packet Parsing Units (PPU), Packet Parsing Units with an external interface to a CAM/RAM (PPUX) 1 Packet Modification Units (PMU), and Decision and Forwarding Units (DFU), which will be described hereinbelow with reference to FIGS. 3-7.
  • PPU Packet Parsing Unit
  • PPUX Packet Parsing Units with an external interface to a CAM/RAM
  • PMU Packet Modification Units
  • DFU Decision and Forwarding Units
  • step 2 if the customer needs a firewall that accepts TCP packets and rejects UDP packets, then three PPUs and one DFU are required.
  • One of the PPUs is devoted to determining a source IP address; a second PPU is devoted to extracting a destination IP address; and a third PPU is devoted to distinguishing between TCP and UDP packets.
  • the three PPUs are connected in parallel (since the information can be extracted simultaneously from the same packet), and the "match" outputs of the PPUs (to be described with reference to FIG. 4) and a source packet is forwarded to a DFU.
  • the DFU takes each match input and the packet and makes a decision: If the packet is a TCP packet and the source and destination addresses are allowed, then the packet is passed on, otherwise the packet is to be dropped. Thus, in step 2, the user can select the required number and combination of packet processing blocks to be used in the design.
  • the packet processing block requirements including their required inputs and outputs, are entered into a connection document, which can be a text based EXCELTM spreadsheet or a VISIOTM block diagram. Typical inputs to the connection document include entries for each PPU and DFU block, which may include an index representing the point of entry into a packet to be processed, and whether a lookup in an internal table of data in a PPU is required.
  • packet processing blocks e.g., each PPU and DFU
  • Configuring a packet processing block involves taking a "default" packet processing block file, such as a generic PPU or DFU file, and modifying portions of it and setting variables within each file.
  • Code for the packet processing blocks to be described in FIGS. 4-7 (written in pseudo-code) can be found in Appendices A-E and G-L attached hereto.
  • the pseudo-code for the PPU calls code found in the following appendices: a file for describing a generic header extraction block called a Hardware Lookup Unit (HLU) (see Appendices D and K), and a file for describing a generic Match/Lookup Unit (MLU) (see Appendices E and L). Both the HLU and MLU will be described hereinbelow as part of the description of the PPU.
  • the packet processing blocks are implemented in a hardware design language (HDL) which models digital circuits, with gates, flip flops, counters, and other logic in a C- like software language.
  • HDL hardware design language
  • the "pruning" process can be performed by manually copying and editing a maximally configured processing block file, or by applying a preprocessor in the form of shell scripts to cull code from and substitute variables within a maximally configured processing block files.
  • Preprocessing shell scripts can include textual or graphically-based user prompts for answering questions about specific parameters desired by the user for a particular block.
  • FIGS. 2A-2D show one possible example of graphical user interface (GUI) which can be used to enter parameters for packet processing blocks.
  • GUI graphical user interface
  • a Main generation GUI window 13 is presented to the user, as shown in FIG. 2A.
  • One of a number of radio buttons 13 is selected by the user to indicate the type of processing block to be configured.
  • a configuration window 15 is displayed, one for each type of processing block (i.e., PPU/PPUX (see FIG. 2B); PMU (see FIG. 2C); and DFU (see FIG. 2D)).
  • Each configuration window 15 contains a field 16 for naming the processing block.
  • a series of configuration screen elements 17 are presented to the user for allowing parameters of each processing block to be specified by the user (including, e.g., data bus width, start of packet width, end of packet width, maximum header words, qualifier width, result width, result .expression, external memory parameters, number of interfaces, etc.), and which may vary according each type of processing block.
  • the user can click on either a "Generate” button 18 to cause the particular processing block code to be generated, or a "Cancel” button 19.
  • the GUI code can pass the input parameters to a preprocessor, such as a preprocessor called "veriloop2."
  • a preprocessor such as a preprocessor called "veriloop2.”
  • the pseudo-code for veriloop2 can be found in Appendix F. Veriloop2 first performs substitutions into appropriate variables using the parameters passed from the GUI. Veriloop2 then searches for constructs such as name-value pairs, conditional constructs, and loops having a particular syntax, and then culls the maximally configured packet processing block file to produce a preprocessed header-like library files, each containing a function or class representing a particular PPU, DFU, etc.
  • Pseudo code for types of preprocessor constructs can be found in Appendix G. Pseudo code for sample pre-processed files of FIG.
  • Appendices H-L there is only one PPU/MLU/HLU file for all three PPUs, which share the same number of inputs/outputs and share the same general structure.
  • the number of PPUs that need to be generated depends upon the degree of parallelism needed for a particular design. If all the operations for a number of PPUs can be performed in series, then one PPU is needed, since all that changes between instances of PPUs is the input parameters (e.g. opcode, mask, etc.). There is one generated PPU for each parallel operation.
  • There are separate DFU Appendices i.e., Appendices B, H 1 and I because each DFU can have a different number of inputs/ outputs).
  • the present invention distils the implementation of maximally configured processing blocks into common sub-blocks which have unique names (e.g., PPlM , DFU_2) or modules which have inputs and outputs that can be interconnected in such a way as to perform all of the functions necessary for implementing a desired packet processing product.
  • the common blocks described herein are preferably instantiations of packet processing blocks written in VHDL 1 Verilog, or System C, but other suitable hardware description languages can be used.
  • the software implementation of packet processing blocks is platform independent, and can be written in a platform independent language such as JAVA.
  • packet parser/classifier functionality of the present invention can run both in Windows and in different versions of the Unix operating system, as well as others.
  • the programmer/designer can invoke instances of these common modules using a C-like application programming interface (API) surrounded by other C-like code for interconnecting the sub-blocks.
  • API application programming interface
  • integration involves declaring instantiations of each processing block by name, and making connections between instantiated packet parsing blocks in a top-level main program file (the top-level main program file is similar to the file containing the main() function call in C language). These connections are called “wires” or “signals” which are declared like variables, and associations are made between two processing block instances which have a common wire. For example, signal “x” in PPU1 ties to signal “y” in the top level file. Signal “z” of DFU 1 also ties to signal “y” in the top level file. In this way, signal “x” of PPU1 is tied to Signal “z” of DFU1 which may also be tied to one or more other signals. Certain input parameters can also be "hard-coded” within the top-level file.
  • step 6 if the customer desires only the design, then at step 7, the generated packet processing block files and the top level file can be delivered to the customer. If the customer desires to have a NETLIST, then at step 8, the generated files are run through a commercially-available synthesis tool, as is known in the art.
  • Sample synthesis tools include Design Compiler from Synopsis, Precision Synthesis from Mentor Graphics, Sinplify from Synplicity, or XST from Xilinx. The synthesis tool behaves like an optimizing compiler which produces a NETLIST for producing an electrical schematic for a custom integrated circuit which is implemented with a minimum number of logic gates, flip-flops, counters, etc.
  • NETLIST generated depends on whether the customer desires to have a foundry-specific device, e.g. a Xilinx FPGA or a generic ("virtual") NETLIST which is not specific to a particular vendor's product.
  • a foundry-specific device e.g. a Xilinx FPGA or a generic (“virtual") NETLIST which is not specific to a particular vendor's product.
  • Customers which are EDA (electronic design automation) vendors desire a non-specific NETLIST.
  • the NETLIST could be a foundry-specific or "virtual" bitstream or binary file that is delivered to customer.
  • the NETLIST is delivered to the customer, otherwise, at step 11 , the NETLIST is run through a place and route program, which physically constructs the gates defined in the NETLIST on a silicon die and interconnects them.
  • the choice of a place and route tool depends on whether the packet parser/classifier is to be implemented as an ASIC (fixed logic) or an FPGA (programmable logic).
  • Sample place and route programs include Quartus Il from Altera and ISE from Xilinx.
  • the integrated circuit is delivered to the customer.
  • FIG. 3 a block diagram of a graphical design environment using packet processing blocks according to the present invention for designing a packet processing product, indicated generally at 20, is depicted.
  • the blocks 20 can be implemented in a text-based or graphical design environment.
  • the environment 20 includes combinations of any number of Packet Parsing Units (PPUs) 22, PPUXs 24 (which are PPUs that can access CAM/RAM memory 26), Packet Modification Units (PMUs) 28, and Decision and Forwarding Units (DFUs) 30.
  • PPUs 22, PPUXs 24, PMUs 28, and DFUs 30 can be connected by a designer in a variety of ways to create parsing/classification logic for any desired packet processing algorithm.
  • the PPUs 22 operate on packet headers 21.
  • the packet itself can be passed through the environment 20 intact.
  • only the packet header 21 is passed through the environment, which requires the creation and passing of a pointer to the packet data to be output after the DFUs 30.
  • the packets are stored in memory upon arrival and retrieved from memory upon departure.
  • a copy of the header 21 and a pointer to the packet location is passed to the development environment 20.
  • the length of the copied header 21 is variable. It starts at a programmable position in the header 21 and ends at the last field that must be processed.
  • a PPU takes a header 21 and can seek, i.e., locate, any field of constant or variable length. Once the field is found in the header 21, the PPU 22 can perform a check on that field, such as whether the field is equal to or greater than a given value, or matches a particular value, and then output that value depending on the operation performed.
  • PPUXs 24 are PPUs that can perform lookups or searches using external random-access memories (RAMs) or CAMs (a CAM is defined as a RAM-like memory which can determine whether an input value is present in the memory device).
  • a PMU 28 is a PPU which allows fields in the header of a packet or the packet itself to be modified by means of insertions, deletions, or substitution of bytes.
  • the PPUs 22 and PPUXs 24 only allow the fields of a packet header to be examined. Any number of PPUs 22, PPUXs 24, and PMUs 28 can be chained together in series or in parallel to implement complex expressions.
  • the DFUs 30 combine the output of one or more PPUs 22 and/or PPUXs 24 and/or PMUs 28 using a programmable condition, and then forward the header to one of a plurality of outputs.
  • the outputs can represent Boolean True and False values, and decisions as to whether to drop, forward, or queue the packet.
  • the DFUs 30 make decisions to forward, drop, or enqueue packets based on the results from the. PPUs 22.
  • the output of the last DFU in the chain such as the DFU labeled "A"
  • the traffic manager 31 is a device which performs a set of actions and operations for a network to guarantee the operability of the network.
  • Traffic Management is exercised in the form of traffic control and flow control.
  • the traffic manager 31 operates on a packet stream once the classification & processing is done on a packet (i.e. once it passes from PPU/DFU blocks).
  • PPU/DFU blocks are used to figure out the priority number of a packet.
  • the traffic manager is given that priority number and the packet to do a traffic control operation to guarantee that high priority packets pass before low priority packets.
  • the PPU 22 performs basic parsing of the packet header 21 and may perform mathematical/logical operations on the parsed fields of packet header 21.
  • the PPU 22 includes a plurality of inputs and outputs 32-83. The function of each input and output 32-83, as well as the values that each input or output handle, are described with reference to Table 1 hereinbelow.
  • the input CIk 32 is supplied from external hardware, such as the clock of a microprocessor.
  • the Input Rst 34 is used to cause the PPU to go into a predefined state where most internal variables and outputs are set to an initial value. This condition is usually needed at power-up of the hardware in logic systems to stabilize the system before execution of a packet processing algorithm.
  • the system is initially Reset. A predetermined amount of time later, when it is known that all circuits have stabilized, then the circuit is put into operation by toggling Rst 34.
  • the PPU 22 includes a Hardware Lookup Unit (HLU) 84, a Delay/FIFO module 86 containing an optional Delay Line 88 or a FIFO 90, a Match and Lookup Unit (MLU) 92, Result Generation (process) 94, Sequence Generation (process) 96, an Output Alignment (process) 98, interconnected as shown.
  • the sub-blocks 84-98 are implemented as modules or processes.
  • a module is similar to a class or subclass in an object-oriented language like C++, while a process is similar to a function.
  • the PPU also contains (not shown) a predetermined but limited number of internal general-purpose registers for storing and retrieving values for comparisons, lookups, etc.
  • a stream of data is continuously presented to the input Dataln 36 of the HLU 84. No data of the input stream is stored in a memory. In such circumstances, it is the job of the HLU 84 to extract information from a packet and present that information to the other blocks of the PPU 22.
  • the HLU 84 takes a snapshot of the data stream according to the location in the data stream specified by the inputs Index 56 and Width 58.
  • the inputs SOHIn 38, EOHIn 40, and InVaI 42 allow for fine tuning of locating data from the output of other PPUs, PPUXs, PMUs, or external hardware.
  • SOHIn 38, EOHIn 40, and InVaI 42 tell the PPU 22 how to delimit data a packet header.
  • SOHIn 38 tells the hardware where packet starts and EOHIn 40 tells the hardware when a packet header ends. Once the packet starts, then at every clock cycle, the data presented at Dataln 36 is either valid or invalid, as indicated by the input InVaI 42.
  • the extracted header bits are present as an output CompDat 100 and as an input to the MLU 92.
  • CompDat 100 stands for the data that needs to be compared in the MLU 92.
  • the Delay/FIFO module 86 is used to synchronize the outputs of the PPU 22 to be presented to a subsequent block, such as a DFU.
  • the Delay/FIFO module 86 is needed because the inputs to the PPU, such as Dataln 36, along with the control input signals SOHIn 38, EOHIn 40, and InVaI 42, need to be aligned in time in the Output Alignment process 98 with intermediate outputs of other sub-blocks of the PPU 22, such as the Match output 110 of the MLU 92, which may be delayed relative to the inputs due to delays in processing within the MLU 92.
  • the MLU 92 performs its decision making (e.g., a comparison of a bit within Dataln 36 with a user specified parameter (Parami )) without full packet storage. Therefore, Dataln 36 along with the control input signals SOHIn 38, EOHIn 40, and InVaI 42 are pipelined to the Result Generation process 94 and the Output Alignment process 98 by way of intermediate I/O Val_i 102, SOH_i 104, EOH_i 106, and Data_i 108. There are fixed delays (measured in clock cycles) associated with processing in the in Result Generation process 94 and the MLU 92. There is a variable delay associated with the HLU 84 depending upon value of Index 56.
  • the inputs described above must be delayed in the Output Alignment process 98 by the sum of the aforementioned individual delays. For example, if Index 56 is 8, then CompDat 100 is received at the MLU 92 eight clock cycles after Dataln 36 arrives at the PPU 22. If the MLU 92 processes CompDat 100 in three clock cycles, then the PPU 22 inputs need to be delayed by 8 + 3 clock cycles in the Output Alignment process 98.
  • the choice of the optional Delay Line 88 or the FIFO 90 depends on the size of the delay needed. A FIFO always works but requires using scarce memory in the PPU 22.
  • the MLU 92 performs the bulk of the packet parsing and classification operation to be performed on one unit of a packet processing algorithm.
  • the MLU 92 is programmable, i.e., it can compare the data/fields extracted in the HLU 84 with values stored in internal registers by means of the inputs Opcode 62, Parami 64, Param2 66, and Mask 68 and declares a match or no match which appears on the internal output Match 110, which, in turn, appears as an output of the Result Generation process 94.
  • the inputs QualEnb 52 and QualCond 54 enable or disable the MLU 92 depending on certain conditions.
  • the operation to be performed in the MLU 92 are enabled if the result of the check of the QualEnb 52 using the QualCond 54 is true.
  • QualEnb 52 is a value stored in a qualEnb register (not shown) which is user programmable through an address map.
  • the Qualifier Condition 44 can be: Always True, Equal, Less Than, Less Than or Equal, Greater Than, Greater Than or Equal, etc.
  • QualEnb 52 can be programmed through the qualEnb register (not shown) to be the value 6.
  • QualCond 54 is set to Equal To (EQ).
  • the packet type is retrieved from a mode register from an external CPU. If the packet type is 6 (IPV6), then the MLU 92 is enabled; if the packet type is 4 (IPV4), then the MLU 92 is disabled, and no comparison takes place. If it is desired to have all types of IP packets, then QualCond 54 is set to Less Than or Equal (LE) or Always True.
  • the match/no-match functionality of the MLU 92 is performed on the portion of the Dataln 36 packet header pointed to by Index 56 and Width 58. Additional inputs Mask 60, Opcode input 62, Parami 64, and optionally Param2 66 are needed to perform the comparison/match/no-match operation.
  • the MLU 92 performs a seek and operation function.
  • the seek function finds a data field in a packet header (not shown) based on an offset from the start of the packet header indicated by the input Index 56. If Index 56 is 0, then the first byte of the packet header is indicated. An Index 56 of six indicates the seventh byte from the beginning of the packet header.
  • the interconnections that can be made to the Index input 56 include a fixed value (e.g. 4), a value stored in an internal user defined control register, or the result output 70 of another PPU, PMU, or DFU. If the Index input 56 is driven from another PPU, PMU, or DFU 1 the value placed on the Index input 56 is variable, depending on the condition(s) evaluated in the previous PPU, PMU 1 or DFU.
  • the operation function performs a check, an extraction, or a lookup on "Data Field", which is the contents of the packet header pointed to by the Index input 56 of width equal to the value in bits placed on the Width input 58.
  • Data Field is the contents of the packet header pointed to by the Index input 56 of width equal to the value in bits placed on the Width input 58.
  • the Data_Field may be filtered (AND'ed) with the Mask input 60.
  • Op is one of the opcodes placed on the Opcode input 62 given the Parami input 64, and optionally the Param2 input 66.
  • Table 2 The types of operations are shown in Table 2 below:
  • a single MLU can be programmed to check if an IP address less than 224.XX.XX.XX, by specifying the following values:
  • IP DA Points to IP DA or SA and can be adjusted automatically for VLAN tagging using a PPU.
  • the inputs MapWrRd_n 76, MapAddr 78, and MapWrData 80, and the output MapRdData 81 are used as the interface between an external microprocessor and the internal registers of the PPU 22 to allow for reading of and writing to the registers.
  • the PPU 22, PPUX 24, PMU 28, and DFU 30 can contain a user defined number of internal registers for packet header manipulation either internally or via an external microprocessor.
  • the opcodes LUP and SPCL can be used to directly manipulate data in internal registers.
  • the output Match 110 of the MLU 92 is fed to the input of the Result Generation process 94 to be described hereinbelow.
  • the Match output 110 is True if the operation performed in the MLU 92 is True, or False otherwise.
  • the Result Generation process 94 takes the Match output 110, the outputs of the Delay/FIFO module 86, and optionally a tag value present on TAG 83 and produces the result output iResult 112, which is fed as an input to the Output Alignment process 98 and ultimately is the output Result 70 of the PPU 22.
  • the Result Generation process 94 also outputs iResVal 114, which indicates when iResult 112 is valid. This is needed as a handshaking device, since result generation can take more than a single clock cycle.
  • iMatch 116 is the value of Match 110 passed along from the MLU 92. Assuming the MLU 92 was enabled, iResult 112 can take on two values corresponding to the True or False evaluation of the operation performed in the MLU 92. The True/False result values can be fixed or an arithmetic or logical function of any of the PPU 22 inputs. The iResult output 112 is later passed through the Output Alignment process 98 to be described hereinbelow as Result 70, which can be used to drive a DFU input or any input of another PPU or a PMU. Result 70 can also be a complex expression that the user may want to program. This allows the Index 56, QualEnb 52, Opcode 62, or Param ⁇ 1,2> 64, 66 inputs of a PPU to be driven with different values depending on the Result 70 output of other PPUs.
  • the PPU 22 generates or forwards a sequence number using the Sequence Generation process 96.
  • the sequence number can optionally come from an external process/hardware via the input Seqln 82 and passed along to a DFU; otherwise sequence numbers are internally generated within a PPU 22 using the Sequence Generation process 96.
  • the sequence number which appears as an internal output iSeq 118, is passed through the Output Alignment process 98 to a DFU through the PPU output SeqOut 74. Sequence numbers are incremented sequentially for each use of a PPU and are used for internal synchronization of all the inputs of a DFU. Sequence numbers are needed because different PPUs can present their output packet header data, match data, and results at different times.
  • one PPU may index at bit 0 of an incoming packet, in which case match output may appear at an input to a DFU after three clock cycles. If another PPU indexes on a VLAN type field, then index is set to block 5 or 6, which gives its results to the same DFU after 6 + 3 clock cycles.
  • the DFU takes the matches packet headers, and sequence number from each of the PPUs and arranges them in correct sequence to be described hereinafter.
  • the Output Alignment process 98 aligns all outputs to the start of packet (SOP) or the end of packet (EOP). This is done in order to provide proper delineation of the output signals of one PPU to the next PPU/PPUX/PMU/DFU. For example, if PPU1 is connected to PPU2, and PPU1 operates either on an 802.3 Ethernet frame or an Ethernet type 2 frame, then PPU 1 examines a byte field which is either 20 bytes or 40 bytes from the beginning of a packet header. Therefore, all outputs of PPU 1 need to be aligned on SOP as a requirement for input to PPU2. As another example, some protocols use trailer insertion, e.g., inserting a checksum at the end of a packet. Therefore, outputs are aligned at EOP.
  • FIG. 5 a block diagram of a PPUX 24 is depicted.
  • a PPUX 24 has the same I/O signals and sub-blocks as the PPU 22 except for additional I/O needed to access an external CAM/RAM 220.
  • Elements illustrated in FIG. 5 which correspond to the elements described above in connection with the PPU 22 of FIG. 5 have been identified by corresponding reference numbers increased by one hundred. Unless otherwise indicated, both the PPU 22 and the PPUX 24 have the same construction and operation.
  • a PPU there is a predetermined number of internal registers/memory which can be programmed by a user.
  • a typical need for programmed memory is for performing a lookup of values by MLU 192. For example, if there is a need to compare Parami 164 to one hundred IP addresses, then internal memory is used. However, if the number of lookups and hence values to be stored in memory is on the order of thousands of bytes or more, then it may be necessary to store and retrieve these values to/from an external CAM/RAM 220.
  • a PMU Packet Modification Units
  • a PMU allows for modification, i.e., insertion, deletion, or replacement, of bytes in a packet, including both the header and payload data.
  • the PMU 28 includes a Delay/FIFO module 300 containing an optional Delay Line 302 or a FIFO 304, a Modification Unit (MU) 306, a Result Generation process 308, a Sequence Generation process 310, and an Output Alignment process 312, interconnected as shown.
  • These sub-blocks 300-312 are implemented as software modules or processes.
  • the inputs InVaI 314, SOHIn 316, EOHIn 318, Dataln 320, Tagln 322, Rst 324, and CIk 326 have the same functionality as is found in the PPU 22 and the PPUX 24.
  • the delay/FIFO module 300 can be used to synchronize the inputs InVaI 314, SOHIn 316, EOHIn 318, Dataln 320, and Tagln 322 with the outputs of the Result Generation Process 308 and the outputs of the Modification Unit (MU) 306 as is done in the PPU 22, but it also provides a second function: to delay incoming packet data by an amount equal to the number of bytes that may be inserted into a packet in the Modification Unit 306.
  • the choice of the optional Delay Line 302 or the FIFO 304 depends on the size of the delay needed. If only a few clock cycles worth of delay (a few words to be inserted) are needed, then the Delay Line 302 is used, otherwise the FIFO 304 is used.
  • InVaI 314, SOHIn 316, EOHIn 318, and Dataln 320 are pipelined to the a Modification Unit (MU) 306 as the intermediate outputs VaI i 328, SOH_i 330, EOH_i 332, and Data_i 334.
  • MU Modification Unit
  • Val_i 328 is also directed to the Result Generation Process 308.
  • the Result Generation Process 308 has a different purpose from the one found in a PPU 22.
  • the intermediate outputs iResVal (result valid) 358 and iResult (the result) 360 are not based on a field value, but reflect the number of bytes inserted.
  • iResult 360 becomes the output Result 378 which can be used as an input to another PPU/PPUX/PMU/DFU. It can also be a complex expression that the user may want to program.
  • the Sequence Generation Process 310 with the optional Seqln input 362 has the same functionality as in the PPU 22.
  • the Modification Unit (MU) 306 inserts/modifies/removes data as specified by a user.
  • the MU 306 is specified at preprocessing time as one of an inserting type, modifying type, or removing type PMU.
  • the type of operations performed by the input signals ByteOffset 336, ByteValid 338, and ByteData 340 are shown in Table 4 below:
  • MapWrRd_n 342, MapAddr 344, and MapWrData 346, and the output MapRdData 348 provide a future programming interface for an external microprocessor to allow for the reading and writing from/to internal registers of the PMU 28 to, for example, dynamically program an MU to either insert, delete, or modify a packet at run time.
  • VaM 350, SOH_i 352, and EOH_i 354 are passed after a delay intact from their corresponding inputs to the MU 306 to the Output Alignment process 312.
  • the modified packet, represented as the intermediate input/output Data_i 356 is also presented to the Output Alignment process 312.
  • the Output Alignment process 312 has the same purpose and functionality as found in the PPU or PPUX, i.e., aligning all intermediate outputs iSeq 362, iResVal 358, iResult 360, VaIM 350, SOH_i 352, EOH_i 354 and Data_i 356 on either the start of packet (SOP) or the end of packet (EOP) to become the aligned outputs SeqOut 366, OutVal 368, SOHOut 370, EOHOut 372, DataOut 374, ResVal 376, Result 378, and TagOut 380.
  • the DFU 30 performs drop, queue, or forward operations based on input from 1 to N PPUs, PPUXs, PMUs, or other DFUs.
  • the DFU 30 includes a plurality of inputs and outputs 400-444. The function of each input and output 400-444, as well as the values each input or output can take on, are described with reference to Table 5 hereinbelow.
  • the DFU 30 includes sub-blocks Latch 445a-445n, Data Selection MUX 446, Result Generation process 448, and Output Alignment process 450.
  • the triangles within FIG. 7 are for blocking together intermediate outputs and do not themselves have inherent functionality. All sub-blocks are processes.
  • Latch 445a-445n latches the incoming results, data, and other output signals coming from 0 to N-1 PPUs/PPUXs/PMUs to be processed at a later time inside the DFU 30.
  • the Latch 445a-445n are necessary since each PPU/PPUX/PMU may present packet data at different times.
  • each Latch 445a-445n namely iRlnVal 459a-459n, iMln 460a-460n, iRln 462a- 462n, and iRlnSeq 464a-464n corresponding to the latched inputs RInVaI 406a- 406n, MIn 402a-402n, RIn 400a-400n, and RlnSeq 404a-404n, respectively, and representing together control/result signals from each PPU/PPUX/PMU, belong to groups, which are fed together to the Result Generation process MUX 448.
  • the Data Selection MUX 446 selects one of the sets of N-1 data groups and forwards the data group to the output group which includes iDValOut 466, iSOHOut 468, iEOHOut 470, and iDOut 472 as inputs to the Output Alignment Process 450.
  • the Result Generation Process 448 has a similar purpose to that found in the PPU/PPUX, namely, generating a result iRout 482 which depends on the evaluation of a programmable logical expression which may depend on the value of the inputs RIn[O - (N-1)] 400a-400n and/or Min [ 0 - (N-1 ) ] 402a-402n.
  • the evaluation of this complex logical expression can determine an output port to which the packet is to be routed, i.e., the pass along/queue outputs A and B, or the drop port D, represented as active high enabling intermediate outputs iROutAVal 476, iROutBVal 478, and iROutDVal 480.
  • These outputs are passed along to the Output Alignment Process 450, which has the same purpose and function as the PPU 22, PPUX 24, and PMU 28.
  • the intermediate outputs 466-482 become the DFU outputs DValOut 426, SOHOut 428, EOHOut 430, DOut 432, SeqOut 416, ROutAVal 408, ROutBVal 410, and ROutDVal 412. and Rout 414, respectively.
  • the output DOut 432 is routed to one of three output ports: DOutA 484, DOutB 486, or DOutD 488.
  • DOutA 484 and DOutB 486 can be used for normal output and DOutD 478 can be used for dropping a packet (not shown).
  • DOutD 488 can be used as a third routing output port.
  • the packet is either forwarded to a destination, or another chain of PPUs/PPUXs/PMUs, or sent to a queue of a traffic manager.
  • the design environment of the present invention can be connected to a set of internal PPU/PPUX/PMU/DFU registers and programmed through a microprocessor interface. The operations that the microprocessor would perform are reads and writes to/from the registers. Table 6 below shows a sample interface for a microprocessor manufactured by Freescale, Inc. (formerly Motorola):
  • Chip Select This active low signal enables the
  • control inputs of the PPUs or DFUs can be driven with fixed values (hardwired), from programmable registers, or from the outputs of other PPUs or DFUs.
  • Table 7 shows the options for control signal connections, with some typical examples of standard packet processing:
  • Each PPU/PPUX/PMU/DFU is configurable at synthesis time using the parameters shown in Table 8:
  • the packet processing algorithm relates to extracting the precedence field of an IP packet for a VLAN/Non-VLAN frame from a packet header 500 belonging to a packet 499.
  • Pseudo code which implements the two DFUs and the three PMUs of FIG. 8 can be found in Appendix H-L.
  • a top-level file for the example of FlG. 8, expressed in pseudo code, can be found in Appendix M.
  • the precedence field is used as the QID of the queue into which the packet is to be stored in a traffic manager.
  • the packet header 500 is fed to a Dataln input 502 of a PPU 504.
  • the operation to be performed is:
  • the Result output 506 of the PPU 504 is set to point to the location or offset in the packet header 500 of the IP address in a VLAN type frame, otherwise it points to the location in the packet header 500 of the IP address in a non-VLAN frame.
  • This IP address is fed to the Index input 508, along with the header 500 to a second PPU 510.
  • the most significant byte is checked and must be less than 224, signifying that the input IP address is valid. The operation to be performed is:
  • the ToS tells the application how a datagram should be used, e.g. delay, precedence, reliability, minimum cost, throughput etc. Depending on the value of the ToS field, one can change a priority assigned to a packet which is then sent to a traffic manager which processes the packet based on the set priority.
  • the IP precedence field is extracted from the header 500 with the following operation:
  • the IP precedence field is fed to the Din[0] input 524 of a second DFU 526.
  • the DFU 526 places the packet header on the DOutA output 528 of an AND gate 530 for queueing, and the precedence field is placed on the DOutB output 532 of an AND gate 534.
  • the precedence field functions as the Queue Identifier (QID) for the packet to be queued and both inputs 536, 538 are fed to a traffic manager 540.
  • the traffic manager 540 outputs the classified packet on output 542 and the QID on output 544.
  • packet processing blocks having other types of functionality can be provided, such as:
  • the programmer/designer can use a graphical design program such as OrCAD or Microsoft Visio to draw and interconnect sub-blocks with input windows for entering interconnecting expressions and entering program inputs.
  • a graphical design program such as OrCAD or Microsoft Visio to draw and interconnect sub-blocks with input windows for entering interconnecting expressions and entering program inputs.
  • the present invention has several advantages over prior art packet processing products.
  • the present invention can be used to produce an inexpensive piece of digital hardware, while the prior art products are limited to programs running on a microprocessor.
  • the present invention is scalable to handle simple to complex classification tasks, and software modules can be connected and configured in a variety of ways.
  • DataWidth OEQ (DataWidth) ;
  • MaxHdrWords OEQ MaxHdrWords
  • QualifierWidth OEQ (QualifierWidth) ;
  • ResultWidth OEQ (ResultWidth) ;
  • FieldWidth OEQ FieldWidth
  • LookupAvaliable OEQ (LookupAvaliable) ;
  • LookupDepth OEQ (LookupDepth) ;
  • Log2LookupDepth ®L2 (LookupDepth) ;
  • SobBits OEQ SObBitS
  • WordNo[i] (Index [IndexWidth-1 : Log2DataWidth] +i)
  • Startlndex [i] 0,- ENDLOOP signal iOutVal ; signal iOutMatch; signal QEnable,- signal [QualifierWidth-1 : 0] QualEnbCondition;
  • ResVal (iSOHOut [SobBits-1] & iValOut) ;
  • PROCESS (on rising edge of CIk) : OUTPUT_ALINGEMENT_PROCESS IF Rst is high assign reset values to iEnbOut assign reset values to OutState assign reset values to Match ELSE
  • PROCESS (on rising edge of CIk) : OUTPUT_ALINGEMENT_PROCESS IF Rst is high assign reset values to iResVal assign reset values to Match assign reset values to Sellndex ELSE
  • DataWidth OEQ(DataWidth) ;
  • InResultWidth OEQ (InResultWidth) ;
  • Log2NumPPUConnects ®L ⁇ 2 (NumPPUConnects) ;
  • DFUID OEQ(DFUID);
  • SopBits OEQ (SopBits) ,-
  • EopBitS OEQ (EopBits) ;
  • PROCESS (on rising edge of CIk) : DATA_SELECTION_MUX_PROCESS IF Rst is high assign initial value to ROutAVal assign initial value to ROutBVal assign initial value to ROutDVal assign initial value to DValOut assign initial value to SOHOut 54 assign initial value to EOHOut assign initial value to DOut assign initial value to StartOutputData ELSE
  • PROCESS (on rising edge of CIk) : RESULT_GENERATION_PROCESS IF Rst is high assign initial value to ROut assign initial value to SOut assign initial value to OutOfSeqErr 55 assign initial value to ⁇ equenceCheck ELSE
  • IF Result output delay is more reclock to align with the result outputs ROutAVal reclock to align with the result outputs ROutBVal reclock to align with the result outputs ROutDVal reclock to align with the result outputs DValOut reclock to align with the result outputs SOHOut reclock to align with the result outputs EOHOut reclock to align with the result outputs DOut ENDIF IF
  • Data output delay is more reclock to align with the result outputs ROut reclock to align with the result outputs SOut ENDIF ENDIF ENDPROCESS // register map
  • DataWidth ®EQ (DataWidth) ;
  • ResultWidth ®L2 (MaxHdrWords* (DataWidth/8) );
  • FieldWidth @EQ (MaxHdrWord ⁇ *DataWidth) ;
  • FieldValidWidth @EQ (MaxHdrWords*DataWidth/8) ;
  • TAGBits @EQ (TAGBits) ,-
  • SobBits OEQ (SobBits) ;
  • EobBits OEQ (EobBits) ;
  • HdrWord [j] HdrData [ ( (i+1) *DataWidth) -1 : (i*DataWidth) ] ;
  • HdrWordMod[j] HdrByteVal [ ( (i+l) * (DataWidth/8) ) -1 :
  • HdrState [i] i; ENDLOOP enum OpCodesType ⁇ Opr_Ins, Opr_Mod, Opr_Rem ⁇ ; OpCodeaType OpCode,- PROCESS (on rising edge of CIk) IF Rst is high assign reset values to HdrExtState assign reset values to InVal_i assign reset values to lnSop_i assign reset values to InSop_l assign reset values to InEop_i assign reset values to InDat_i assign reset values to Result assign reset values to CurPktlndex
  • InVal_i InVal_r [Adjusted OFFSET based on no of bytes inserted] ,
  • InDat_i InDat_r [Adjusted OFFSET based on no of bytes inserted] ;
  • IF Result output delay is more reclock to align with the result outputs OutVal reclock to align with the result outputs SOHOut reclock to align with the result outputs EOHOut reclock to align with the result outputs DataOut ENDIF IF Data output delay is more reclock to align with the result outputs ResVal reclock to align with the result outputs Result ENDIF ENDIF ENDPROCESS //
  • PROCESS (on rising edge of CIk) : REGISTER_MAP IF Rst is high assign reset values to MapRdData assign reset values to Opcode (i.e. Opcode present) assign reset values to SPsignal_O assign reset values to SPsignal_l assign reset values to SPsignal_2 61 assign reset values to ⁇ Psignal_3 ELSE
  • This f i le contains generic hardware look -up uni t (header extraction block) (HLU)
  • SobBita ⁇ EQ(SobBits) ,-
  • MaxHdrWords ⁇ EQ(MaxHdrWord ⁇ ) ;
  • MaxHdrWords is not equal to MaxHdrWords increment HdrWordCntr by one ENDIF
  • LookupAvaliable @EQ (LookupAvaliable) ;
  • conditionN //else_if_generate (conditionN) - optional code needed to be generated if conditionN is true
  • PROCESS (on rising edge of CIk) : VALUE_LATCH_PROCESS IF Rst is high assign initial value to iRInVal assign initial value to iMIn
  • PROCESS (on rising edge of CIk) : DATA_SELECTION_MUX_PROCESS IF Rst is high assign initial value to ROutAVal assign initial value to ROutBVal assign initial value to ROutDVal assign initial value to DValOut assign initial value to SOHOut assign initial value to EOHOut assign initial value to DOut assign initial value to StartOutputData
  • EOHOut EOHIn [LastArrivalData] ;
  • PROCESS (on rising edge of CIk) : RESULT_GENERATION_PROCESS IF Rst is high assign initial value to ROut assign initial value to SOut assign initial value to OutOfSeqErr assign initial value to SequenceCheck
  • IF Result output delay is more reclock to align with the result outputs ROutAVal reclock to align with the result outputs ROutBVal reclock to align with the result outputs ROutDVal reclock to align with the result outputs DVaIOut reclock to align with the result outputs SOHOut reclock to align with the result outputs EOHOut reclock to align with the result outputs DOut ENDIF IF Data output delay is more reclock to align with the result outputs ROut reclock to align with the result outputs SOut ENDIF ENDIF ENDPROCESS
  • PROCESS (on rising edge of CIk) : DATA_SELECTION_MUX_PROCESS IF Rst is high assign initial value to ROutAVal assign initial value to ROutBVal assign initial value to ROutDVal assign initial value to DValOut assign initial value to SOHOut assign initial value to EOHOut assign initial value to DOut assign initial value to StartOutputData
  • PROCESS (on rising edge of CIk) : RESULT_GENERATION_PROCESS IF Rst is high assign initial value to ROut assign initial value to SOut assign initial value to OutOfSeqErr assign initial value to SequenceCheck
  • IF Result output delay is more reclock to align with the result outputs ROutAVaI reclock to align with the result outputs ROutBVal reclock to align with the result outputs ROutDVal reclock to align with the result outputs DValOut reclock to align with the result outputs SOHOut reclock to align with the result outputs EOHOut reclock to align with the result outputs DOut ENDIF IF Data output delay is more reclock to align with the result outputs ROut reclock to align with the result outputs SOut ENDIF ENDIF ENDPROCESS
  • IndexWidth LLoo ⁇ g22DDaattaWidth+Log2MaxHdrWords ;
  • MapWrRd_n 85 input [3:0] MapAddr, input [31:0] MapWrData,- output [31:0] MapRdData; // Result values output Match; output ResVal ; output [Re ⁇ ultWidth-1 :0] Result; output [7:0] SeqOut , ) ,
  • WordNo[i] (Index [IndexWidth-1 :Log2DataWidth] +i) ;
  • PROCESS (on rising edge of CIk) : OUTPUT_ALINGEMENT_PROCESS IF Rst is high assign reset values to iResVal assign reset values to Match assign reset values to Sellndex ELSE
  • PROCESS (on rising edge of CIk) : SEQUENCE GENERATION IF R ⁇ t is high assign reset values to SeqOut ELSE
  • PROCESS (on rising edge of CIk) IF R ⁇ t is high assign reset values to OutVal assign reset values to OutMatch assign reset values to LklnStart assign reset values to LklnProgress assign reset values to LnkProcessState ELSE

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Abstract

L'invention concerne un système et un procédé pour permettre à un utilisateur de créer des instructions pour construire un circuit intégré de traitement de paquet. Le système comprend une interface utilisateur pour permettre à un utilisateur de définir un algorithme (4) de traitement de paquet désiré à l'aide d'une pluralité de blocs discrets de traitement de paquet (22, 24, 28, 30), chacun des blocs correspondant à une partie de l'algorithme (4) de traitement de paquet désiré. Le système permet à l'utilisateur de définir des connections (10) entre la pluralité de blocs de traitement de paquet (22, 24, 28, 30). Le système traite une pluralité de blocs de traitement de paquet (22, 24, 28, 30) et les connexions pour donner une liste d'instructions dans un langage de description de matériel pour fabriquer un circuit intégré qui peut exécuter l'algorithme (19) de traitement de paquet désiré.
PCT/US2007/012583 2007-05-24 2007-05-24 Système et procédé pour concevoir et mettre en œuvre des produits de traitement de paquet WO2008143622A1 (fr)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020010886A1 (en) * 2000-01-18 2002-01-24 Daihen Corporation Recording medium storing a program for constructing scan paths, scan path constructing method, and arithmetic processing system in which said scan paths are integrated
US20030198204A1 (en) * 1999-01-13 2003-10-23 Mukesh Taneja Resource allocation in a communication system supporting application flows having quality of service requirements
US20050058149A1 (en) * 1998-08-19 2005-03-17 Howe Wayne Richard Time-scheduled and time-reservation packet switching
US20060039280A1 (en) * 1999-08-10 2006-02-23 Krishnasamy Anandakumar Systems, processes and integrated circuits for rate and/or diversity adaptation for packet communications
US20060256719A1 (en) * 2002-06-10 2006-11-16 Hsu Raymond T Packet flow processing in a communication system
US20070050603A1 (en) * 2002-08-07 2007-03-01 Martin Vorbach Data processing method and device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050058149A1 (en) * 1998-08-19 2005-03-17 Howe Wayne Richard Time-scheduled and time-reservation packet switching
US20030198204A1 (en) * 1999-01-13 2003-10-23 Mukesh Taneja Resource allocation in a communication system supporting application flows having quality of service requirements
US20060039280A1 (en) * 1999-08-10 2006-02-23 Krishnasamy Anandakumar Systems, processes and integrated circuits for rate and/or diversity adaptation for packet communications
US20020010886A1 (en) * 2000-01-18 2002-01-24 Daihen Corporation Recording medium storing a program for constructing scan paths, scan path constructing method, and arithmetic processing system in which said scan paths are integrated
US20060256719A1 (en) * 2002-06-10 2006-11-16 Hsu Raymond T Packet flow processing in a communication system
US20070050603A1 (en) * 2002-08-07 2007-03-01 Martin Vorbach Data processing method and device

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