WO2008138926A1

WO2008138926A1 - Single-ended and matched complementary output driver with configurable driver strength, slew rate and propagation delay times

Info

Publication number: WO2008138926A1
Application number: PCT/EP2008/055836
Authority: WO
Inventors: Gerd Rombach
Original assignee: Texas Instruments Deutschland Gmbh
Priority date: 2007-05-14
Filing date: 2008-05-13
Publication date: 2008-11-20

Abstract

A driver for digital complementary signals applied to RAM modules, comprises a chain of series-connected delay cells each with differential signal inputs and differential signal outputs. The driver further comprises two sets of output stages, each output stage with a signal input, a single-ended signal output and an enable input. The signal outputs of the output stages in the first set are all connected to a first common differential driver output and the signal inputs of the output stages in the first set are connected to signal outputs of different ones of the delay cells or to a signal input of the first delay cell in the chain. Further, the signal outputs of the output stages in the second set are all connected to a second common differential driver output and the signal inputs of the output stages in the second set are each connected to a signal output of a different one of the delay cells or to a signal input of the first delay cell in the chain. The driver properties at the first and second common differential driver outputs are digitally programmable by selectively applying enable signals to the enable inputs of the output stages. Likewise, by digitally programming the enabling signals that are statically applied to the driver's output stages, the essential driver properties can be adjusted: driver strength, slew rate and delay time.

Description

Single-ended and matched complementary output driver with configurable driver strength, slew rate and propagation delay times

The present invention relates to the field of drivers for digital address, data or clock signals applied to a series of RAM modules such as DRAMs on different kinds of PC or server DIMM boards.

An important property for drivers in such applications is the driver strength, i.e. the output impedance of the driver's output stages. Depending on each particular memory configuration, different driver strengths may be necessary. Other important properties are slew rate and propagation delay. In addition, single-ended and complementary drivers are needed in DIMM applications. For example, the clock signals are complementary and the address signals are single-ended. But they should match each other in all their specifications. In a typical application with an integrated CMOS circuit, many driver output stages are spread over the die. With increasing clock frequencies, e.g. 800 MHz for a DDR3 application, the physical distances on the die require strategies that are no more achieved with a central analog control of the circuit properties.

The present invention, in a first aspect, provides a driver for digital single-ended signals applied to RAM modules that can be digitally controlled. Specifically, the invention in its first aspect provides a driver for digital single-ended signals applied to RAM modules. The driver comprises a chain of series-connected delay cells each with differential signal inputs and differential signal outputs. The driver further has a set of output stages each with a signal input, a single-ended signal output and an enable input. The signal outputs of the output stages are all connected to a common single-ended driver output. The signal inputs of the output stages are connected to signal outputs of different ones of the delay cells or to the signal input of the first delay cell in the chain. The properties of the driver at the common driver output are digitally programmable by selectively applying enable signals to the enable inputs of the output stages. By digitally programming the enabling signals that are statically applied to the driver's output stages, the essential driver properties can be adjusted: driver strength, slew rate and delay time.

In a second aspect of the invention, a similar concept is proposed for complementary signals applied to RAM modules. Specifically, the invention in its second aspect provides a driver for digital complementary signals applied to RAM modules, comprising a chain of series- connected delay cells each with differential signal inputs and differential signal outputs. The driver further comprises two sets of output stages, each output stage with a signal input, a single-ended signal output and an enable input. The signal outputs of the output stages in the first set are all connected to a first common differential driver output and the signal inputs of the output stages in the first set are connected to signal outputs of different ones of the delay cells or to a signal input of the first delay cell in the chain. Further, the signal outputs of the output stages in the second set are all connected to a second common differential driver output and the signal inputs of the output stages in the second set are each connected to a signal output of a different one of the delay cells or to a signal input of the first delay cell in the chain. The driver properties at the first and second common differential driver outputs are digitally programmable by selectively applying enable signals to the enable inputs of the output stages. Again, by digitally programming the enabling signals that are statically applied to the driver's output stages, the essential driver properties can be adjusted: driver strength, slew rate and delay time.

Despite the physical distances of components and building blocks spread over the die of the integrated CMOS circuit and despite the high switching frequencies involved, a complete matching of signal specifications can be achieved by digital programming of the drivers.

In a third aspect of the invention, an integrated CMOS circuit is provided which comprises on a single die a plurality of the inventive drivers as defined, and these drivers all have matched output stages, especially for single-ended and for complementary signals.

In the preferred embodiments of the invention, cross-coupling is widely used to compensate for imbalanced signals.

Further details of the invention will ensue from the following description of preferred embodiments with reference to the appending drawings. In the drawings:

Fig. l is a block diagram of a driver for digital complementary signals; Fig. 2 is a block diagram of a driver for digital single-ended signals; Fig. 3 is a circuit diagram of a delay cell used in the driver; Fig. 4 is a circuit diagram of an output stage used in the driver;

Fig. 5 is a partial diagram of an alternative embodiment with parallel output stages that receive the same input signal;

Fig. 6 a), b) and c) circuit diagrams of an inverter stage between supply terminals, a dummy inverter stage and an inverter stage for connection between current sources, respectively; and

Fig. 7 is a signal diagram with exemplary wave forms obtained with the driver.

With reference first to Fig. 1 , complementary input signals IN and INB are applied to input terminals IN and INB of a first stage DLY1 of a delay chain that, in the embodiment shown, consists of five series-connected delay cells DLY1 to DLY5. The inverting outputs OUTB of the delay cells are coupled with the non-inverting inputs of the successive delay cells and the non- inverting outputs OUT of the delay cells are coupled with the inverting inputs INB of successive delay cells, successive delay cells effectively being cross-coupled. A first set of parallel output stages Stagel to Stageθ all have their signal outputs OUT connected to a first signal output OUT. A second set of parallel output stages CStagei to CStageθ all have their signal outputs OUT connected to a second, complementary signal output OUTB. Each output stage has a signal input IN and an enable input ENB. Digital enabling signals ENB1 to ENB6 are applied to the enable inputs of the first set of output stages and the same digital enabling signals ENB1 to ENB6 are applied to the enable inputs of the second set of output stages. The signal inputs of output stages Stagel and CStagei are connected to the complementary input terminals IN and INB, respectively. The signal inputs of the remaining output stages Stage2 to Stage 6 in the first set are coupled to alternating outputs of the successive delay cells DLY1 to DLY5. For example, the signal input of output stage Stage2 is connected to the non-inverted output OUT of delay cell DLY1 and the signal input of output stage Stage3 is connected to the inverted output OUTB of delay cell DLY2. Similarly, the signal inputs of the remaining output stages CStage2 to CStageθ in the second set are coupled to alternating outputs of the successive delay cells DLY1 to DLY5. For example, the signal input of output stage CStage2 is connected to the inverted output OUTB of delay cell DLY1 and the signal input of output stage CStage3 is connected to the non-inverted output OUT of delay cell DLY2.

The enable signals ENB1 to ENB6 are provided by a control logic that permits these signals to be programmed in accordance with requirements.

The embodiment in Fig. 2 is similar to that in Fig. 1 , except for a single-ended output concept so that the second set of output stages is eliminated. In order to keep loads balanced, dummy loads DL1 to DL6 are connected to those terminals of the delay cells DLY1 to DLY5 to which no signal input of an output stage is coupled. The dummy loads are derived from a basic inverter circuit in which the series-connected complementary transistors P1 and N1 have the drain and source interconnected, as shown in Fig. 6 b).

The delay cells are each configured as shown in Fig. 3. Each delay cell consists of a parallel connection of a first delay stage I-DELAY with two parallel inverters IV5, IV6, one for each of the two complementary input signals, and a second delay stage J-DELAY with two parallel pairs of series-connected inverters IV1 , IV3 and IV2, IV4. Inverters IV1 and IV2 are basic, each with a pair of complementary MOS transistors P1 , N1 , as sown in Fig. 6a, connected in series between the positive and negative supply terminals, with a signal input IN at the interconnected gates and a signal output OUT at the interconnected source of P1 and drain of N1. All other inverter stages IV3 to IV6 are also basic inverters, as shown in Fig. 6c, but have controlled current supplies. Specifically, inverters IV3 and IV4 of delay stage J-DELAY have negative supply current sources NJ1 , NJ2, NJ3 and NJ4 all connected in parallel and each with a control input J1 , J2, J3 and J4, respectively, and positive supply current sources PJ1 , PJ2, PJ3 and PJ4 all connected in parallel and each with a control input JB1 , JB2, JB3 and JB4, respectively. Similarly, inverters IV5 and IV6 of delay stage I-DELAY have negative supply current sources NM , NI2, NI3 and NI4 all connected in parallel and each with a control input 11 , I2, I3 and I4, respectively, and positive supply current sources PM , PI2, PI3 and PI4 all connected in parallel and each with a control input IB1 , IB2, IB3 and IB4, respectively. The signal inputs of inverters IV5 and IV2 are both connected to the common non-inverting input IN of the delay cell, and the signal inputs of inverters IV6 and IV1 are both connected to the common inverting input INB of the delay cell. On the output side, the signal outputs of inverters IV4 and IV6 are both connected to the common non-inverting signal output OUT of the delay cell, and the signal outputs of inverters IV3 and IV5 are both connected to the common inverting signal output OUTB of the delay cell.

The current sources PI1-PI4, NI1-NI4 and PJ1-PJ4, NJ1-NJ4 can be of identical strength or weighted in accordance with a predetermined scheme. The important aspect is that they can be selectively enabled or disabled by application of programmed signals IB1-IB4, NI1-NI4 and JB1- JB4, J1-J4.

The output stages are all similar. A straightforward implementation is shown in Fig. 4. Basically, it is a push-pull design with complementary transistors P1 and N1 and a series output resistor R1 connected between the interconnection node of transistors P1 and N1 and the signal output OUT. The gates of transistors P1 and N1 are driven by NAND gate NA1 and NOR gate NO1 , respectively, which have inputs connected to the signal input IN and the enable input ENB as shown in Fig. 4.

In the alternative embodiment of Fig. 5, several output stages which have their signal outputs connected to the common output OUT, have a common input signal but have separate enabling inputs. By enabling either just one or more than one of the output stages that have the same input signal, the driving strength (in terms of low output impedance) for a particular contribution to the overall output signal can be adjusted since the output resistors of all enabled output stages are connected in parallel.

In an actual application many of the drivers are implemented on a single die as an integrated CMOS circuit, for example to drive a series of DRAMs on different PC or server DIMM boards. There will be both differential and single-ended drivers on the same die, but all stages in the drivers will be matched. The drivers are spread all over the die. Given the high clock frequencies, e.g. 800 MHz, timing and signal specifications are problematic. However, by programming the current sources in each delay cell and by programming the enable inputs of the output stages in each driver, any driver can be adjusted to the needs of a particular DRAM as regards timing, slew rate and driving strength.

Fig. 7 illustrates different slew rate settings of a differential output signal at a given driver strength (20 Ohm in this case) that can be obtained by selective programming of the current sources in the delay cells. It should be noted that the complementary signals are perfectly matched. This is due to the extensive use of cross-coupling in the driver.

Claims

1. A driver for digital single-ended signals applied to RAM modules, comprising a chain of series-connected delay cells each with differential signal inputs and differential signal outputs; and a set of output stages each with a signal input, a single-ended signal output and an enable input; wherein: the signal outputs of the output stages are all connected to a common single-ended driver output and the signal inputs of the output stages are connected to signal outputs of different ones of the delay cells or to the signal input of the first delay cell in the chain, and the driver properties at the common driver output are digitally programmable by selectively applying enable signals to the enable inputs of the output stages.

2. A driver for digital complementary signals applied to RAM modules, comprising a chain of series-connected delay cells each with differential signal inputs and differential signal outputs; and two sets of output stages, each output stage with a signal input, a single-ended signal output and an enable input; wherein: the signal outputs of the output stages in the first set are all connected to a first common differential driver output and the signal inputs of the output stages in the first set are connected to signal outputs of different ones of the delay cells or to a signal input of the first delay cell in the chain,

the signal outputs of the output stages in the second set are all connected to a second common differential driver output and the signal inputs of the output stages in the second set are each connected to a signal output of a different one of the delay cells or to a signal input of the first delay cell in the chain,

and the driver properties at the first and second common differential driver outputs are digitally programmable by selectively applying enable signals to the enable inputs of the output stages.

3. A driver in accordance with claim 1 or claim 2, wherein the signal inputs of the output stages are alternately connected to different ones of the differential outputs of successive delay cells.

4. A driver in accordance with claims 1 and 3, wherein a dummy load is connected to outputs of the delay cells which have no connection to a signal input of an output stage.

5. A driver in accordance with claims 2 and 3, wherein the signal inputs of the output stages in the first set are connected to different ones of the differential outputs of associated delay cells than the signal inputs of corresponding output stages in the second set.

6. A driver according to any of the preceding claims, the delay cells comprising a first delay stage with two parallel inverters, one for each of the differential signals, and a second delay stage with two parallel paths each with two series-connected inverters; wherein: the differential signal inputs of the first delay stage are connected with corresponding differential signal inputs of the second delay stage and the differential signal outputs of the first delay stage are cross-coupled with corresponding differential signal outputs of the second delay stage; and the first and second delay stages each have a number of associated supply current sources that can be selectively activated or deactivated to digitally adjust the delay in each delay stage.

7. A driver according to any of the preceding claims, wherein the output stages comprise a complementary transistor pair mounted in a push-pull configuration.

8. A driver according to any of the preceding claims, wherein particular ones of the output stages receive the same input signal and different enable signals.

9. An integrated CMOS circuit comprising on a single die a plurality of drivers according to any of the preceding claims, wherein said drivers have matched output stages.