WO2008136646A1 - Multilayer substrate and electrical tester having the same - Google Patents
Multilayer substrate and electrical tester having the same Download PDFInfo
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- WO2008136646A1 WO2008136646A1 PCT/KR2008/002578 KR2008002578W WO2008136646A1 WO 2008136646 A1 WO2008136646 A1 WO 2008136646A1 KR 2008002578 W KR2008002578 W KR 2008002578W WO 2008136646 A1 WO2008136646 A1 WO 2008136646A1
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- Prior art keywords
- substrate
- dielectric constant
- printed pattern
- length
- sub
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- 239000000758 substrate Substances 0.000 title claims abstract description 310
- 239000000523 sample Substances 0.000 claims abstract description 26
- 230000005540 biological transmission Effects 0.000 claims description 52
- 238000012360 testing method Methods 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004804 winding Methods 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06772—High frequency probes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
Abstract
A multilayer substrate includes a first substrate and a second substrate. The first substrate has a first dielectric constant. The second substrate has a second dielectric constant different from the first dielectric constant. The first substrate and the second substrate are stacked with each other. Further, an electrical tester includes a first substrate, a second substrate and a connecting member. The first substrate has a plurality of probe tips configured to make contact with an object. The second substrate has a structure substantially the same as that of the multilayer substrate. The first substrate and the second substrate are electrically connected to each other through the connecting member.
Description
Description
MULTILAYER SUBSTRATE AND ELECTRICAL TESTER
HAVING THE SAME
Technical Field
[1] Example embodiments of the present invention relate to a multilayer substrate and an electrical tester having the same. More particularly, example embodiments of the present invention relate to a multilayer substrate making electrical contact with an object to test electrical characteristics of the object, and an electrical tester having the multilayer substrate. Background Art
[2] Generally, an electrical tester corresponds to a probe card. The electrical tester includes a first substrate having a plurality of probe tips that are configured to make contact with an object, such as a semiconductor substrate having a circuit pattern, a second substrate arranged to face the first substrate to receive electrical signals applied from the first substrate, and a connecting member for electrically connecting the first substrate with the second substrate.
[3] Therefore, in a process for testing electrical characteristics of the object using the electrical tester, the probe tips of the first substrate may make contact with the object. The electrical signals may be transmitted to the probe tips from the object. The electrical signals may then be transmitted to a test controller through the connecting member and the second substrate from the first substrate. In contrast, the electrical signals may be transmitted to the second substrate from the test controller. The electrical signals may then be transmitted to the probe tips through the connecting member and the first substrate.
[4] Here, it may be required to provide the electrical signals, which are transmitted to the probe tips from the test controller or to the test controller from the probe tips, with substantially the same transmission speed. That is, each of the electrical signals may be transmitted to the probe tips from the test controller at substantially the same transmission speed. Further, each of the electrical signals may be transmitted to the test controller from the probe tips at substantially the same transmission speed.
[5] Printed patterns in the first substrate may be configured to have the shortest distance.
Further, sub-substrates in the second substrate may be stacked with each other to have a multilayer structure. Here, the sub-substrates in the second substrate may have substantially the same dielectric constant.
[6] As mentioned above, since the printed patterns in the first substrate have the shortest distance and the sub-substrates in the second substrate have substantially the same di-
electric constant, printed patterns in the second substrate may have a winding structure that is not the shortest distance, so as to transmit the electrical signals to the first substrate or the test controller at substantially the same transmission speed. This may be caused by different transmission speeds of the electrical signals passing through the printed patterns in the first substrate having the shortest distance. In order to provide the electrical signals, which have the different transmission speeds after passing through the printed patterns in the first substrate, with substantially the same transmission speed, it may be required to form the printed patterns to have a winding structure in the second substrate. In other words, according to a conventional technique, the electrical signals having the different transmission speeds may be provided with substantially the same transmission speeds by controlling lengths of the printed patterns in the second substrate.
[7] In a conventional electrical test, the winding printed patterns in the second substrate may cause low test reliability. Further, since it may be very difficult to control the lengths of the printed patterns in the second substrate, the productivity of the conventional electrical test may be reduced. Disclosure of Invention Technical Problem
[8] Example embodiments of the present invention provide a multilayer substrate having printed patterns that have substantially the same shortest length.
[9] Example embodiments of the present invention also provide an electrical tester having the above-mentioned multilayer substrate. Technical Solution
[10] A multilayer substrate in accordance with one aspect of the present invention includes a first substrate and a second substrate. The first substrate has a first dielectric constant. The second substrate has a second dielectric constant different from the first dielectric constant. The first substrate and the second substrate are stacked with each other.
[11] A multilayer substrate in accordance with another aspect of the present invention includes a first substrate, a second substrate, a first printed pattern and a second printed pattern. The first substrate has a first surface and a second surface opposite to the first surface. First terminals for allowing electrical signals to pass through the first terminals are formed on the first surface. Further, the first substrate has a first dielectric constant. The second substrate has a third surface and a fourth surface opposite to the third surface. Second terminals for allowing electrical signals to pass through the second terminals are formed on the third surface. Further, the second substrate has a second dielectric constant different from the first dielectric constant. The first printed pattern is
arranged on the first substrate. The first printed pattern is electrically connected to any one of the first terminals and any one of the second terminals. Further, the first printed pattern has a first length. The second printed pattern is arranged on the second substrate. The second printed pattern is electrically connected to another first terminal and another second terminal. Further, the second printed pattern has a second length. The first substrate and the second substrate are sequentially stacked to contact the second surface of the first substrate and the fourth surface of the second substrate with each other.
[12] An electrical tester in accordance with still another aspect of the present invention includes a first substrate, a second substrate and a connecting member. The first substrate has a plurality of probe tips configured to make contact with an object. The second substrate includes a first sub-substrate and a second sub-substrate stacked sequentially. The first sub-substrate has a first dielectric constant. The second sub- substrate has a second dielectric constant different from the first dielectric constant. The first substrate and the second substrate are electrically connected to each other through the connecting member.
[13] An electrical tester in accordance with yet still another aspect of the present invention includes a first substrate, a second substrate and a connecting member. The first substrate has a first surface and a second surface opposite to the first surface. A plurality of probe tips configured to make contact with an object is arranged on the first surface of the first substrate. Pads for receiving electrical signals from the probe tips are arranged on the second surface of the first substrate. The second substrate includes a first sub-substrate, a second sub-substrate, a first printed pattern and a second printed pattern. The first sub-substrate has a first surface and a second surface opposite to the first surface. First terminals for allowing the electrical signals to pass through the first terminals are formed on the first surface of the first sub-substrate. Further, the first sub-substrate has a first dielectric constant. The second sub-substrate has a third surface and a fourth surface opposite to the third surface. Second terminals for allowing the electrical signals to pass through the second terminals are formed on the third surface. Further, the second sub-substrate has a second dielectric constant different from the first dielectric constant. The first printed pattern is arranged on the first sub-substrate. The first printed pattern is electrically connected to any one of the first terminals and any one of the second terminals. Further, the first printed pattern has a first length. The second printed pattern is arranged on the second sub-substrate. The second printed pattern is electrically connected to another first terminal and another second terminal. Further, the second printed pattern has a second length. The first sub- substrate and the second sub-substrate are sequentially stacked to contact the second surface of the first sub-substrate and the fourth surface of the second sub-substrate with
each other. The pads of the first substrate and the first terminals of the second substrate are electrically connected to each other through the connecting member.
[14] According to one example embodiment, when the first dielectric constant is higher than the second dielectric constant, the first length may be shorter than the second length. In contrast, when the first dielectric constant is lower than the second dielectric constant, the first length may be longer than the second length.
[15] Further, the first dielectric constant and the second dielectric constant may be determined in accordance with transmission speeds of the electrical signals passing through the first printed pattern and the second printed pattern. Here, when the transmission speed of the electrical signal transmitted to the first printed pattern is faster than that transmitted to the second printed pattern, the first dielectric constant may be higher than the second dielectric constant. In contrast, when the transmission speed of the electrical signal transmitted to the first printed pattern is slower than that transmitted to the second printed pattern, the first dielectric constant may be lower than the second dielectric constant.
[16] Furthermore, the first length, the second length, the first dielectric constant and the second dielectric constant may be determined in accordance with transmission speeds of the electrical signals passing through the first printed pattern and the second printed pattern. Here, when the transmission speed of the electrical signal transmitted to the first printed pattern is faster than that transmitted to the second printed pattern, the first dielectric constant may be higher than the second dielectric constant, the first length may be shorter than the second length or the first dielectric constant may be higher than the second dielectric constant with the first length being shorter than the second length. In contrast, when the transmission speed of the electrical signal transmitted to the first printed pattern is slower than that transmitted to the second printed pattern, the first dielectric constant may be lower than the second dielectric constant, the first length may be longer than the second length or the first dielectric constant may be lower than the second dielectric constant with the first length being longer than the second length.
Advantageous Effects
[17] According to the present invention, a multilayer substrate may include substrates having different dielectric constants. Further, an electrical tester may include the multilayer substrate having the substrates that have different dielectric constants. Thus, although printed patterns in the multilayer substrate and the electrical tester may have the shortest lengths, electrical signals having different transmission speeds may be provided with substantially the same transmission speed. Brief Description of the Drawings
[18] The above and other features and advantages of the invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
[19] FIG. 1 is a cross-sectional view illustrating a multilayer substrate in accordance with one example embodiment of the present invention; and
[20] FIG. 2 is a cross-sectional view illustrating an electrical tester having the multilayer substrate in FIG. 1. Best Mode for Carrying Out the Invention
[21] The present invention is described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the present invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
[22] It will be understood that when an element or layer is referred to as being "on" or
"connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[23] It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
[24] Spatially relative terms, such as "lower," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath"
other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[25] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[26] Example embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, example embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
[27] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[28]
[29] Multilayer substrate
[30] FIG. 1 is a cross-sectional view illustrating a multilayer substrate in accordance with one example embodiment of the present invention.
[31] Referring to FIG. 1, a multilayer substrate 100 includes a first substrate 11 and a second substrate 13. In this example embodiment, the first substrate 11 and the second substrate 13 may have different dielectric constants. Particularly, the first substrate 11 may have a first dielectric constant. In contrast, the second substrate 13 may have a second dielectric constant different from the first dielectric constant. The first substrate
11 and the second substrate 13 may be sequentially stacked to manufacture the multilayer substrate 100.
[32] Here, in this example embodiment, the multilayer substrate 100 may include the first substrate 11 and the second substrate 13. Alternatively, the multilayer substrate 100 may include at least three substrates having different dielectric constants.
[33] The first substrate 11 has a first surface 11a and a second surface 1 Ib opposite to the first surface 11a. First terminals 15a and 15b are formed on the first surface 11a. Electrical signals may be transmitted through the first terminals 15a and 15b. Here, in this example embodiment, the two first terminals 15a and 15b may be arranged on the first surface 11a. Alternatively, at least three first terminals may be arranged on the first surface 11a. The second substrate 13 has a third surface 13a and a fourth surface 13b. Second terminals 17a and 17b are formed on the third surface 13a. Electrical signals may be transmitted through the second terminals 17a and 17b. The fourth surface 13b is opposite to the third surface 13a. Here, in this example embodiment, the two second terminals 17a and 17b may be arranged on the third surface 13a. Further, the numbers of the first terminals 15a and 15b may be equal to those of the second terminals 17a and 17b on the third surface 13a of the second substrate 13. That is, the first terminals 15a and 15b and the second terminals 17a and 17b may be electrically connected to each other in one-to-one correspondence.
[34] Further, the second surface 1 Ib of the first substrate 11 may make contact with the fourth surface 13b of the second substrate 13.
[35] Additionally, the multilayer substrate 100 may include a first printed pattern 19a and a second printed pattern 19b. The first printed pattern 19a may be connected between any one 15a of the first terminals 15a and 15b on the first surface 1 Ia of the first substrate 11 and any one 17a of the second terminals 17a and 17b on the third surface 13a of the second substrate 13. The second printed pattern 19b may be connected between another first terminal 15b on the first surface 1 Ia of the first substrate 11 and another second terminal 17b on the third surface 13a of the second substrate 13. In this example embodiment, a portion of the first printed pattern 19a in the first substrate 11 may have a first length 11. A portion of the second printed pattern 19b in the second substrate 13 may have a second length 12.
[36] Particularly, the first length 11 of the first printed pattern 19a and the second length 12 of the second printed pattern 19b may be determined in accordance with the first dielectric constant of the first substrate 11 and the second dielectric constant of the second substrate 13 and / or transmission speeds of the electrical signals passing through the first printed pattern 19a and the second printed pattern 19b. Here, an electronic transmission speed may be inversely proportional to a square root of a dielectric constant as a following formula 1. Thus, when the dielectric constant is
relatively higher, the electronic transmission speed may become slower. In contrast, when the dielectric constant is relatively lower, the electronic transmission speed may become faster. Therefore, the electrical signals having different transmission speeds may be provided with substantially the same transmission speed by providing the printed patterns with short lengths in case that the dielectric constant is relatively higher, or with long lengths in case that the dielectric constant is relatively lower. [37] Formula 1
[39] In the formula 1, Vp indicates the electronic transmission speed, C represents the velocity of the light, and εr indicates the dielectric constant.
[40] Therefore, when the first dielectric constant of the first substrate 11 is higher than the second electric constant of the second substrate 13, the first length 11 of the first printed pattern 19a may be shorter than the second length 12 of the second printed pattern 19b. In contrast, when the first dielectric constant of the first substrate 11 is lower than the second electric constant of the second substrate 13, the first length 11 of the first printed pattern 19a may be longer than the second length 12 of the second printed pattern 19b.
[41] Further, when the transmission speed of the electrical signal passing through the second printed pattern 19b is slower than that passing through the first printed pattern 19a, the second dielectric constant of the second substrate 13 may be higher than the first dielectric constant of the first substrate 11. In contrast, when the transmission speed of the electrical signal passing through the second printed pattern 19b is faster than that passing through the first printed pattern 19a, the second dielectric constant of the second substrate 13 may be lower than the first dielectric constant of the first substrate 11.
[42] In this example embodiment, to provide the first printed pattern 19a and the second printed pattern 19b with the shortest lengths, the portion of the first printed pattern 19a in the first substrate 11 and the portion of the second printed pattern 19b in the second substrate 13 may be arranged in parallel with lengthwise directions of the first substrate 11 and the second substrate 13. In this example embodiment, the portion of the first printed pattern 19a in the first substrate 11 and the portion of the second printed pattern 19b in the second substrate 13 may be arranged in a horizontal direction.
[43]
[44] Measuring transmission speeds of electrical signals
[45] A first substrate, a second substrate, a third substrate and a fourth substrate were sequentially stacked to form a multilayer substrate. Further, a first printed pattern, a
second printed pattern, a third printed pattern and a fourth printed pattern were built into the multilayer substrate. Here, the first substrate had a dielectric constant of about 4.2. The second substrate had a dielectric constant of about 3.8. The third substrate had a dielectric constant of about 3.5. The fourth substrate had a dielectric constant of about 3.2. Further, a portion of the first printed pattern in the first substrate had a length of about 220 mm. A portion of the second printed pattern in the second substrate had a length of about 230 mm. A portion of the third printed pattern in the third substrate had a length of about 240 mm. A portion of the fourth printed pattern in the fourth substrate had a length of about 250 mm. Transmission speeds of electrical signals passing through the first printed pattern, the second printed pattern, the third printed pattern and the fourth printed pattern, respectively, were measured.
[46] Measured transmission speeds of the electrical signals passing through the first printed pattern, the second printed pattern, the third printed pattern and the fourth printed pattern were 1,502 ps, 1,494 ps, 1,496 ps and 1,490 ps, respectively. Therefore, it can be noted that a deviation of the measured transmission speeds of the electrical signals was within an allowable range of about 12 ps.
[47] According to this example embodiment, the multilayer substrate may include the sequentially stacked substrates having different dielectric constants. Thus, the printed patterns in the multilayer substrate may mostly have a linear shape with the shortest lengths. As a result, in the multilayer substrate, increases in resistance and inductance caused by arrangements of printed patterns may be sufficiently suppressed. Further, the printed patterns may be readily arranged in the multilayer substrate owing to the shortest lengths of the printed patterns.
[48]
[49] Electrical tester
[50] FIG. 2 is a cross-sectional view illustrating an electrical tester having the multilayer substrate in FIG. 1.
[51] Referring to FIG. 2, an electrical tester 200 may correspond to a probe card. The electrical tester 200 of this example embodiment includes a first substrate 20, a second substrate 100 and a connecting member 30. Additionally, although not depicted in the drawing, the electrical tester 200 may further include a combining member (not shown) for combining the first substrate 20 and the second substrate 100 with each other, an adjusting member (not shown) for adjusting a horizontal level of the first substrate 20 and the second substrate 100, and a reinforcing member (not shown) for structurally reinforcing the first substrate 20 and the second substrate 100.
[52] The first substrate 20 may correspond to a microprobe head (MPH), a space transformer, etc. The first substrate 20 has a first surface and a second surface opposite to the first surface. Probe tips 22 configured to make contact with an object such as a
semiconductor substrate having a circuit pattern are arranged on the first surface of the first substrate 20. Pads 24 for receiving electrical signals applied to the probe tips 22 are arranged on the second surface of the first substrate 20. The electrical signals may be transmitted to the pads 24 from the probe tips 22 by contacting the probe tips 22 to the object. Thus, printed patterns 26a and 26b through which the electrical signals pass from the probe tips 22 to the pads 24 may be built into the first substrate 20. In this example embodiment, the printed patterns 26a and 26b may have the shortest lengths.
[53] The second substrate 100 may correspond to a printed circuit board (PCB). The second substrate 100 may face the second surface of the first substrate 20.
[54] Here, the second substrate 100 may be substantially the same as the multilayer substrate in FIG. 1. The second substrate 100 includes a first sub-substrate 11 and a second sub-substrate 13. The first sub-substrate 11 has a first surface and a second surface opposite to the first surface. First terminals 15a and 15b are formed on the first surface of the first sub-substrate 11. The electrical signals may be transmitted through the first terminals. The first sub-substrate 11 has a first dielectric constant. The second sub-substrate 13 has a third surface and a fourth surface opposite to the third face. Second terminals 17a and 17b are formed on the third surface. Electrical signals may be transmitted through the second terminals 17a and 17b. The second sub-substrate 13 has a second dielectric constant different from the first dielectric constant. The first sub-substrate 11 and the second sub-substrate 13 are sequentially stacked to contact the second surface of the first sub-substrate 11 and the fourth surface of the second sub- substrate 13 to each other. Additionally, the second substrate may include a first printed pattern 19a and a second printed pattern 19b. The first printed pattern 19a may be connected between any one 15a of the first terminals 15a and 15b on the first surface of the first sub-substrate 11 and any one 17a of the second terminals 17a and 17b on the third surface of the second sub-substrate 13. The second printed pattern 19b may be connected between another first terminal 15b on the first surface of the first sub-substrate 11 and another second terminal 17b on the third surface of the second sub-substrate 13. In this example embodiment, a portion of the first printed pattern 19a in the first sub-substrate 11 may have a first length 11. A portion of the second printed pattern 19b in the second sub-substrate 13 may have a second length 12.
[55] Here, in this example embodiment, the second substrate 100 may include the first sub-substrate 11 and the second sub-substrate 13. Alternatively, the second substrate 100 may include at least three substrates having different dielectric constants.
[56] That is, the second substrate 100 of this example embodiment may include same elements substantially the same as those of the multilayer substrate in FIG. 1 except that the first substrate and the second substrate in FIG. 1 are named as the first sub- substrate and the second sub-substrate in FIG. 2, respectively. Thus, any further illus-
trations with respect to the same elements are omitted herein for brevity.
[57] Here, the second substrate 100 may have a structure for receiving the electrical signals applied from the pads 24 on the second surface of the first substrate 20.
[58] Therefore, in a process for testing electrical characteristics of the object using the electrical tester 200, the probe tips 22 of the first substrate 20 may make contact with the object. The electrical signals may be transmitted to the probe tips 22 from the object. The electrical signals may then be transmitted to a test controller (not shown) through the second substrate 100 from the first substrate 20.
[59] The electrical tester 200 may further include the connecting member 30. The connecting member 30 is connected between the pads 24 on the second surface of the first substrate 20 and the first terminals 15a and 15b on the first surface of the second substrate 100. In this example embodiment, the connecting member 30 may have a structure and a material for sufficiently reducing a vertical pressure applied to the first substrate 20 to prevent the first substrate 20 from being bent. As a result, the connecting member 30 may function as to provide the first substrate 20 with a uniform horizontal level.
[60] As mentioned above, the electrical tester 200 of this example embodiment includes the first substrate 20, the second substrate 100 and the connecting member 30.
[61] When an electrical test may be performed using the electrical tester 200, transmission speeds of the electrical signals transmitted to the pads 24 of the first substrate 20 from the probe tips 22 that make contact with the object may be different from each other, because the printed patterns 26a and 26b in the first substrate 20 connected between the pads 24 and the probe tips 22 have the shortest lengths.
[62] Thus, the electrical signals having the different transmission speeds may be transmitted to the first terminals 15a and 15b of the second substrate 100 from the first substrate 20 through the connecting member 30. Here, when the electrical signals having the different transmissions speeds may be directly transmitted to the test controller, test results may have low reliability. Accordingly, it may be required to provide the electrical signals having the different transmission speeds with substantially the same transmission speed in the second substrate 100.
[63] In the electrical tester 200 of this example embodiment, the first sub-substrate 11 and the second sub-substrate 13 of the second substrate 100 substantially the same as the multilayer substrate in FIG. 1 may have different dielectric constants. Further, the first length of the first printed pattern 19a and the second length of the second printed pattern 19b may be determined in accordance with the dielectric constants. In this example embodiment, the first printed pattern 19a and the second printed pattern 19b may be partially arranged in parallel with each other with the shortest lengths.
[64] As mentioned above, while the electrical signals having the different transmission
speeds pass through the second substrate 100, the electrical signals may be provided with substantially the same transmission speed by properly determining the first length of the first printed pattern 19a and the second length of the second printed pattern 19b in accordance with the dielectric constants of the first substrate 20 and the second substrate 100, although the electrical signals having the different transmission speeds are transmitted to the second substrate 100. This may be achieved by applying the electronic transmission speed inversely proportional to the square root of the dielectric constant illustrated with reference to FIG. 1. Industrial Applicability
[65] According to the present invention, a multilayer substrate and an electrical tester may include printed patterns having the shortest lengths and a linear shape. Thus, increases in resistance and inductance caused by arrangements of printed patterns may be sufficiently suppressed.
[66] Further, the multilayer substrate and the electrical tester may prevent signal distortions caused by the arrangements of the printed patterns. As a result, the reliability of test results may be improved regardless of operational frequencies.
[67] Furthermore, the printed patterns may be readily arranged in the multilayer substrate owing to the shortest lengths of the printed patterns. As a result, productivities of the multilayer substrate and the electrical tester may be increased.
[68] Having described the preferred embodiments of the present invention, it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiment of the present invention disclosed which is within the scope and the spirit of the invention outlined by the appended claims.
Claims
[1] A multilayer substrate for an electrical tester, comprising: a first substrate having a first dielectric constant; a second substrate stacked on the first substrate, the second substrate having a second dielectric constant different from the first dielectric constant.
[2] The multilayer substrate of claim 1, wherein the first substrate and the second substrate comprise a printed circuit board (PCB).
[3] A multilayer substrate for an electrical tester, comprising: a first substrate having a first surface on which first terminals for allowing electrical signals to pass through the first terminals are arranged and a second surface opposite to the first surface, the first substrate having a first dielectric constant; a second substrate having a third surface on which second terminals for allowing the electrical signals to pass through the second terminals are arranged and a fourth surface opposite to the third surface, wherein the second substrate is stacked on the first substrate to contact the fourth surface of the second substrate to the second surface of the first substrate and the second substrate has a second dielectric constant different from the first dielectric constant; a first printed pattern connected between any one of the first terminals and any one of the second terminals, the first printed pattern having a portion in the first substrate that has a first length; and a second printed pattern connected between another first terminal and another second terminal, the second printed pattern having a portion in the second substrate that has a second length.
[4] The multilayer substrate of claim 3, wherein the first length is shorter than the second length when the first dielectric constant is higher than the second dielectric constant.
[5] The multilayer substrate of claim 3, wherein the first length is longer than the second length when the first dielectric constant is lower than the second dielectric constant.
[6] The multilayer substrate of claim 3, wherein the portion of the first printed pattern in the first substrate and the portion of the second printed pattern in the second substrate are parallel with each other along lengthwise directions of the first substrate and the second substrate.
[7] The multilayer substrate of claim 3, wherein the first dielectric constant and the second dielectric constant are determined in accordance with transmission speeds of electrical signals passing through the first printed pattern and the second
printed pattern.
[8] The multilayer substrate of claim 7, wherein the first dielectric constant is higher than the second dielectric constant when the transmission speed of the electrical signal transmitted to the first printed pattern is faster than that transmitted to the second printed pattern.
[9] The multilayer substrate of claim 7, wherein the first dielectric constant is lower than the second dielectric constant when the transmission speed of the electrical signal transmitted to the first printed pattern is slower than that transmitted to the second printed pattern.
[10] The multilayer substrate of claim 3, wherein the first length, the second length, the first dielectric constant and the second dielectric constant are determined in accordance with transmission speeds of electrical signals passing through the first printed pattern and the second printed pattern.
[11] The multilayer substrate of claim 10, wherein the first dielectric constant is higher than the second dielectric constant, the first length is longer than the second length or the first length is longer than the second length with the first dielectric constant being higher than the second dielectric constant, when the transmission speed of the electrical signal transmitted to the first printed pattern is faster than that transmitted to the second printed pattern.
[12] The multilayer substrate of claim 10, wherein the first dielectric constant is lower than the second dielectric constant, the first length is shorter than the second length or the first length is shorter than the second length with the first dielectric constant being lower than the second dielectric constant, when the transmission speed of the electrical signal transmitted to the first printed pattern is slower than that transmitted to the second printed pattern.
[13] An electrical tester comprising: a first substrate having probe tips that make contact with an object; a second substrate including a first sub-substrate and a second sub-substrate sequentially stacked, the first sub-substrate having a first dielectric constant and the second sub-substrate having a second dielectric constant different from the first dielectric constant; and a connecting member for electrically connecting the first substrate and the second substrate with each other.
[14] An electrical tester comprising: a first substrate having a first surface and a second surface opposite to the first surface, the first surface having probe tips that make contact with an object and the second surface having pads for receiving electrical signals applied by contacting the probe tips to the object;
a second substrate including a first sub-substrate, a second sub-substrate, a first printed pattern and a second printed pattern, the first sub-substrate having a first surface on which first terminals for allowing electrical signals to pass through the first terminals are arranged and a second surface opposite to the first surface, the first sub-substrate having a first dielectric constant; a second sub-substrate having a third surface on which second terminals for allowing the electrical signals to pass through the second terminals are arranged and a fourth surface opposite to the third surface, wherein the second substrate is stacked on the first substrate to contact the fourth surface of the second sub- substrate to the second surface of the first sub-substrate and the second sub- substrate has a second dielectric constant different from the first dielectric constant; a first printed pattern connected between any one of the first terminals and any one of the second terminals, the first printed pattern having a portion in the first sub-substrate that has a first length; and a second printed pattern connected between another first terminal and another second terminal, the second printed pattern having a portion in the second sub- substrate that has a second length; and a connecting member for electrically connecting the pads of the first substrate and the first terminals of the second substrate with each other.
[15] The electrical tester of claim 14, wherein the first length is shorter than the second length when the first dielectric constant is higher than the second dielectric constant, and the first length is longer than the second length when the first dielectric constant is lower than the second dielectric constant.
[16] The electrical tester of claim 14, wherein the first dielectric constant and the second dielectric constant are determined in accordance with transmission speeds of electrical signals passing through the first printed pattern and the second printed pattern.
[17] The electrical tester of claim 16, wherein the first dielectric constant is higher than the second dielectric constant when the transmission speed of the electrical signal transmitted to the first printed pattern is faster than that transmitted to the second printed pattern, and the first dielectric constant is lower than the second dielectric constant when the transmission speed of the electrical signal transmitted to the first printed pattern is slower than that transmitted to the second printed pattern.
[18] The electrical tester of claim 14, wherein the first length, the second length, the first dielectric constant and the second dielectric constant are determined in ac-
cordance with transmission speeds of electrical signals passing through the first printed pattern and the second printed pattern.
[19] The electrical tester of claim 18, wherein the first dielectric constant is higher than the second dielectric constant, the first length is longer than the second length or the first length is longer than the second length with the first dielectric constant being higher than the second dielectric constant, when the transmission speed of the electrical signal transmitted to the first printed pattern is faster than that transmitted to the second printed pattern, and the first dielectric constant is lower than the second dielectric constant, the first length is shorter than the second length or the first length is shorter than the second length with the first dielectric constant being lower than the second dielectric constant, when the transmission speed of the electrical signal transmitted to the first printed pattern is slower than that transmitted to the second printed pattern.
[20] The electrical tester of claim 14, wherein the transmission speeds of the electrical signals passing through the first printed pattern and the second printed pattern are different from each other.
[21] The electrical tester of claim 14, wherein the portion of the first printed pattern in the first sub-substrate and the portion of the second printed pattern in the second sub-substrate are parallel with each other along lengthwise directions of the first sub-substrate and the second sub-substrate.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2007-0044676 | 2007-05-08 | ||
KR1020070044676A KR100904388B1 (en) | 2007-05-08 | 2007-05-08 | Multi layer board and apparatus for inspecting electric condition having the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008136646A1 true WO2008136646A1 (en) | 2008-11-13 |
Family
ID=39943699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/KR2008/002578 WO2008136646A1 (en) | 2007-05-08 | 2008-05-08 | Multilayer substrate and electrical tester having the same |
Country Status (3)
Country | Link |
---|---|
KR (1) | KR100904388B1 (en) |
TW (1) | TW200907381A (en) |
WO (1) | WO2008136646A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI455222B (en) * | 2011-08-25 | 2014-10-01 | Chipmos Technologies Inc | Testing method for stacked semiconductor device structure |
JP7101457B2 (en) * | 2017-04-13 | 2022-07-15 | 株式会社日本マイクロニクス | Electrical connection device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06302964A (en) * | 1993-04-16 | 1994-10-28 | Oki Electric Ind Co Ltd | Circuit board for high-speed signal transmission |
JPH07212047A (en) * | 1994-01-20 | 1995-08-11 | Fujitsu General Ltd | Multilayer board of low permittivity |
KR20070026632A (en) * | 2004-05-24 | 2007-03-08 | 동경 엘렉트론 주식회사 | Laminated board and probe card |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR200200204Y1 (en) * | 2000-05-15 | 2000-10-16 | 김영배 | Multi-layer substrate structure using double materials |
KR100607568B1 (en) * | 2004-08-09 | 2006-08-02 | 전자부품연구원 | Method for manufacturing multilayer substrate using dissimilar dielectric material |
-
2007
- 2007-05-08 KR KR1020070044676A patent/KR100904388B1/en not_active IP Right Cessation
-
2008
- 2008-05-08 TW TW097116981A patent/TW200907381A/en unknown
- 2008-05-08 WO PCT/KR2008/002578 patent/WO2008136646A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06302964A (en) * | 1993-04-16 | 1994-10-28 | Oki Electric Ind Co Ltd | Circuit board for high-speed signal transmission |
JPH07212047A (en) * | 1994-01-20 | 1995-08-11 | Fujitsu General Ltd | Multilayer board of low permittivity |
KR20070026632A (en) * | 2004-05-24 | 2007-03-08 | 동경 엘렉트론 주식회사 | Laminated board and probe card |
Also Published As
Publication number | Publication date |
---|---|
KR20080099057A (en) | 2008-11-12 |
TW200907381A (en) | 2009-02-16 |
KR100904388B1 (en) | 2009-06-26 |
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