WO2008126270A1 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

Info

Publication number
WO2008126270A1
WO2008126270A1 PCT/JP2007/057158 JP2007057158W WO2008126270A1 WO 2008126270 A1 WO2008126270 A1 WO 2008126270A1 JP 2007057158 W JP2007057158 W JP 2007057158W WO 2008126270 A1 WO2008126270 A1 WO 2008126270A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
semiconductor integrated
wirings
pitch
transistors
Prior art date
Application number
PCT/JP2007/057158
Other languages
French (fr)
Japanese (ja)
Inventor
Hiroshi Katakura
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/057158 priority Critical patent/WO2008126270A1/en
Publication of WO2008126270A1 publication Critical patent/WO2008126270A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A semiconductor integrated circuit composed of logical cells including transistors and wirings has a structure in which the layout of the transistors and wirings along a second direction perpendicular to a first direction along the array of the source, gate, and drain of each transistor is designed with a reference of the pitch of the wiring, and the layout of the transistors along the first direction is designed with a reference of the bulk pitch larger by a predetermined ratio than the pitch of the wirings.
PCT/JP2007/057158 2007-03-30 2007-03-30 Semiconductor integrated circuit WO2008126270A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/057158 WO2008126270A1 (en) 2007-03-30 2007-03-30 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/057158 WO2008126270A1 (en) 2007-03-30 2007-03-30 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
WO2008126270A1 true WO2008126270A1 (en) 2008-10-23

Family

ID=39863450

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/057158 WO2008126270A1 (en) 2007-03-30 2007-03-30 Semiconductor integrated circuit

Country Status (1)

Country Link
WO (1) WO2008126270A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103299423A (en) * 2011-01-11 2013-09-11 高通股份有限公司 Standard cell architecture using double poly patterning for multi VT devices
CN109564893A (en) * 2016-08-01 2019-04-02 株式会社索思未来 Semiconductor chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6143467A (en) * 1984-08-08 1986-03-03 Fujitsu Ltd Semiconductor device
JPH02270372A (en) * 1989-04-11 1990-11-05 Seiko Epson Corp Basic cell circuit
JP2004342757A (en) * 2003-05-14 2004-12-02 Toshiba Corp Semiconductor integrated circuit and method of designing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6143467A (en) * 1984-08-08 1986-03-03 Fujitsu Ltd Semiconductor device
JPH02270372A (en) * 1989-04-11 1990-11-05 Seiko Epson Corp Basic cell circuit
JP2004342757A (en) * 2003-05-14 2004-12-02 Toshiba Corp Semiconductor integrated circuit and method of designing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103299423A (en) * 2011-01-11 2013-09-11 高通股份有限公司 Standard cell architecture using double poly patterning for multi VT devices
JP2014507067A (en) * 2011-01-11 2014-03-20 クアルコム，インコーポレイテッド Standard cell architecture using double polyline patterning for devices with multiple voltage thresholds
KR101538350B1 (en) * 2011-01-11 2015-07-22 퀄컴 인코포레이티드 Standard cell architecture using double poly patterning for multi vt devices
JP2015156517A (en) * 2011-01-11 2015-08-27 クアルコム，インコーポレイテッド Method of fabricating devices associated with standard cell architecture
CN109564893A (en) * 2016-08-01 2019-04-02 株式会社索思未来 Semiconductor chip
CN109564893B (en) * 2016-08-01 2022-11-25 株式会社索思未来 Semiconductor chip

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